JPS5929477A - Light-emitting element - Google Patents

Light-emitting element

Info

Publication number
JPS5929477A
JPS5929477A JP57139363A JP13936382A JPS5929477A JP S5929477 A JPS5929477 A JP S5929477A JP 57139363 A JP57139363 A JP 57139363A JP 13936382 A JP13936382 A JP 13936382A JP S5929477 A JPS5929477 A JP S5929477A
Authority
JP
Japan
Prior art keywords
semiconductor layer
light
semiconductor
type
approximately
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57139363A
Other languages
Japanese (ja)
Inventor
Kenichi Kasahara
健一 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57139363A priority Critical patent/JPS5929477A/en
Publication of JPS5929477A publication Critical patent/JPS5929477A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004Devices characterised by their operation
    • H01L33/002Devices characterised by their operation having heterojunctions or graded gap
    • H01L33/0025Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain the light-emitting element having a light-emitting diode and its driving element monolithicly integrated on the semiconductor substrate using the material of InGaAsP mixed crystal whereon a high resistivity semiconductor layer is hardly formed. CONSTITUTION:On both sides of an N type InP semiconductor substrate 31, the second semiconductor layers 321 and 322 of approximately 2 mum in thickness consisting of N type InP, the third semiconductor layers 331 and 332 of approximately 2mum in thickness consisting of N type InP, the third semiconductor layers 331 and 332 of approximately 1mum in thickness consisting of In1-xGaxAsyP1-y,the fourth semiconductor layers 341 and 342 of approximately 1mum in thickness consisting of P type InP, and the fifth semiconductor layers 351 and 352 of approximately 1mum in thickness consisting of N type In1-zGazAswP1-w are formed by performing a vapor-phase growing method. When a positive voltage is applied to an electrode 38, electrons are induced on the interface where the P type semiconductor layer 342 and an insulating from 37 come in contact with each other, an electron current runs from an electrode 39 and along the interface of the insulating film and the semiconductor layer, and the electrons are injected to the semiconductor layer 331 of a light-emitting part 21 which is an active layer. Also, a hole current runs from an electrode 42 through an impurity diffusion layer 40, said hole current is injected to the semiconductor layer 331, a light emission is generated by the recoupling of the electron and the light is picked up to outside.

Description

【発明の詳細な説明】 本発明は発光ダイオードとその駆動素子を同一半導体基
板上にモノリシックに集積した)Y; J’、rl、 
(i用発光素子に関するものである。
[Detailed Description of the Invention] The present invention monolithically integrates a light emitting diode and its driving element on the same semiconductor substrate)Y; J', rl,
(Regarding the light emitting element for i.

発光ダイオードは低伝送損失光ファイバを用いた光通信
用の安価な光源として既に実用されているが、更に同一
半導体基板上にその駆動素子を集積化ずれば製造コスト
も下がり装置も小ハリ化される。一方発光クイオードな
どの光半導体素子をfil産するために気相成長法等の
結晶成長技術が開発されつつあるが、本発明になる発光
素子はこれ73(らの成長技術の特徴を活かして製造す
るものである。
Light-emitting diodes are already in practical use as inexpensive light sources for optical communications using low-transmission-loss optical fibers, but if the driving elements are integrated on the same semiconductor substrate, manufacturing costs can be reduced and the device can also be made smaller. Ru. On the other hand, crystal growth techniques such as vapor phase growth are being developed to produce optical semiconductor devices such as light-emitting diodes. It is something to do.

発光ダイオードと駆動素子を集積化した発光素子として
は従来、例えば第1図の様なものが知られている。
As a light emitting element in which a light emitting diode and a driving element are integrated, for example, a light emitting element as shown in FIG. 1 is known.

第1図は(JaAlAsloaAs ダブルへテロ構造
の発光ダイオードと1(j界効果トランジスターを集積
化したものの断面図であり、13が活性半導体層、12
はIt型クりッド層、14はp型クラッド層であり、そ
れぞれ1)型U;Io9A/?o、+As、 n型Ua
 o7hl o3As 1p型(Ja 0.7AeO,
3AFlからなっている。15は!]型(hA、s。
FIG. 1 is a cross-sectional view of a light emitting diode with a double heterostructure (JaAlAsloaAs) integrated with a field effect transistor (1), in which 13 is an active semiconductor layer, 12
is an It-type cladding layer, and 14 is a p-type cladding layer, each of which is 1) type U; Io9A/? o, +As, n-type Ua
o7hl o3As 1p type (Ja 0.7AeO,
It consists of 3AFl. 15 is! ] type (hA, s.

16は高い抵抗率を有するノンドープのOa O,7A
10.3ASからなるアイソレーション層である。17
は11型GaAs118はAuGe −N iの1・゛
レイン電極、19はA、1のゲート電極、23及び24
はソース11イ極でソース電極おの部分はkuGe −
N i 1 ソース′航極24の部分はA、11/Zn
/Auよりなる。又11はn 4F、’J−GaAsの
半導体基板、25はAuGe−Niの1W極、である。
16 is non-doped OaO, 7A with high resistivity
This is an isolation layer consisting of 10.3AS. 17
is 11 type GaAs118 is AuGe-Ni 1・rain electrode, 19 is A, 1 gate electrode, 23 and 24
is the source 11 electrode and the source electrode part is kuGe −
N i 1 Source' The part of the navigation pole 24 is A, 11/Zn
/Au. Further, 11 is an n4F, 'J-GaAs semiconductor substrate, and 25 is an AuGe-Ni 1W pole.

第2図は第1図で示した素子の等価回路図である。発光
ダイオードと電界効果トランジスターはアイソレーショ
ン層16によって分離されている。しかしながらこの様
な構造は高い抵抗率を持つアイソレーション用の半導体
層が容易に作製出来るA11O;+’hs系の様な材料
では問題ないが、高抵抗率の半導体層の作製がか1#か
しい半導体材料に対しては適用出来ない。特に光ファイ
バが低分散低損失なる特性を示す111m帯での半導体
拐料として知られるIn0aA?’$混晶てはAdGa
As系程容易に高程容易(抗率を持った半導体層の形成
がjlUかしく、rJslし1の様な構造は適用し多)
((い。
FIG. 2 is an equivalent circuit diagram of the element shown in FIG. The light emitting diode and the field effect transistor are separated by an isolation layer 16. However, with this kind of structure, there is no problem with materials such as A11O;+'hs, where semiconductor layers for isolation with high resistivity can be easily produced, but it is difficult to produce semiconductor layers with high resistivity. It cannot be applied to semiconductor materials. In0aA is known as a semiconductor material especially in the 111m band where optical fiber exhibits low dispersion and low loss characteristics. '$ mixed crystal is AdGa
The higher the As type, the easier it is (the formation of a semiconductor layer with resistivity is difficult, and structures like rJsl and 1 are often applied)
((stomach.

本発明は上記欠点に鑑みなされたイ)のであり、高抵抗
率な2)半導体層の作製が容易ならさる材料に於いて発
光タイオード及びその駆H1ij f4<子を隼A11
(化した発光素子きして有効なtjl、lj造を提供〕
−るものである。
The present invention was made in view of the above-mentioned drawbacks, and 2) it is possible to manufacture a light emitting diode and its driver using a material that has high resistivity and 2) facilitates the production of a semiconductor layer.
(Providing an effective tjl, lj structure using a light-emitting element that has been modified)
-

本発明の発光素子は、第1導11τ、型を有する′!1
等lト休基体の両面にそれぞれ第1.4.’+li型を
有するtl−2半導体層と第3半導体層と第1導↑If
、型吉[4,:+’?Hなる第2導亀型を有する第4半
導体層と第1導′f1シ“ζりを有する第5半導体層力
i Illll形成され、前記第2半導体層と前記第4
半導体層は前記第3半2p月4’ I・1”iよりも少
なく共禁制帯幅が大きく、又実射1f率が小さくなる様
に形成され、前記半導体基板の片面を発光部、もう片面
を駆動部とし、前81鼎1(動部に於いて前記第5半導
体層の表面より前記E:i72半2.り体層の内部にま
で遅する深さの円形凹形状の)’1−J1”J、り出し
窓が形成され、その光取り出し窓の側壁には絶縁11′
Sを介し、て′M、極が形成され、更に前記第5半導体
層の表面で前記光取り出し窓が形成されていない部分に
電極が形成されており、前ハ1シ発光部に於いて、前n
V第5半導体層で前記光取り出し窓に対向する部分に電
1流注入手段を形成した構成となっている。
The light emitting device of the present invention has a first conductor 11τ, type '! 1
No. 1, 4, etc. are applied to both sides of the substrate, respectively. '+tl-2 semiconductor layer having li type, third semiconductor layer and first conductor ↑If
, type kichi [4,:+'? A fourth semiconductor layer having a second conductive turtle shape H and a fifth semiconductor layer having a first conductive arch shape are formed, and the second semiconductor layer and the fourth semiconductor layer are formed.
The semiconductor layer is formed so that the third half 2p month 4'I·1''i is smaller than the third half, the co-gang band width is large, and the effective 1f ratio is small, and one side of the semiconductor substrate is used as a light emitting part and the other side is is the driving part, and the front part has a circular concave shape with a depth that extends from the surface of the fifth semiconductor layer to the inside of the E:i72 half 2. body layer in the moving part. J1"J, a projecting window is formed, and an insulator 11' is installed on the side wall of the light extraction window.
A pole is formed through S, and an electrode is formed in a portion of the surface of the fifth semiconductor layer where the light extraction window is not formed, and in the front light emitting part, front n
A current injection means is formed in a portion of the V fifth semiconductor layer facing the light extraction window.

以下、図面を用いて本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail using the drawings.

第3図は本発明に係わる一実施例の断面ン1である。I
nGaAsJ、’ 混晶を用いで作製したものである。
FIG. 3 is a cross-sectional view 1 of one embodiment of the present invention. I
It was fabricated using nGaAsJ,' mixed crystal.

同図において、31は11型Inl’の半導体基板、3
21及び322は厚さ約2μIllのn 型InPから
なる第2半導体層、331及び332は厚さ約1 /1
mの1旧−X(laxAs yP + −yからなる第
3半導体1v、341及び342はjワ、さ約1μmの
■)型InPからなる第4半導体層、351及び352
は厚ざ約1/1mのn型■nt−zG a 7.AFI
WLF I−Wからなる第5半導体層であり、気相成長
法によって半導体基板31の両面にそれぞれ同時に形成
しである。半導体基板31の下側が活性層となる第3半
導体層331を含む発光量?1へ21であり、上側が発
光をスイッチングする機能を備えた制御用等の電極を含
む駆動部22である。;3(iは1.駆動)1(〜22
の半導体)f・1側にエツチングによって形成された直
径約200μn1で、第2半導体層322の内R11に
まで達する深さで形成された円形、凹形状の)’(、H
V、り出し窓である。37は光取り出し窓36の側壁(
こCV11法によって形成された厚さ約1000 ’h
のS+ 02から成る絶縁膜、38はぞの上に形成され
た発)°Cを制1111するためのAlの電極である。
In the figure, 31 is an 11-type Inl' semiconductor substrate;
21 and 322 are second semiconductor layers made of n-type InP and have a thickness of approximately 2 μIll; 331 and 332 have a thickness of approximately 1/1
The third semiconductor layer 1v, 341 and 342 are made of m's 1 old -
is an n-type ■nt-zG a with a thickness of approximately 1/1 m 7. AFI
This is a fifth semiconductor layer made of WLF I-W, and is simultaneously formed on both sides of the semiconductor substrate 31 by vapor phase growth. The amount of light emitted including the third semiconductor layer 331 where the lower side of the semiconductor substrate 31 is an active layer? 1 to 21, and the upper side is a drive section 22 including electrodes for control and the like having a function of switching light emission. ;3 (i is 1. drive) 1 (~22
A circular, concave ()' (, H
V, is a projecting window. 37 is a side wall of the light extraction window 36 (
Approximately 1000'h thick formed by CV11 method
The insulating film 38 is made of S+02 and is an Al electrode formed on top of the insulation film 1111 to control the temperature.

39は同質状のAn(lc −Niから成る電極である
。40は光取り出しi(:K 3(’lに対向する位置
に直径約20μInで円形状に”/r+1を拡111i
39 is an electrode made of homogeneous An(lc-Ni). 40 is an electrode made of homogeneous An(lc-Ni);
.

することによって形成された不純物拡11を領域で1]
型でIn+−zGazAswL’+−wからなる第5仝
1飄り7体層351のうち、この部分はp型となってい
4)。41は5i02.42は’J’ i/P t /
Auから成る電極である。使用に際しては′電極42に
正電圧を印加し、市、(飢3りは接地する。駆動部22
の第2半導体層322が11型、第4半導体層342が
p型である本実施例のJ7.5合には、この間が逆バイ
アス状態になるので、’Ill: 4jK :(8に印
加される電圧が0■、乃しは負’tit圧である時には
、tlf、41□□□39と111.極42の間には電
流は流れず、発光も生じない。電、極38(こ正電1圧
を印加すると1)ハリである第4半導体層342と絶縁
j換37c!:が接する界面に電子が誘起され、f[1
,子′「遅流が電極;)9から絶縁膜37と半導体層の
界面に沿って流れ活性層である発光部21の第3半導体
層331に電子が注入される。
The impurity diffusion 11 formed by
This part of the fifth layer 351 made of In+-zGazAswL'+-w is p-type (4). 41 is 5i02.42 is 'J' i/P t /
The electrode is made of Au. When in use, a positive voltage is applied to the electrode 42, and the drive unit 22 is grounded.
In the case of J7.5 in this embodiment, in which the second semiconductor layer 322 is of the 11 type and the fourth semiconductor layer 342 is of the p type, this period becomes a reverse bias state, so 'Ill: 4jK : (applied to 8) When the voltage is 0, or negative 'tit pressure, no current flows between tlf, 41□□□39 and 111.pole 42, and no light is emitted. When an electric voltage of 1 voltage is applied, 1) electrons are induced at the interface where the fourth semiconductor layer 342, which is firm, and the insulation layer 37c!: are in contact, and f[1
Electrons flow from 9 to the interface between the insulating film 37 and the semiconductor layer and are injected into the third semiconductor layer 331 of the light emitting section 21, which is an active layer.

又正孔電流は′電極42から不純物拡散領域・10を通
して流れ第3半導体層331に正比が注入され、′1ハ
子、正孔の再結合によって発光が起こり第3図で矢印で
示される方向に外t(μに取り出される。尚、駆動部2
2の第3半導体層332の/、l# 1.11型は背に
明記してないがn型なら勿論、又p型であっても上述の
効果で絶縁膜37との界面に・遊子が誘起されて電子に
対する電流路が形成されることは了解されるであろう。
Further, the hole current flows from the electrode 42 through the impurity diffusion region 10, and a positive ratio is injected into the third semiconductor layer 331, and light emission occurs due to the recombination of the holes in the direction shown by the arrow in FIG. It is taken out to the outside t(μ).
/, l# 1.11 type of the third semiconductor layer 332 of 2 is not specified on the back, but if it is an n type, of course, and even if it is a p type, due to the above-mentioned effect, . It will be appreciated that a current path is induced for the electrons.

光取り和し窓36の直径は本実施例では200μmであ
るので円周は6:30μIn程度となり、電子に対する
電流路の幅を広くすることか出来る。その結果tlZ 
& 3Bに1vの電圧を印加することによって約70〜
80 mAの低流を流すことが出来る。電流41Nは第
4半導体層342の層厚に比例し、ブレーク・ダウンを
起こさない程度に層厚をもつ吉薄くすれば更に電流)i
−を増大さぜることか0■能である。本実施例では電子
電流を制御する方式であったが、本実施例の各半導体層
の導′(l型を逆にすれば正孔電流を制御する方式の発
光素子になるが、jL−凡の移動度は電子のそれより遅
いのて高速スイン・1−ングを目的とした応用には好ま
しくない。
Since the diameter of the light balancing window 36 is 200 .mu.m in this embodiment, the circumference is approximately 6:30 .mu.In, making it possible to widen the width of the current path for electrons. As a result tlZ
& Approximately 70~ by applying a voltage of 1v to 3B
It can flow a low current of 80 mA. The current 41N is proportional to the thickness of the fourth semiconductor layer 342, and if the layer thickness is made thin enough to prevent breakdown, the current will increase further)
- It is possible to increase the value by 0. In this example, the electron current is controlled, but if the conductor (l type) of each semiconductor layer in this example is reversed, it becomes a light emitting element that controls the hole current. The mobility of electrons is slower than that of electrons, so it is not suitable for applications aimed at high-speed swinging.

本発明になる発光素子は気相成長法等の技術を用いて一
回の結晶成長で済み、構造もfil単であり、比較的容
易に製造出来る。又半導体の層)1方向に発光部及び駆
動部か集積化されているので、スペースもとらず、小型
化が要求される装置に適したものとなるっ
The light emitting device of the present invention requires only one crystal growth using a technique such as a vapor phase growth method, has a single fil structure, and can be manufactured relatively easily. In addition, since the light emitting part and the driving part are integrated in one direction (semiconductor layer), it does not take up much space and is suitable for devices that require miniaturization.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の断面図、笥2図はその等価回路図、第
3図は本発明(こ係わる一実施例の161面図である。 11及び31は半導体基板、12はn型クラッド層、1
3は活性半導体層、J4はp型クラッド層、15及び1
7はn型0aAs、IGはアイソレーション層、18は
ドレイン電極、19はゲート電極、23及び24はソー
ス電4iζ、32]及び322は第2半導体層、331
及び332は第3半導体層、341及び342は第4半
導体層、351及び352は第5半導体層、36は光取
り出し窓、37は絶縁膜、25 、38 、39及び4
2(ま’+it・1ぐく、/l()は不純物拡11(頭
載、41はS + 02.2Lは発光部、22は駆動部
である。 才 1 図 f 2 口 才 −5区
Fig. 1 is a sectional view of a conventional example, Fig. 2 is an equivalent circuit diagram thereof, and Fig. 3 is a 161-plane view of an embodiment of the present invention (11 and 31 are semiconductor substrates, 12 is an n-type cladding). layer, 1
3 is an active semiconductor layer, J4 is a p-type cladding layer, 15 and 1
7 is n-type 0aAs, IG is an isolation layer, 18 is a drain electrode, 19 is a gate electrode, 23 and 24 are source electrodes 4iζ, 32] and 322 are second semiconductor layers, 331
and 332 are third semiconductor layers, 341 and 342 are fourth semiconductor layers, 351 and 352 are fifth semiconductor layers, 36 is a light extraction window, 37 is an insulating film, 25, 38, 39 and 4
2 (ma'+it・1guku, /l() is the impurity expansion 11 (head mounted, 41 is S + 02.2L is the light emitting part, 22 is the driving part.) 1 Figure f 2 Mouth -5 section

Claims (1)

【特許請求の範囲】[Claims] tn1導11L型を有する半導体基板の両面にそれぞれ
第1導′11工型を有する第2半導体層き第3半導体層
と第1導電型とは異なる第2導電ハリを有する第4半導
体層と第1導11T、型を有する第5半導体層が順次形
成され、前記第2半導体層と前記第4半導体層は前記第
3半導1体層よりも少なくとも禁制帯幅が大きく、又屈
折率が小さくなる様に形成され、前記半導体基板の片面
を発光部、もう片面を駆動部とし、前記駆動部に於いて
前記第5半導体層の表面より前記第2半導体層の内部に
すで達する深さの円形凹形状の光取り出し窓か形成され
、その光取り出し窓の側壁ζこは絶R膜を介して電極が
形成され、更に前記第5半導体層の表面で前記光取り出
し窓が形成されていない部分に電極が形成されており、
前記発光部に於いて、前記第5半導体層で前記光取り出
し窓に対向する部分に、′1′lj1流注入手段を形成
しであることを特徴とする発光素子。
A second semiconductor layer having a first conductivity type, a third semiconductor layer, a fourth semiconductor layer having a second conductivity type different from the first conductivity type, and a fourth semiconductor layer having a second conductivity type different from the first conductivity type, on both sides of a semiconductor substrate having a tn1 conductivity type 11L type. A fifth semiconductor layer having a type of 1 conductor 11T is sequentially formed, and the second semiconductor layer and the fourth semiconductor layer have at least a larger forbidden band width and a smaller refractive index than the third semiconductor layer. One side of the semiconductor substrate is a light emitting part, the other side is a driving part, and the driving part has a depth that reaches from the surface of the fifth semiconductor layer to the inside of the second semiconductor layer. A light extraction window having a circular concave shape is formed, an electrode is formed on the side wall of the light extraction window via an insulated film, and a portion of the surface of the fifth semiconductor layer where the light extraction window is not formed. electrodes are formed on the
A light-emitting element characterized in that, in the light-emitting portion, a '1'lj1 flow injection means is formed in a portion of the fifth semiconductor layer that faces the light extraction window.
JP57139363A 1982-08-11 1982-08-11 Light-emitting element Pending JPS5929477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57139363A JPS5929477A (en) 1982-08-11 1982-08-11 Light-emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57139363A JPS5929477A (en) 1982-08-11 1982-08-11 Light-emitting element

Publications (1)

Publication Number Publication Date
JPS5929477A true JPS5929477A (en) 1984-02-16

Family

ID=15243582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57139363A Pending JPS5929477A (en) 1982-08-11 1982-08-11 Light-emitting element

Country Status (1)

Country Link
JP (1) JPS5929477A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280184A (en) * 1992-04-08 1994-01-18 Georgia Tech Research Corporation Three dimensional integrated circuits with lift-off
US5401983A (en) * 1992-04-08 1995-03-28 Georgia Tech Research Corporation Processes for lift-off of thin film materials or devices for fabricating three dimensional integrated circuits, optical detectors, and micromechanical devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280184A (en) * 1992-04-08 1994-01-18 Georgia Tech Research Corporation Three dimensional integrated circuits with lift-off
US5401983A (en) * 1992-04-08 1995-03-28 Georgia Tech Research Corporation Processes for lift-off of thin film materials or devices for fabricating three dimensional integrated circuits, optical detectors, and micromechanical devices

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