JPS5928372A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make OFF-state always by increasing the threshold voltage more than an operating source voltage and thus obtain an ROM by a method wherein a B doped poly Si and a P doped poly Si are laminated on a P type Si substrate via a gate oxide film, and the surface is changed into a P<+> layer by making B reach the substrate by heat teatment. CONSTITUTION:The B doped poly Si 24 is formed on the gate oxide film 23 of the P type Si substrate 21, and made to remain on a region to form OFF-state always according to the order reception of ROM's. The gate oxide film 26 is completed by forming an oxide film 25 on the surface. Next, poly Si 27 and 28 containing P at high density is provided, and a double layer poly Si is formed by etching the film 25 and the layer 24 with the layer 28 as the mask. High temperature treatment causes B to diffuse 29 only into the region determined by the layer 24. Thereafter, a source and drain 30 is provided corresponding to gate electrodes 27 and 28, covered with a PSG31, and a metallic wiring 32 is performed. This contitution makes the resistance of the gate electrodes decrease, capacity and the capacity of an output part also decrease accordingly an ROM of high integration and high speed action can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and particularly to a silicon gate MO8 semiconductor device using polycrystalline silicon as a gate electrode. In particular, silicon gate type MO8
ROM using semiconductor devices
mory: read-only memory).

Semiconductor 11. OM is increasing capacity and T A T (Tu
rnAround 'l'ime) is being shortened, and 1 large capacity and ROM code process after ordering? It is hoped that the product can be shipped to the orderer as soon as possible.

For 7 to 1 large capacity ratio, vertical stacking R (JM (NANJ)
However, there are various methods for horizontally stacked R (JJNO type), including υ with high integration ratio and large capacity, and vertically stacked ROM J:υ horizontally stacked OM. Since a high-speed ratio is possible, the planar configuration shown in Fig.
Mi is used.

In a horizontally stacked ROM as shown in FIG. 1, polycrystalline silicon wiring l is used as the wiring and gate electrode. In the manufacturing process of the silicon gate type MO8, a structure is formed to separate the field region from the diffusion and gate regions, and is separated into a transistor region 2 and a non-transistor region (field region) 3.

Therefore, in region 2, the insulating film under the gate electrode becomes thinner, the threshold voltage in region 7 becomes lower, and it becomes an active transistor, and in region 3, the insulating film becomes thicker.

This region 3 has a high threshold voltage.

This becomes an inactive area. Therefore, the output wiring 4 as ROM
A contact hole is provided in all regions to form an NCJ type, and by selecting an active transistor and an inactive transistor (region 3), the ROM code tit As a method of incorporating
There is a ROM as shown in FIG.

In such a OM, the ROM code, that is, the presence or absence of a transistor is selected depending on the pattern 6 that separates the field area.

Since the insulating film under the polycrystalline silicon 1 in the region 3 is thick, it is a horizontally stacked ILOM, and the wiring capacitance of the polycrystalline silicon 1 is small, so that high-speed operation is possible. Such ROM has a high integration ratio.

ROM at the early stage of the wafer manufacturing process.
Since it is a code ratio, l also has the disadvantage that it takes a long time from receiving an order to shipping the 0M code. Next, we will develop a tank (JM
The ROM of this configuration shown in FIG. 2 has all the transistor areas in field pattern 7. Form of activity ratio? The degree of integration is exactly the same as the ROM with the configuration shown in Figure 1, but the ROM code is manufactured after forming the gate oxide film, and then using the ion implantation method to form the transistor region 8. It is separated into a non-transistor region 9.

The transistor region 8 is similar to the transistor region 2 in FIG. 1, but the region 9 that is to become a non-transistor is always formed in a JFF state by performing one ion implantation to increase the threshold voltage of gold.

With such a ROM configuration, the TAT is shortened and there is no change in the degree of integration.

Ion implantation of an impurity of a conductivity type opposite to that of the source/drain is performed in the ion implantation region 10 to increase the threshold voltage gold, and the transistor region 9 is then OI! ' Since the state is set to F, the insulating film under the polycrystalline silicon in this region 9 is a thin gate oxide film similar to the active transistor, and the capacitance becomes large, resulting in high-speed operation due to the delay of -f: It's getting in the way.

As described above, the ROM shown in FIG. 1 and the ROM shown in FIG. 2 each have their own characteristics, and have both advantages and disadvantages.

Therefore, the present invention provides a horizontally stacked ROM (H) that is highly integrated, has a large capacity, is capable of high-speed operation, and has a shortened TATi.

The horizontally stacked ROM of the present invention has a thousand-sided configuration as shown in FIG. 3, and has the same degree of integration as the conventional IL OM. In this explanation, RO is used as a semiconductor device using an N-channel transistor using a P-type substrate.
MkExplain. Namely.

Depending on the field pattern 11, transistor regions and non-transistor regions are constructed as shown in FIG. Therefore, in the ILOM, a field pattern ll' is formed so as to form all l transistor regions. The active transistor region 12 is formed of a polycrystalline silicon gate electrode 13, which is a thin gate oxide film, and has a low threshold voltage, as in the prior art. Next, in the non-current transistor region 14, is there a single gate acid ratio film? After the growth, boron and impurities are introduced into the polycrystalline silicon (the first layer of polycrystalline silicon), and when the ROM code is ordered, the boron impurity is introduced into the field area in the area where the transistor is to be formed. Remaining polycrystalline cricon containing 1
No polycrystalline silicon remains in the normal active transistor area. After that, a second layer of polycrystalline silicon is grown,
Is this polycrystalline silicon impurity? Introducing it and getting a complete picture of resistance. This second layer of polycrystalline silicon is patterned to form polycrystalline silicon 13, and the first layer of polycrystalline silicon into which boron impurities have been introduced is patterned using this polycrystalline 7 silicon gold mask. A region 15 is formed in which the first layer of polycrystalline silicon and the second layer of polycrystalline silicon overlap. Is this part formed using two-layer polycrystalline silicon? This is a well-known manufacturing method similar to that of the PROM (programmable OM) used. In this state, the gate electrode of the active transistor region is made of only the second layer of polycrystalline silicon, but the inactive transistor region consists of the first layer of polycrystalline silicon containing boron impurities and the second layer of polycrystalline silicon. Crystalline silicon has a two-layer structure.

Next, high temperature heat treatment? By doing this, the boron impurity in the first layer of polycrystalline silicon penetrates through the gate oxide film and reaches the substrate surface in this region, creating an effect similar to that of ion implantation. This increases the surface concentration of the P-type substrate in that portion, increasing the threshold voltage.

The threshold voltage of a transistor with this structure is determined by the capacitance ratio of each of the 12 layers of floating electrodes and the gate electrode, and is higher than when using at least one layer, and the threshold voltage is even higher due to the increased surface concentration. Therefore, the transistor is always in the OF Ii' state. Therefore, this structure has horizontal stacking R
In OM, the field pattern is made common by using two layers of polycrystalline silicon, and the surface impurity concentration is increased to reach the surface of the boron layer, and the threshold voltage of that part? This is the same as the conventional example shown in Fig. 2, but the wiring capacitance of the gate electrode is 2-layer. Since it is made of polycrystalline silicon, it has a small capacitance, and in the manufacturing method shown in Figure 2, the threshold box and the ion implantation region for increasing pressure are formed in the source region, which is later formed in a self-aligned manner. In contrast, in the structure and method of the present invention, the second layer polycrystalline silicon is used as a mask to kevadate the first layer polycrystalline silicon. almost the same width,
In the subsequent heat treatment, is there boron only under the gate electrode? As a result, the overlap between this boron impurity layer and the source/drain diffusion region becomes smaller, allowing high-speed operation.

Next, a method of manufacturing a ROM according to the present invention will be explained with reference to FIG. As shown in FIG. 4(a), a field region 22 and a gate oxide film 23 are formed on a P-type substrate 21. As shown in FIG.

The field oxide film 22 is formed by a conventional method of forming an insulating film buried in a substrate. on this gate oxide film 23.

Growing polycrystalline silicon with boron introduced.

When the ROM code is ordered, 24 layers of this polycrystalline silicon (including boron impurities) are patterned using a mask so that a predetermined transistor area is always turned off? Leave it where you want it to form. Next, an oxide film 25 is formed on the optical surface of the polycrystalline silicon 23, at which time a gate oxide film (although the arsenal film becomes thicker) is formed.

This film is used as the gate oxide film 26. At this time, there is also a method of removing the gate oxide film 23 using the polycrystalline silicon 24 as a mask and then applying acid. After 7, the polycrystalline silicon containing a high concentration of phosphorous is used as the gate electrode wiring, and the polycrystalline silicon 27 where the transistor region is formed and the inactive transistor region? Polycrystalline silicon 2El patterning is carried out at the place where it will be made (Fig. 4(b)).

The oxide film 25 is removed using a polycrystalline silicon 28 mask, and polycrystalline silicon 24 containing boron is etched to form a two-layer polycrystalline/licon gold structure in a self-aligned manner.

After 7, the boron impurity in the first layer of polycrystalline silicon penetrates through the gate acid ratio film 23 and forms 29 P-type diffusion layers on the substrate surface by passing through a high-temperature heat treatment 7. The P diffusion layer of 11q will diffuse only into the region under the first layer of polycrystalline silicon, and that region will be
] Determined by polycrystalline silicon 24. After that, phosphorus and arsenic impurities with conductivity type opposite to the substrate? Thermal diffusion method or ion implantation method? Then, 30 source/drain regions are formed in a self-aligned manner with respect to the gate electrodes 27 and 28 (Fig. 4(C)).
). Next, an insulating film 31 such as phosphor glass is grown, and contact holes are formed in predetermined locations. Provide metal wiring 32? By performing these steps, the ROM semiconductor device of the present invention is completed (fourth step).
Figure (d)).

The OMI-t of the present invention is to form a transistor region that is always OFF, and this region uses two layers of polycrystalline silicon, and boron impurities are introduced into the first layer of polycrystalline silicon. So, is there resistance to polycrystalline silicon in the 21st issue 1a? By introducing a high concentration of linoleic material to reduce the amount of boron contained in the first layer of polycrystalline silicon, heat treatment is performed.

1) Threshold voltage by increasing the W concentration on the substrate surface? The 01i'F state is always formed by increasing the power supply voltage to a level higher than that used. By doing this,
The resistance of the gate electrode is low and its capacitance. , and the capacitance of the output section is also reduced, making it possible to configure a ROMt that is highly integrated and capable of high-speed operation.

In this example, the second layer is linen thin material? Although the introduced polycrystalline silicon is used, this impurity may also be introduced during diffusion and ion implantation when forming the source/drain N-type regions.Also, this structure is an N-channel transistor structure. However, even if it is used in a complementary transistor semiconductor device, its meaning remains the same.

[Brief explanation of the drawing]

1 and 2 are plan views showing the conventional iL OM configuration, FIG. 3 is a plan view showing the R(JM f7'?) configuration of the embodiment of the present invention, and FIG. 4 is a plan view showing the implementation of the present invention. It is a manufacturing process sectional view showing the manufacturing method of the example half 2!'I body device i'7. .12... Active transistor area, 3. 9. 14... Inactive transistor area % 6, 7.11... Field pattern, 21... P-type silicon substrate,
22...Field oxide film%23.26...
...Gate oxide film, 24...Polycrystalline silicon containing boron impurity, 27.28...Polycrystalline silicon containing Linnean impurity, 29...Surface Region with high substrate concentration, 30... Source/drain region, 31... Phosphorus glass, 4
．． 31...Metal wiring. Etc. 4-Father

Claims (1)

[Claims] Through a gate oxide film on a P-type silicon substrate. The first layer of polycrystalline silicon into which boron impurities are introduced is formed, the second layer of polycrystalline silicon into which N-type impurities are further introduced into the upper layer, and the first layer of polycrystalline silicon. By selecting the ROM code, the poron impurity in the first layer of polycrystalline silicon penetrates through the gate oxide film, and the transistor is in an always-off state with a high substrate P-type impurity concentration and the second layer of polycrystalline silicon. An N-channel, OM type semiconductor device characterized by having an active transistor having an electrode.