JPS59231952A - マルチプロセツサ間通信制御方式 - Google Patents

マルチプロセツサ間通信制御方式

Info

Publication number
JPS59231952A
JPS59231952A JP58107135A JP10713583A JPS59231952A JP S59231952 A JPS59231952 A JP S59231952A JP 58107135 A JP58107135 A JP 58107135A JP 10713583 A JP10713583 A JP 10713583A JP S59231952 A JPS59231952 A JP S59231952A
Authority
JP
Japan
Prior art keywords
bus
polling
communication control
ccu
common bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58107135A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0226904B2 (enrdf_load_stackoverflow
Inventor
Hiroki Masuda
増田　博樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58107135A priority Critical patent/JPS59231952A/ja
Publication of JPS59231952A publication Critical patent/JPS59231952A/ja
Publication of JPH0226904B2 publication Critical patent/JPH0226904B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
JP58107135A 1983-06-15 1983-06-15 マルチプロセツサ間通信制御方式 Granted JPS59231952A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58107135A JPS59231952A (ja) 1983-06-15 1983-06-15 マルチプロセツサ間通信制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58107135A JPS59231952A (ja) 1983-06-15 1983-06-15 マルチプロセツサ間通信制御方式

Publications (2)

Publication Number Publication Date
JPS59231952A true JPS59231952A (ja) 1984-12-26
JPH0226904B2 JPH0226904B2 (enrdf_load_stackoverflow) 1990-06-13

Family

ID=14451389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58107135A Granted JPS59231952A (ja) 1983-06-15 1983-06-15 マルチプロセツサ間通信制御方式

Country Status (1)

Country Link
JP (1) JPS59231952A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63288534A (ja) * 1987-05-21 1988-11-25 Nippon Denso Co Ltd 通信機能を有する制御装置
JPS63289664A (ja) * 1987-05-21 1988-11-28 Matsushita Electric Ind Co Ltd マルチｃｐｕ装置
JPH0265337A (ja) * 1988-08-31 1990-03-06 Fujitsu Ltd チャネルアクセス方式

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336115A (en) * 1976-09-16 1978-04-04 Fujitsu Ltd Polling control system
JPS5652949A (en) * 1979-10-05 1981-05-12 Hitachi Ltd Interruption control method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336115A (en) * 1976-09-16 1978-04-04 Fujitsu Ltd Polling control system
JPS5652949A (en) * 1979-10-05 1981-05-12 Hitachi Ltd Interruption control method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63288534A (ja) * 1987-05-21 1988-11-25 Nippon Denso Co Ltd 通信機能を有する制御装置
JPS63289664A (ja) * 1987-05-21 1988-11-28 Matsushita Electric Ind Co Ltd マルチｃｐｕ装置
JPH0265337A (ja) * 1988-08-31 1990-03-06 Fujitsu Ltd チャネルアクセス方式

Also Published As

Publication number Publication date
JPH0226904B2 (enrdf_load_stackoverflow) 1990-06-13

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