JPS59231795A - Memory device - Google Patents

Abstract

PURPOSE:To shorten the access time to a memory by changing the threshold voltage of a sense circuit in response to the input signal. CONSTITUTION:An address signal is supplied to a decoder 2 as a decoding signal via an input circuit 1, and a specific memory is selected within a memory array 3 corresponding to the output signal of the decoder 2. Then the state of the selected memory is decided by a sense circuit 11. In this case, the level of decision is changed by the contents of a latch circuit 12. Based on the result of this decision, an output circuit 5 delivers the data corresponding to the input data. Therefore the specific data is delivered by the address signal given to the circuit 1 from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and more particularly to a memory device that reduces the access time of a read-only memory device.

FIG. 1 is a block diagram showing a conventional read-only memory device. In the same figure, (1) is an address input circuit into which the address input signal shown in FIG. 2 (a) is input, (2)
u An address decoding circuit that decodes the output of this address input circuit (1) and outputs a selected memory address signal, (3) a memory array that stores data corresponding to this memory address signal, (4) ti determine the state of the selected memory in this memory array (3);
A sense circuit which outputs an output signal having an access time E shown in FIG. 2(C) in response to an input signal shown in FIG. 2(b) is shown in FIG. 3 in detail. (5) is a data output circuit which inputs the judgment data of this sense circuit (4) and outputs data corresponding thereto. In addition,
VTRt shown in FIG. 2(b);j the sense circuit (4)
The threshold voltage is Ruru.

Furthermore, in the sense circuit (4) shown in FIG. 3, (6)
is a memory transistor consisting of an N-channel memory transistor (6a), (the bottom is a P-channel pull-up transistor 7, (8) is a TiP-channel transistor, and (9) is an N-channel transistor.
The channel transistor (10) is the output terminal.

Note that the transistors (8) and (9) constitute a sense inverter. FIG. 5 shows the input/output characteristics of this 0MO8 sense inverter.

Next, the operation of the read-only memory device with the above configuration will be explained. First, we begin with an externally given N2 diagram (a
) is internally taken in by the address input circuit (1). Therefore, the address input circuit (1) outputs a decode input signal corresponding to this address signal. This decode input signal is then input to the address decode circuit (2). Therefore, this address decode circuit (2) outputs a decode output signal corresponding to this decode input signal to the memory array (3). Therefore, a specific memory of the memory array (3) corresponding to this decoded output signal is selected. Then, the sense circuit (4) determines whether the state of the selected memory is "1" or "0", and depending on the determination result, the corresponding data signal (Fig. 2 (C) ) is output to the data output circuit (5). Therefore, this data output circuit (5) outputs data corresponding to the input data. In this way, specific data can be output from the data output circuit (5) by inputting the next address signal applied from the outside to the address input circuit (0). Next, the operation of the sense circuit (4) shown in FIG. 3 will be explained with reference to FIGS. 4 and 5. First, one bit of data is held depending on whether the memory transistor (6a) of the memory element (6) is present or not. That is, when the address input signal is r 1 j and there is a memory element (6), the pull-up transistor (7
), current flows to this memory transistor (6a).

The operating point in this case can be indicated by point Q in FIG. They can be expressed by the following formulas (2) and (2), respectively.

Coco-e, IM = I PL "l" 67) From, VTMM = VTRPL, β, , = 10βPL
Assuming that, however, W=Va −VTHM + Y”
' VDSM +y<w Y →0.05 W tonal o j tsu”C1v,=s
If v, vTIDiI=1v, Y=0.2V.

In other words, VD, M=0.2 V tip, and the level at point F in FIG. 3 is 0.2V. On the other hand, when the address input is "0" or "1", the memory element (6
), current flows through the pull-up transistor (7), and the operating point is point R in the N4 diagram. In this case, the level at point F in FIG. 3 becomes +V. In this way, when the address input is "1", the level tiO at point F changes from 2V to +V depending on whether the memory element has it or not. Here, the threshold voltage V1 is (3)
It is determined by the formula.

(3) If β and = β, , v, , = vT, then v8 = O, S (see Figure 5), and the power supply voltage i becomes the voltage. Therefore, the level of point F in Figure 3 is 0.
．． If it changes from 2v to +■ (power supply voltage) t, the output terminal (
Even if the voltage changes from 1G) +V (power supply voltage) to Ov, a corresponding voltage can be obtained at the output terminal (1G) of the sense circuit with or without a memory element.

However, in conventional memory devices, the sense circuit (4)
When determining whether the state of the selected memory is "1" or rOJ, a constant threshold voltage V is applied as shown in Figure 2(a).
Since the determination is made based on TW, there is a limit to how much time it takes to output specific data more quickly in response to an externally applied address signal, that is, how to shorten the access time E (see Figure 2<c>t*). Ruru was the runner-up.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a memory device in which the threshold voltage of a sense circuit can be changed depending on an input signal to shorten access time.

To achieve this purpose, Hitoshi invented a latch circuit that memorizes the state of a selected memory in the memory array, and a sense that is controlled by the output signal of this latch circuit and whose threshold value changes. The circuit is described in detail below using examples.

FIG. 6 is a block diagram showing an embodiment of the memory device according to the present invention. In the figure, (11) is a sense circuit whose detailed circuit is shown in FIG. 7, and (12) is a latch circuit that temporarily stores judgment data of this sense circuit (11). Yosense circuit (11)
) to change the threshold voltage VTHt.

Note that in the sense circuit (11) shown in FIG.
3) is a first transfer gate consisting of an N-channel transistor (14) and a P-channel transistor (15), and (16) is an N-channel transistor (17).
and a second P-channel transistor (18).
Transfer gates (19m) to (19c) are P-channel transistors, (20a) to (20c) are N-channel transistors, and (21) is a D-type 7-lip 7-4 transistor.

Next, the operation of the memory device with the above configuration will be explained. First, an address signal applied from the outside is input internally by the address input circuit (1). therefore,
Address input circuit (1) Outputs a decode input signal corresponding to the extended address signal. This decode input signal is then input to the expanded address decode circuit (2). Therefore, this address decode circuit outputs a decode output signal corresponding to the decode input signal. Then, a specific memory in the memory array (3) corresponding to this decoded output signal is selected. Next, the sense circuit (
11). In this judgment, the judgment level changes depending on the contents of the latch circuit (12). Based on the determination result, the data output circuit (5) outputs data corresponding to the input data. Be friends,
Specific data can be output from the data output circuit (5) by an address signal externally applied to the address input circuit (1).

Next, regarding the operation of the sense circuit (11) shown in FIG. 7, FIGS. 8, 9, and 10 (a) to 1O (c)
Explain with reference to. First, one bit of data is held depending on whether the memory element (6) is present or not.

In other words, when the address input signal is "1", current flows to the memory transistor (6a) through the pull-up transistor (η). Therefore, the level at point F is 0.2V. On the other hand, if the address input is "0" or "1", the memory element (
6) If there is no pull-up transistor (η), no current flows and the level at point F is +■.Now, the D-type 7-rip 70-tube (21) f) Q terminal is rlJ,
When the Q terminal is rOJ, the first transformer 7 agate (1
3) is turned off, and the second transfer gate (1G) is turned on. Further, since the transistor (19c) Id is turned on and the transistor (20c) Id remains off, the gate of the transistor (19b) becomes +V, so this transistor / (19b) fi is turned off. t
In addition, since the gate of the transistor (20b) is connected to point F through the second transformer 7 agate (16),
The inverter tube is constructed as shown in FIG. Now, β of the transistor (19a) is βP1. Let β of the transistor (20m) be □, β of the transistor (zob) be βN2,
βPi = /Ml rβN2=3β*1 e V7p
= Vt*, the threshold voltage of the above formula (3) ■0
can be expressed by equation (4).

,. 77. V-9゜ (4) Cocoa, vT
, = IV, V, D=5 V then the threshold voltage V
'=0.4. This means that even if the threshold voltage V'' of the sense circuit (4) shown in FIG. 3 is 0.5, the sense voltage will drop.

Next, the Q terminal of the D type 7 rig 70 tube (21) is connected to rOJ.
, when the Q house is "1", the first transfer gate (1
3) a ontona tai, 2nd trance 7 agate (16)
is off. Also, since the transistor (19c) t1 is off and the transistor (20c) is on, the gate of the transistor (19b) is the first transformer 7A).
(13) and is connected to point F through the transistor (2
Since the gate of 0b) becomes GND, this transistor (20b) is turned off.

As a result, the inverter shown in FIG. 9 is constructed.

Now, let β of the transistor (19a) be βP1, β of the transistor (19b) be βP2, β19 of the transistor (20a), and βPl=β, □.

If β, 2=3β and ■TP=■TH, the threshold voltage Vζ15) of the above equation (3) can be expressed.

Cocoa, vT, = IV, VD, = 5V, the threshold voltage V'' = 0.6. This means that the threshold voltage v'' of the sense circuit (4) shown in Fig. 3 = o, s
The voltage will rise even more in the evening.

Next, the D-7 lip-flop (21) latches the output signal at the output terminal (10) at the falling edge of the clock. Therefore, when the output terminal (10) is rOJ,
At the falling edge of the clock, the latch is activated and the D, D type arrest flop (21) operates, the Q terminal becomes rOJ9, and the Q terminal becomes "1". Also, when the output terminal (lO) is "1", the latch is applied at the falling edge of the clock, the D-type 7-ripple loop (21) operates, and the Q terminal becomes "1".
The output terminal becomes “0”. That is, point F is 0.2v″t
′, the output terminal (10) becomes ti +V (logically “1”).

When this data is latched by a clock, the Q terminal becomes “l-
1 and the Q terminal becomes "0", so the sensing inverter can be shown in the configuration shown in FIG. The sense voltage of the inverter is assumed to be V''=0.4. Therefore, when the address changes and the F point changes from 0.2V to +V, the sense circuit (4) shown in Figure 3 The threshold voltage v''=o, determined by s, is the threshold voltage V'' of the sense circuit (4) shown in FIG. The time required to reach the threshold voltage v0 is short.Next, when the F point is set to +V, the output terminal (10) becomes GND (logically l-OJ).Therefore, the D-type 7-lip 7p Tube (21) K Therefore, when this output data is latched by a clock, the Q terminal becomes "0" and becomes the terminal tj:rlJ, so the sensing inverter can be shown in the configuration shown in FIG. The voltage of this inverter is V"=0.6. Therefore, the address changes and then point F changes from +V to 0.
．． When the voltage changes to 2V, the sense circuit (4) shown in Figure 3
The threshold voltage VI = 0.5V, but the threshold voltage V'' of the sense circuit (11) shown in Figure 7 = 0.6, so the time it takes for the F point to drop +■ to reach vo. In other words, as shown in FIG. 10(a), F
In response to a change in the point, the output signal from the output terminal (10) shown in FIG. 7 is output at the timing shown in FIG. 10(c), but the conventional output signal from the output terminal (10) shown in FIG. The signal is output at the timing shown in Fig. 10). Therefore, as shown in FIG. 10(c), the output signal can be made faster by T1.

It should be noted that as the clock signal for the D-type 7-lip 70-tub (21), a signal generated when the address changes may be used, and it goes without saying that a teragu select signal given after the address is set may also be used. Ruru.

In the above embodiment, complementary MO8) transistors were used, but N-channel MO8) two transistors were used. Yarnel MO8) Of course, it is also possible to configure it with only transistors. Further, it goes without saying that the circuit for changing the threshold voltage is not limited to the above-mentioned circuit.

As described above in detail, according to the memory device according to the present invention, the access time can be increased by changing the threshold voltage of the sense circuit according to the output signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional read-only memory device, FIGS. 2(a) to 2(C) are diagrams showing waveforms of each part of FIG. 1, and FIG. 3 is a sense circuit of FIG. 1. Figure 4 is a detailed circuit diagram showing the input voltage and current characteristics of the sense circuit in Figure 3, Figure 5 is an input/output characteristic diagram showing the threshold voltage of the sense inverter, and Figure 6 is a diagram showing the input voltage and current characteristics of the sense inverter. A block diagram showing an embodiment of the memory device according to the invention, FIG. 7 is a detailed circuit diagram of the sense circuit of FIG. 6, and FIGS. 8 and 9 are circuit diagrams for explaining the operation of FIG. 7. , Figures 10(a) to 10
FIG. 7C is a timing diagram for explaining the operation of the sense circuit of FIG. 3 and the operation of the sense circuit of FIG. 7. (1) Address input circuit, (2) Address decoding circuit, (3) Memory array, (4
)...Sense circuit, (5)...Data output circuit, (6)...Memory element, (6a)...Memory transistor, (η...Pull-up transistor, (8) and (9)...transistor, (10)
-@...Output terminal, (11)...Sense circuit, (1
2)...Latch circuit, (13)...9 first transfer gate, (14) and (15)...transistor, (16)...second transistor,
(17) and (18)・Dispute・φ transistor, (19
a)~(19c)---Transistor, (20m)~
(20c)・Fist・・Transistor, (21) @・−・
D-type flip 70 tubes. In the drawings, the same reference numerals indicate the same parts corresponding to the fc line. Agent Masuo Oiwa Figure 1 Figure 2 Flash Figure 3 1 "-a

Claims (1)

[Claims] A memory device comprising an address input circuit, an address decode circuit, a memory array, a sense circuit, and a data output circuit, including a latch circuit that stores the state of the selected memory during the memory play, and control by an output signal of the latch circuit. and a sense circuit whose threshold value changes.