JPH0120519B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and more particularly to a memory device that reduces the access time of a read-only memory device.

FIG. 1 is a block diagram showing a conventional read-only memory device. In the figure, 1 is the figure 2 a.
2 is an address decoding circuit that decodes the output of this address input circuit 1 and outputs a selected memory address signal; 3 stores data corresponding to this memory address signal; The memory array 4, which has a memory array 4, determines the state of the selected memory in the memory array 3, and in response to the input signal shown in FIG. 2b, outputs an output signal with an access time E shown in FIG. 2c. This is a sense circuit for outputting, and the detailed circuit is shown in FIG. Reference numeral 5 denotes a data output circuit which inputs the judgment data of this sense circuit 4 and outputs data corresponding thereto. Note that V _TH shown in FIG. 2b is the threshold voltage of the sense circuit 4.
In the sense circuit 4 shown in FIG. 3, 6 is a memory element consisting of an N-channel memory transistor 6a, 7 is a P-channel pull-up transistor, 8 is a P-channel transistor, and 9 is an N-channel transistor.
The channel transistor 10 is an output terminal. Note that the transistors 8 and 9 constitute a sense inverter. Figure 5 shows the input/output characteristics of this CMOS sense inverter.

Next, the operation of the read-only memory device with the above configuration will be explained. First, the address signal shown in FIG. 2A applied from the outside is taken into the address input circuit 1 internally. Therefore, address input circuit 1 outputs a decode input signal corresponding to this address signal. This decode input signal is then input to the address decode circuit 2. Therefore, address decode circuit 2 outputs a decode output signal corresponding to this decode input signal to memory array 3. Therefore, a specific memory in the memory array 3 corresponding to this decoded output signal is selected. Then, the sense circuit 4 determines whether the state of the selected memory is "1" or "0", and based on the determination result, the corresponding data signal (see Figure 2 c)
is output to the data output circuit 5. Therefore, this data output circuit 5 outputs data corresponding to the input data. In this way, by inputting an externally applied address signal to the address input circuit 1, specific data is transmitted to the data output circuit 5.
It can be output from. Next, the operation of the sense circuit 4 shown in FIG. 3 will be explained with reference to FIGS. 4 and 5. First, depending on whether the memory transistor 6a of the memory element 6 is present or not, 1
Holds bit data. That is, the address input signal becomes "1", and if there is a memory element 6, current flows through the pull-up transistor 7 to the memory transistor 6a. The operating point in this case can be shown by point Q in FIG. Therefore, the current I _M flowing through the memory transistor 6a and the current I _PL flowing through the pull-up transistor 7 at this point Q can be expressed by the following equations (1) and (2), respectively.

I _M = β _M {(V _G −V _THM )V _DSM −V _DSM ² /2} (1) I _PL = β _PL /2(V _G −V _THPL ) ² (2) Here, I _M = I Since it is _PL , let V _THM = V _THPL ,
Assuming β _M = 10β _PL , 10β _PL (W×−Y ² /2) = β _PL /2W ² However, W=V _G −V _THM , Y=V _DSM , Y<W Y≒0.05W . Therefore, V _G = 5V, V _THM =
If it is 1V, Y=0.2V. That is, V _DSM =
0.2, and the level at point F in Figure 3 is 0.2V. On the other hand, if the address input is "0" or "1" and there is no memory element 6, no current flows through the pull-up transistor 7, and the fourth
Point R in the figure is the operating point. In this case, F in Figure 3
The level of the point becomes +V. In this way, when the address input is "1", the level at point F changes from 0.2V to +V depending on whether the memory element has it or not. Here, the threshold voltage V ^*
is calculated using equation (3).

Here, if β _P = β _N and V _TP = V _TN , then V ^* = 0.5
(See Figure 5), and 1/2 of the power supply voltage becomes the voltage. Therefore, the level of point F in Figure 3 is
If the voltage changes from 0.2V to +V (power supply voltage), the output terminal 10 will change from +V (power supply voltage) to 0V, and the corresponding voltage will be obtained at the output terminal 10 of the sense circuit with or without the memory element. be able to.

However, in conventional memory devices, the state of the memory selected by the sense circuit 4 is either "1" or "0".
As shown in Figure 2b, when determining _whether the E
(See Figure 2 c) There was a drawback that there was a limit to the shortening of the length.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a memory device in which the threshold voltage of a sense circuit can be changed depending on an input signal to shorten access time.

To achieve this object, the present invention includes a latch circuit that stores the state of a selected memory in the memory array, and a sense circuit whose threshold value is changed by being controlled by the output signal of the latch circuit. This will be described in detail below using examples.

FIG. 6 is a block diagram showing one embodiment of a memory device according to the present invention. In the figure, 11 is a sense circuit whose detailed circuit is shown in FIG.
is a latch circuit that temporarily stores judgment data of this sense circuit 11, and this latch circuit 12 changes the threshold voltage _VTH of the sense circuit 11.

Note that in the sense circuit 11 shown in FIG.
13 is a first transfer gate consisting of an N-channel transistor 14 and a P-channel transistor 15; 16 is an N-channel transistor 1;
7 and P channel transistors 18, 19a to 19c are P channel transistors, 20a to 20c are N channel transistors, and 21 is a D type flip-flop.

Next, the operation of the memory device with the above configuration will be explained. First, an address signal applied from the outside is internally taken in by the address input circuit 1. Therefore, the address input circuit 1 outputs a decode input signal corresponding to the address signal. This decode input signal is then input to the address decode circuit 2. Therefore, this address decode circuit 2 outputs a decode output signal corresponding to the decode input signal. Then, a specific memory in the memory array 3 corresponding to this decoded output signal is selected. Next, the sense circuit 11 determines whether the state of the selected memory is "1" or "0". In this judgment, the judgment level changes depending on the contents of the latch circuit 12. Based on the determination result, the data output circuit 5 outputs data corresponding to the input data. Therefore, specific data can be output from the data output circuit 5 by an address signal externally applied to the address input circuit 1.

Next, regarding the operation of the sense circuit 11 shown in FIG. 7, FIGS. 8, 9, and 10a to 10c.
Explain with reference to. First, one bit of data is held depending on whether the memory element 6 is present or not. That is, when the address input signal becomes "1" and there is a memory element 6, the memory transistor 6a is connected through the pull-up transistor 7.
A current flows through. Therefore, the level of point F is
0.2V is obtained. On the other hand, the address input is "0"
or "1", and if there is no memory element 6, no current flows through the pull-up transistor 7,
+V is obtained at the level of point F. Now, when the Q terminal of the D-type flip-flop 21 is "1" and the terminal is "0", the first transfer gate 13 is turned off and the second transfer gate 16 is turned on. Further, since the transistor 19c is turned on and the transistor 20c is turned off, the gate of the transistor 19b becomes +V, so that the transistor 19b is turned off. Further, since the gate of the transistor 20b is connected to point F through the second transfer gate 16, an inverter shown in FIG. 8 is configured. Now transistor 1
β of transistor 9a is β _P1 , β of transistor 20a is β _N1 ,
Let β of the transistor 20b be β _N2 , β _P1 = β _N1 ,
If β _N2 =3β _N1 and V _TP =V _TN , the threshold voltage V ^* in equation (3) above can be expressed as equation (4).

Here, if V _TP = 1V and V _DD = 5V, the threshold voltage V ^* = 0.4. This means that the sensing voltage drops below the threshold voltage V ^* =0.5 of the sensing circuit 4 shown in FIG.

Next, when the Q terminal of the D-type flip-flop 21 is "0" and the terminal is "1", the first transfer gate 13 is turned on and the second transfer gate 16 is turned off. In addition, the transistor 19
c is off and transistor 20c is on, so the gate of transistor 19b is connected to point F through the first transfer gate 13, and the gate of transistor 20b is connected to GND, so transistor 20b is off. As a result,
The inverter shown in FIG. 9 is constructed. Now, β of the transistor 19a is β _P1 , β of the transistor 19b is β _P2 , and β of the transistor 20a is
is β _N1 , β _P1 = β _N1 , β _P2 = 3β _P1 , and V _TP = V _TN , then the threshold voltage V ^* in equation (3) above can be expressed as equation (5).

Here, if V _TP = 1V and V _DD = 5V, the threshold voltage V ^* = 0.6. This means that the sensing voltage will rise above the threshold voltage V ^* =0.5 of the sensing circuit 4 shown in FIG.

Next, the D-type flip-flop 21 latches the output signal at the output terminal 10 at the falling edge of the clock. Therefore, the output terminal 10 is "0"
When , the latch is applied at the falling edge of the clock, and D
The flip-flop 21 operates, the Q terminal becomes "0", and the terminal becomes "1". Also, when the output terminal 10 is "1", it is latched at the falling edge of the clock, the D-type flip-flop 21 operates, the Q terminal becomes "1", and the terminal becomes "0".
become. That is, when the F point is 0.2V, the output terminal 10 becomes +V (logically "1"). When this data is latched with a clock, the Q terminal becomes "1" and the terminal becomes "0", so
The sense inverter can be shown in the configuration shown in FIG. The voltage of this inverter is V ^* = 0.4
becomes. Therefore, when the address changes and then the F point changes from 0.2V to +V, the threshold voltage V ^* of the sense circuit 4 shown in FIG. 3 is 0.5, but the sense circuit shown in FIG. 4 threshold voltage V ^* = 0.4
Therefore, it takes only a short time for the F point to rise from 0.2V and reach the threshold voltage V ^* . Next, F
When the point is +V, the output terminal 10 becomes GND (logically "0"). Therefore, when this output data is latched by the clock by the D-type flip-flop 21, the Q terminal becomes "0".
Since the terminal becomes "1", the sensing inverter can be shown in the configuration shown in FIG. The average voltage of this inverter is V ^* = 0.6. Therefore, the address changes and then point F becomes +V
When the voltage changes from to 0.2V, the threshold voltage V ^* of the sense circuit 4 shown in FIG. 3 is 0.5V, but the threshold voltage V ^* of the sense circuit 11 shown in FIG. 7 becomes 0.6, so F The time required for the point to fall from +V and reach V ^* is short. That is, as shown in FIG. 10a, the output signal of the output terminal 10 shown in FIG. 7 is output at the timing shown in FIG. The output signal of the output terminal 10 shown in FIG. 10 is outputted at the timing shown in FIG. 10b. Therefore, the output signal can be accelerated by T ₁ as shown in FIG. 10c.

As a clock signal for the D-type flip-flop 21, a signal generated when the address changes may be used, or a chip select signal applied after the address is set, of course.

In the above embodiment, complementary MOS transistors are used, but it is of course possible to use only N-channel MOS transistors or P-channel MOS transistors. Furthermore, it goes without saying that the circuit for changing the threshold voltage is not limited to the above-mentioned circuit.

As described above in detail, the memory device according to the present invention has the effect of speeding up the access time by changing the threshold voltage of the sense circuit based on the output signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional read-only memory device, FIGS. 2a to 2c are diagrams showing waveforms of each part in FIG. 1, and FIG. 3 is a detailed diagram showing the sense circuit in FIG. A circuit diagram, Fig. 4 is a diagram showing the input voltage/current characteristics of the sense circuit in Fig. 3, Fig. 5 is an input/output characteristic diagram showing the threshold voltage of the sense inverter,
FIG. 6 is a block diagram showing one embodiment of the memory device according to the present invention, FIG. 7 is a detailed circuit diagram of the sense circuit of FIG. 6, and FIGS. 8 and 9 explain the operation of FIG. 7. Circuit diagram for
FIG. c is a timing diagram for explaining the operation of the sense circuit of FIG. 3 and the operation of the sense circuit of FIG. 7. DESCRIPTION OF SYMBOLS 1... Address input circuit, 2... Address decoding circuit, 3... Memory array, 4... Sense circuit, 5... Data output circuit, 6... Memory element,
6a...Memory transistor, 7...Pull-up transistor, 8 and 9...Transistor,
10...Output terminal, 11...Sense circuit, 12...
...Latch circuit, 13...First transfer gate, 14 and 15...Transistor, 16...
Second transfer gate, 17 and 18...transistor, 19a-19c...transistor,
20a-20c...Transistors, 21...D-type flip-flops. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Address input circuit, address decoding circuit,
The memory device includes a memory array, a sense circuit, and a data output circuit, and includes a flip-flop type latch circuit that stores the state of a selected memory in the memory array, and the sense circuit is activated by an output signal of the latch circuit. A memory device characterized in that a threshold voltage is controlled.