JPH1166875A - Semiconductor storage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the high speed of a read rate by wiring a speed reference cell similarly with a cell being a position where is the farest from the sense amplifier of a cell array and generating a signal permitting the outputting of data from an output buffer when expectations of 0 and 1 from the speed reference cell are read out and to make a delay time for reading data minimum. SOLUTION: The output permitting circuit constituted of a speed reference cell 80, sense amplifiers 82, 84, an inverter 85 and an AND circuit 86 is provided in this circuit and this circuit generates a signal the inverse of OE to supply it to an output buffer 30. The speed reference cell 80 is made to be the same constitution as that of a cell array 26 and expectations 0 and 1 are preliminarily set in the cell 80. The wiring length between the speed reference cell 80 and the sense amplifiers 82, 84 is made to be the same length as that of the cell being a position where is the farest from the sense amplifier 16 being the cell array 26 or more. The sense amplifiers 82, 84 are made to be respectively the same constitution as that of the sense amplifier 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory circuit, and more particularly, to a nonvolatile semiconductor memory circuit. 2. Description of the Related Art A nonvolatile semiconductor memory circuit is widely used as a semiconductor memory device in conjunction with an MPU (microprocessor unit) and peripheral circuits. As the speeds of these MPUs and peripheral circuits are increased, higher-speed read operations are required.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a conventional semiconductor memory circuit. In FIG. 1, when a low-level signal CE / is supplied from a control terminal 10 to a control buffer 12, the control buffer 12 outputs a low-level signal PD and the address buffer 14 and the sense amplifier 16 are activated. When the address buffer 14 is activated and an address coming from the address terminal 20 is determined, the address buffer 14 supplies the row address and the column address to the row decoder 22 and the column decoder 24 respectively, and A specific cell is selected, and the output potential of the selected cell is supplied to the sense amplifier 16.

On the other hand, the reference cell 28 generates a reference potential serving as a read reference, that is, an intermediate potential between “0” and “1” output from each cell of the cell array 26 and supplies the same to the sense amplifier 16. The sense amplifier 16 compares the reference potential the output potential of the selected cell is supplied to the output buffer 30 as the data RD _n reads the comparison result, the data is output through the output terminal 32 as output data IO _n.

However, due to the circuit operation of the sense amplifier 16,
At the time of access immediately after activation, there is a possibility that inverted data obtained by inverting read data is output. For this reason, the signal PD output from the control buffer 14 is
, A signal / OE is generated, and the output of the output buffer 30 is permitted by the supply of the signal / OE to prevent the output of the reverse data.

FIG. 8 is a circuit diagram showing an example of the sense amplifier 16. In the figure, a p-channel MOS transistor like a MOS transistor P1 is hatched, and an n-channel MOS transistor like a MOS transistor N1 is distinguished without a hatch. In FIG. 9, the amplification unit 34
Indicates that when the signal PD goes low, the reference cell 28
Is amplified, converted to a reference voltage SAREF, and supplied to the gate of the n-channel MOS transistor N2 of the comparison unit 36. Similarly, when the signal PD goes low, the amplifier 38 amplifies the output current of the selected cell 40, converts it to a voltage SAIN, and supplies the voltage SAIN to the gate of the n-channel MOS transistor N3 of the comparator 36. Comparing unit 36 compares the above reference voltage SAREF voltage SAIN, reading the data RD _n toward the terminal 40 to the output buffer 30 outputs as a result of the comparison.

FIG. 9 is a circuit diagram showing an example of the delay circuit 18. In the figure, a signal PD is supplied to a terminal 42. When the signal PD is at the high level, the output of the NOR circuit is at the low level, and a high-level signal / OE is output from the terminal 48 through the inverter 46. Here, after a predetermined time has elapsed after the signal PD has become low level, the capacitors C1 and C2
After each accumulated charge is discharged through each of the resistors R1 and R2 in the inverter, the output of the NOR circuit 44 goes high and the signal / OE goes low.

FIG. 10 is a circuit diagram showing an example of the output buffer 30. In the figure, the read data RD _n from the sense amplifier 16 is supplied to the terminal 50, the terminal 52 signal /
OE is supplied. When the signal / OE is at a high level, the output of the NOR circuit 54 is at a low level and the p-channel MOS transistor P5 is off, and the output of the NAND circuit 56 is at a high level and the n-channel MOS transistor N5 is off and the terminal 32 is in a high impedance state. , Data R
D _n is not output. When the signal / OE goes low, the data RD _n is a NOR circuit 54, is supplied to people MOS transistors P5, N5 respectively through s NAND circuit 56 respectively, where it is inverted and output as output data IO _n from the terminal 32.

FIG. 12 is a block diagram showing another example of a conventional semiconductor memory circuit. In the figure, a low-level signal CE /
Is supplied, the control buffer 52 outputs a low-level signal PD, and the address buffer 54, the sense amplifier 56, the output buffer 70, and the ATD buffer 74 are activated. When the address buffer 54 is activated and the address coming from the address terminal 60 is determined, the address buffer 54 supplies the row address and the column address to the row decoder 62 and the column decoder 64, respectively, and A specific cell is selected, and the output potential of the selected cell is applied to sense amplifier 66.
Supplied to Note that an ATD (address / tradition detector) buffer 74 is provided in the address buffer 54.
, And supplies the detected pulse to the row decoder 62, the sense amplifier 56, the delay circuit 58, and the reference cell 68 to activate them.

On the other hand, the reference cell 28 generates a reference potential serving as a read reference, that is, an intermediate potential between “0” and “1” output from each cell of the cell array 66 and supplies it to the sense amplifier 66. The sense amplifier 66 compares the reference potential the output potential of the selected cell is supplied to the data latch 78 as the data RD _n reads the comparison result, which is output from the output terminal 72 as output data IO _n through an output buffer 70 You.

Due to the circuit operation of the sense amplifier 56, there is a possibility that the inverted data obtained by inverting the read data is output at the time of access immediately after activation, so that after the detection pulse output from the ATD buffer 74 is delayed by the delay circuit 58, A latch pulse is generated by a pulse generator 76, and the sense amplifier 56 is generated by a data latch 78 using the latch pulse.
By latching the output and supplying it to the output buffer 70, the output of the reverse data is prevented.

[0011]

In the conventional circuit of FIG. 7 [SUMMARY OF THE INVENTION], 11 (A), the after signal PD at time t ₀ is down standing, the word line voltage WL applied to the gate of the cell 40 The reference word line voltage RWL supplied to the gate of the reference cell 28 rises with a delay. The amount of delay differs depending on the load on the word line, that is, whether the cell is located closer to or farther from the sense amplifier of the word line.

As for the cell at the close position, the data held in the cell is "1" and "0", and the voltage SAIN is
The voltage changes as shown by solid lines Ia and Ib in FIG. 1 (B), but when the data held in the distant cell is “0”, the voltage SAI
N rises along the solid line Ib first, as shown by the broken line Ic, and then falls and approaches the solid line Ia. Therefore, the read data RD _n is "1" in the cell of the close, "0" solid IIa when, with respect to changes as IIb, the farther the read data RD _n of the cell is "1" At this time, as shown by the solid line IIc, it first falls as shown by the solid line IIb, then rises and approaches the solid line IIa. For this reason, the output data of the cell at the close position is “1” and “0”, respectively, as shown in FIG.
However, the output data of the cell at a position far from the cell changes as shown by the solid lines IIIa and IIIb, and is "1" and "0", respectively.
Changes like IIId.

That is, the period T ₁ is a data indefinite period, and if the fall of the signal / OE falls within the period T ₁ as shown by the broken line IV, there is a possibility that inverted data will be output.
The fall of only ₂ to delayed signal / OE are outside the period T ₁ as shown by the solid line V. In order to increase the read speed of the nonvolatile semiconductor memory circuit, it is very important to increase the speed after the circuit is activated (hereinafter referred to as tCE). However, at tCE of the nonvolatile semiconductor memory circuit, a delay time is set to prevent reverse data as shown in FIG. 8, and no output is output during that time. The delay circuit 18 is generally a circuit determined by the time constant of the resistance R and the capacitance C, but has characteristics different from the inverse data coming from the sense amplifier 16, so that the inverse data is output even when the temperature or the voltage is changed. Must be set to not. As a result, there has been a problem that the delay time becomes long and the tCE can be prevented from increasing in speed.

Also, as shown in FIG.
The same applies to the case of controlling the latch of the read data by the delay circuit 58. In order to compensate for the operation, it is necessary for the delay circuit 58 to take a long delay time. The present invention has been made in view of the above points, and provides a semiconductor memory circuit capable of minimizing a data read delay time regardless of cell performance, an ambient temperature, and a power supply voltage and increasing a read speed. With the goal.

[0015]

According to a first aspect of the present invention, there is provided a semiconductor memory circuit for outputting data read by a sense amplifier from a cell array of a non-volatile memory via an output buffer. Wired in the same way as a cell at a distant position,
And a speed reference cell in which an expected value of "1" is set, and a signal for permitting output of data from the output buffer when expected values of "0" and "1" are read from the speed reference cell. And an output permission circuit for generating

As described above, since the expected value is read from the speed reference cell and the accurate data is read from the cell farthest from the sense amplifier in the cell array, the data output from the output buffer is permitted.
Accurate data reading is possible irrespective of the cell performance, ambient temperature, and power supply voltage, and it is not necessary to make the reading delay time excessive, and the reading speed can be increased.

According to a second aspect of the present invention, in a semiconductor memory circuit which latches data read by a sense amplifier from a cell array of a non-volatile memory by a latch circuit when an address changes and outputs the data, a position farthest from the sense amplifier of the cell array Is wired in the same manner as the cell of
And a speed reference cell in which an expected value of "1" is set and a signal instructing the latch circuit to latch from the expected value of "0" and "1" read from the speed reference cell when the address changes. A latch instruction circuit.

As described above, the expected value of the speed reference cell is read out, and the sense amplifier output is latched at the timing when accurate data is read from the cell farthest from the sense amplifier of the cell array, and the data output is performed. Accurate data reading is possible irrespective of the cell performance, ambient temperature, and power supply voltage, and it is not necessary to make the reading delay time excessive, and the reading speed can be increased.

[0019]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory circuit according to the present invention. In FIG. 1, when a low-level signal CE / is supplied from the control terminal 10 to the control buffer 12, the control buffer 12
Outputs a low-level signal PD to output the address buffer 1
4 and the sense amplifiers 16, 82, 84 are activated. When the address buffer 14 is activated and an address coming from the address terminal 20 is determined, the address buffer 14 supplies the row address and the column address to the row decoder 22 and the column decoder 24 respectively, and A specific cell is selected, and the output potential of the selected cell is supplied to the sense amplifier 16.

On the other hand, the reference cell 28 generates a reference potential serving as a read reference, that is, an intermediate potential between “0” and “1” output from each cell of the cell array 26 and supplies the same to the sense amplifier 16. The sense amplifier 16 compares the reference potential the output potential of the selected cell is supplied to the output buffer 30 as the data RD _n reads the comparison result, the data is output through the output terminal 32 as output data IO _n.

However, due to the circuit operation of the sense amplifier 16,
At the time of access immediately after activation, there is a possibility that inverted data obtained by inverting read data is output. Therefore, the speed reference cell 80 and the sense amplifiers 82 and 84
, An inverter 85 and a NAND circuit 86 are provided, and the output permission circuit generates a signal / OE and supplies it to the output buffer 30.

The speed reference cell 80 has the same configuration as that of the cell array 26, and has expected values “0” and “1” set in advance. The wiring length between the speed reference cell 80 and the sense amplifiers 82 and 84 is Of the cell farthest from the sense amplifier 16 in the cell. Each of the sense amplifiers 82 and 84 has the same configuration as the sense amplifier 16, and the reference cell 28
Is connected to

Each of the sense amplifiers 82 and 84 outputs "0" when the signal PD is at the high level, and outputs the NAND circuit 86.
Outputs the high level, but when the signal PD goes low, the expected values SRQ0 and SRQ1 that become “0” and “1” are read from the speed reference cell 80, respectively. The NAND circuit 86 outputs the low level signal / OE. Output. This is the same time as placing the read data RD _n farthest cell from the sense amplifier 16 of the cell array 26. After the signal / OE is at the low level, the output buffer 30 is output from the terminal 32 to read data RD _n from the sense amplifier 16 as the output data IO _n.

FIG. 2 is a circuit diagram showing one embodiment of each of the sense amplifiers 16, 82 and 84. In the figure, a p-channel MOS transistor like a MOS transistor P10 is hatched, and an n-channel MOS transistor like a MOS transistor N10 is distinguished without hatching.
2, when the signal PD goes low, the amplifier 88 amplifies the output current of the reference cell 28, converts the output current to the reference voltage SAREF,
The voltage is supplied to the gate of the transistor N12. Similarly, when the signal PD goes low, the amplifier 92 amplifies the output current of the cell 80a set to the expected value "0" or "1", converts the output current to the voltage SRREF0 or SRREF1, and
To the gate of the n-channel MOS transistor N13. The comparison unit 90 compares the reference voltage SAREF with the voltage S
RREF0 or SRREF1 is compared with the expected value data SRQ0 or SRQ1 as a comparison result.
To the output buffer 30.

Here, as shown in FIG.
After the signal PD falls at ₀ , the word line voltage WL and the reference word line voltage RWL supplied to the gate of the reference cell 28 rise with a delay. The amount of delay differs depending on the load on the word line, that is, whether the cell is located closer to or farther from the sense amplifier of the word line.

With respect to the cell at the close position, the data held in the cell is "1" and "0", and the voltage SAIN is
Although the voltage changes as shown by solid lines Ia and Ib in (B), when the data held in a cell at a far position is “0”, the voltage SAIN is changed.
First rises along the solid line Ib as shown by the broken line Ic, then falls and approaches the solid line Ia. Therefore, the read data RD _n is "1" in the cell of the close, "0" solid IIa when, with respect to changes as IIb, the farther the read data RD _n of the cell is "1" At this time, as shown by the solid line IIc, it first falls as shown by the solid line IIb, then rises and approaches the solid line IIa. Also, the sense amplifier 8
The voltages SRREF1 and SRREF0 of 2,84 are respectively shown in FIG.
The expected values SRQ1 and SRQ0 read out change as shown by the broken line IIIa and the solid line IIIb in FIG.
As shown in FIG. 3, the signal / OE is a solid line V in FIG.
As shown in (1), it falls after the data indefinite period.
As a result, the output data is "1" and "0", respectively, as shown in FIG.
The output is changed as shown by the solid lines VIa and VIb in (D).

As described above, when the read data SRQ0 and SRQ1 of the expected values “0” and “1” from the speed reference cell 80 similar to the cell farthest from the sense amplifier 16 of the cell array 26 are determined, the signal / OE is output. Since the data is output, accurate data reading with the reverse data output prevented can be performed in the shortest time irrespective of the cell performance, ambient temperature conditions, and fluctuations in the power supply voltage, and the speed of tCE can be improved.

FIG. 4 is a block diagram showing a second embodiment of the semiconductor memory circuit according to the present invention. In the figure, control terminal 50
To the control buffer 52 from the low level signal CE.
When / is supplied, the control buffer 52 outputs a low-level signal PD to output the address buffer 54, the sense amplifiers 56, 82, 84, the output buffer 70, and the ATD.
Buffer 74 is activated. Address buffer 54
Is activated to supply the row address and the column address respectively to the row decoder 62 and the column decoder 64 when the address coming from the address terminal 60 is determined. Is selected, and the output potential of the selected cell is supplied to the sense amplifier 66. ATD (address
A transition detector buffer 74 detects a change in the address value supplied from the address buffer 54 and supplies the detected pulse to the row decoder 62, the reference cell 68, the speed reference cell 80, and the sense amplifiers 56, 82, and 84. And then launch these.

On the other hand, the reference cell 28 generates a reference potential serving as a read reference, that is, an intermediate potential between “0” and “1” output from each cell of the cell array 66 and supplies it to the sense amplifier 66. The sense amplifier 66 compares the reference potential the output potential of the selected cell is supplied to the data latch 78 as the data RD _n reads the comparison result, which is output from the output terminal 72 as output data IO _n through an output buffer 70 You.

Due to the circuit operation of the sense amplifier 56, there is a possibility that the inverted data obtained by inverting the read data is output at the time of access immediately after activation. Therefore, a latch instruction circuit including a speed reference cell 80, sense amplifiers 82 and 84, an inverter 85, and a NAND circuit 86 is provided. The latch instruction circuit generates a signal / OE and supplies the signal / OE to the output buffer 30. doing.

The speed reference cell 80 has the same configuration as the cell array 26, and has expected values “0” and “1” set in advance. The wiring length between the speed reference cell 80 and the sense amplifiers 82 and 84 is Of the cell farthest from the sense amplifier 16 in the cell. Each of the sense amplifiers 82 and 84 has the same configuration as the sense amplifier 16, and the reference cell 28
Is connected to

Each of the sense amplifiers 82 and 84 outputs "0" when the signal PD is at the high level, and outputs the NAND circuit 86.
Outputs a high level. When the signal PD goes low, the expected values SRQ0 and SRQ1 that become “0” and “1” are read from the speed reference cell 80, respectively. The NAND circuit 86 outputs the low level signal / SP. Output. This is the same time as placing the read data RD _n farthest cell from the sense amplifier 16 of the cell array 26. After the signal / SP becomes low level, the pulse generator 76 generates the latch pulse / LE, and the data latch 78 latches the output of the sense amplifier 56 using the latch pulse / LE, and supplies the output to the output buffer 70. , From the output terminal 72.

FIG. 5 is a circuit diagram of one embodiment of the pulse generator 76. In the figure, a signal / SP is supplied to a terminal 100, inverted by an inverter 102, and
04. The output of the inverter 102 is inverted by the cascade-connected inverters 106, 108, and 110 and supplied to the NAND circuit 104. As a result, the NAND circuit 104 generates a latch pulse / LE which is a negative-polarity pulse that has detected the fall of the signal / SP.
Output from 2.

Here, as shown in FIG.
After the signal PD falls at ₀ , the word line voltage WL and the reference word line voltage RWL supplied to the gate of the reference cell 28 rise with a delay. The amount of delay differs depending on the load on the word line, that is, whether the cell is located closer to or farther from the sense amplifier of the word line.

As for the cell at the close position, the data held in the cell is "1" and "0", respectively, and the voltage SAIN is
Although the voltage changes as shown by solid lines Ia and Ib in (B), when the data held in a cell at a far position is “0”, the voltage SAIN is changed.
First rises along the solid line Ib as shown by the broken line Ic, then falls and approaches the solid line Ia. Minotame, the read data RD _n is "0" in the cell of the close, "1" solid IIa when, with respect to change as IIb, read data RD _n of cells farther "1" At this time, as shown by the solid line IIc, it first falls as shown by the solid line IIb, then rises and approaches the solid line IIa.

Therefore, during the data indefinite period, FIG.
Conventionally, the latch pulse / LE shown by the solid line VIIb is generated with a large margin (delay time) so that the latch pulse shown by the broken line VIIa is not output.
In this embodiment, a latch pulse / LE having a minimum necessary margin can be generated as shown by a solid line VIIc, and reverse data output can be prevented in the shortest time irrespective of cell performance, ambient temperature conditions and fluctuations in power supply voltage. Thus, accurate data reading can be performed, and the speeding up of tCE can be improved.

[0037]

As described above, the first aspect of the present invention provides
In a semiconductor memory circuit that outputs data read by a sense amplifier from a cell array of a nonvolatile memory via an output buffer, the semiconductor memory circuit is wired in the same manner as a cell farthest from the sense amplifier of the cell array, and is previously set to “0” and “1”. A speed reference cell in which an expected value is set, and “0” and “1” from the speed reference cell.
And an output permitting circuit for generating a signal for permitting output of data from the output buffer when the expected value is read out.

As described above, since the expected value is read from the speed reference cell and the accurate data is read from the cell farthest from the sense amplifier of the cell array, data output from the output buffer is permitted.
Accurate data reading is possible irrespective of the cell performance, ambient temperature, and power supply voltage, and it is not necessary to make the reading delay time excessive, and the reading speed can be increased.

According to a second aspect of the present invention, there is provided a semiconductor memory circuit in which data read by a sense amplifier from a cell array of a nonvolatile memory is latched and output by a latch circuit when an address changes, and A speed reference cell that is wired in the same manner as a cell at a distant position, and has an expected value of “0” and “1” set in advance, and an expected value of “0” and “1” read from the speed reference cell when the address changes. A latch instruction circuit for generating a signal for instructing the latch circuit to latch from the value.

As described above, the expected value of the speed reference cell is read, and the output of the sense amplifier is latched at the timing when accurate data is read from the cell farthest from the sense amplifier of the cell array, and the data is output. Accurate data reading is possible irrespective of the cell performance, ambient temperature, and power supply voltage, and it is not necessary to make the reading delay time excessive, and the reading speed can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a main part circuit diagram of the delay control circuit of the present invention.

FIG. 3 is a signal waveform diagram of FIG.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a pulse generator.

FIG. 6 is a signal waveform diagram of FIG.

FIG. 7 is a block diagram of a conventional circuit.

FIG. 8 is a circuit diagram of a sense amplifier.

FIG. 9 is a circuit diagram of a delay circuit.

FIG. 10 is a circuit diagram of an output buffer.

11 is a signal waveform diagram of FIG.

FIG. 12 is a block diagram of a conventional circuit.

[Explanation of symbols]

 12 Control Buffer 14 Address 16, 82, 84 Sense Amplifier 22 Row Decoder 24 Column Decoder 26 Cell Array 28 Reference Amplifier 30 Output Buffer 74 ATD Buffer 76 Pulse Generator 78 Data Latch 80 Speed Reference Cell 85 Inverter 86 NAND Circuit

Claims (2)

[Claims] 1. A semiconductor memory circuit for outputting data read by a sense amplifier from a cell array of a nonvolatile memory via an output buffer, wherein the semiconductor memory circuit is wired in the same manner as a cell farthest from the sense amplifier of the cell array, and is set to "0" in advance. A speed reference cell set with expected values of "1" and "1"; and when the expected values of "0" and "1" are read from the speed reference cell, output of data from the output buffer is permitted. A semiconductor memory circuit having an output permission circuit for generating a signal. 2. A semiconductor memory circuit which latches data read out from a cell array of a nonvolatile memory by a sense amplifier by a latch circuit when an address changes and outputs the data, in the same manner as a cell farthest from the sense amplifier in the cell array. A speed reference cell in which expected values of “0” and “1” are set in advance, and an instruction to latch the latch circuit based on expected values of “0” and “1” read from the speed reference cell when the address changes. And a latch instructing circuit for generating a signal to perform the operation.