JPS6257196A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the reliability of a memory operation that conforms the physical state and logic state of a memory cell by making a logic circuit that controls the normal and reverse rotation of data while the output of a sense amplifier is unstable a non-output state. CONSTITUTION:In EPROM of a memory in which the physical state and logic state of the memory cell MC are coincident with each other in an open bit line system, a controlling signal A0 that accompanies the change of address is delayed by the delay circuit 11 of a data normal/reverse rotation circuit 10. Accordingly, an FF 13 that latches the output of an exclusive OR circuit 12 that rotates the output of a sense amplifier normally or reversely according to the selection of the cell MC of a bit line BL or a reverse BL during delay time of the circuit 11 when a new cell MC is selected through a word line WL by the change of address remains as it is while latching the output of an amplifier SA corresponding to a cell MC selected just before. Consequently, data having the unnecessary change of amplitude when the output of the amplifier SA is unstable are not outputted, and the reliability of EPROM is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a data forward/inversion circuit for a semiconductor memory in which the physical state and logical state of memory cell data are required to match. .

[Technical background of the invention]

In nonvolatile memories such as EFROM (ultraviolet erasable and rewritable read-only memory) and EEFROM (electrically erasable and rewritable read-only memory), the physical state and logical state of memory cell data must match. For example, the erased state in which no charge is accumulated in the floating boot of a memory cell transistor is determined as data "'11". The area around the sense amplifier has a configuration as shown in Figure 5. That is, the bit line BL is connected to the latch type differential sense amplifier SA using an open bit line method.
, BL are connected to one bit line BL, and a large number of memory cells MC (representatively only one is shown) and one reference cell RC are connected to one bit line BL. In addition, the other bit line BL also has a large number of memory cells MC... and 1.
Reference cells RC are connected to each other, and each of these is selected by a word line WL . . . . Reference numeral 50 denotes a data normal rotation/inversion circuit for changing the logic level of the output data of the sense antenna 7'SA as it is or inverting it (l), the output data of which is read out to the data output terminal 52 via the output buffer 51. The data normal rotation/inversion circuit 50 has a transfer gate 53 connected between the input terminal and the output terminal, which is dart-controlled by a control signal A applied when selecting a memory cell on the bit line BL side. An inverter circuit 54 and a transfer gate 55 which is dart-controlled by a control signal A applied when selecting a memory cell on the bit line BL side are connected in series between the input and output terminals. P
R is a bit line precharge/equalization circuit, which is made up of transfer gates Q1 and Q2 for precharging and a transfer gate Q3 for equalization, to which a precharging pulse φpit is applied.

Next, the operation of the memory having the above configuration will be explained with reference to FIG. First, a bit line precharge pulse φPI is generated in synchronization with a change in address switching, and the bit line precharge/equalize circuit PR precharges and equalizes the bit lines BL, BL. At the same time, the sense latch signal φL becomes inactive, and the latches of the eight sense amplifiers are released.

After the precharging is completed, the memory cell MC on the bit line BL side (or the memory cell MC on the bit line BL side) and the reference cell RC on the bit line BL side (or the reference cell RC on the bit line BL side) are selected, The potentials of the bit lines BL, BL start to drop according to their respective conductances (free running state). Then, after a certain period of time, the false latch signal φL becomes active, and the potential difference that has been generated between the bit lines BL and BL up to this time is sense-amplified and latched by the sense amplifier 7''SA.

Note that the conductance of the reference cell RC is the same as that of the memory cell M.
The conductance in the "'1" state (erased state) of C is large, and the conductance in the @0" state (written state) is small.

By the way, the case where the '1' state is sensed when the memory cell MC on the bit line BL side is selected and the case where the 'O' state is sensed when the memory cell MC on the bit line BL@ side is selected are the 8 sense amplifiers. The output data of will be the same.

Therefore, in order to make the physical state and logical state of memory cell data correspond, the output data of the sense amplifier SA is transferred to the data forward/inverter circuit 5o according to the left and right address selection of the sense amplifier SA. It is necessary to pass it through as is or reverse it.

In the open bit line method described above, the parasitic capacitance of the bit line is equal on the left and right sides of the sense amplifier, so
It is possible to sense even relatively small potential differences between bit lines, which is advantageous for large-capacity, highly integrated memories where memory cells may have low conductance.

[Problems with background technology]

By the way, the above-mentioned memory has the following problems. After the address changes, the timing from word line selection to the output response of the sense amplifier SA and the dart control input signal A or A to the data forward/inversion circuit 50.
The timing until o is given is not necessarily the same. Therefore, the timing t! where the dart control input signal A or human ◎ is earlier than the output response of the sense amplifier SA! When the data normal rotation/inversion circuit 50 changes, the data output of the data normal rotation/inversion circuit 50 is inverted once, and then becomes the normal output data level at timing t2 when the output of the sense amplifier 7'8A changes. Conversely, if the dart control input signal AO or A changes at timing t3, which is later than the output response of the sense amplifier fsk, the output of the data normal rotation/inversion circuit 50 changes at timing 1.1 of the change in the output of the sense amplifier SA. Then, at the timing t3, the output becomes the normal output f-Tarepel. In this way, the curved waveform that occurs in the output of the data normal rotation/inversion circuit 50 appears at the data output terminal 52 via the output buffer 51. This data output terminal 52 usually drives a large-capacitance load such as a pass line, and a large current is generated due to the above-mentioned bus-like changing waveform, and the peak of this large current is There is a risk that noise components will be induced into the power supply line of the memory, leading to malfunction of the memory.

In addition, especially in open bit line memory, it is necessary to charge and equalize the bit lines Bl, BL with a precharge pulse φPi before selecting a memory cell, and this precharge is necessary. During this period, the output of the sense amplifier SA is always at a constant logic level.

Therefore, in the worst case, the output data obtained at the data output terminal 52 from the precharge period to the sense amplification period will have a complicated waveform with many amplitude changes, which will induce noise noise in the power supply line, thereby causing the grid charge pulse. There is a possibility that feedback may occur in which erroneous generation of data occurs, resulting in malfunction of the memory.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is a semiconductor that can perform normal rotation/inversion processing on the sense amplifier output so as to prevent unnecessary amplitude changes from occurring in the data output, and that can improve the reliability of memory operation. It provides memory.

[Summary of the invention]

That is, the present invention has an open bit line method or a folded bit line method, and uses data normal rotation and inversion to normalize and invert sense amplifier output data in order to match the physical state and logical state of memory cell data. In a semiconductor memory having an inverting circuit, the above-mentioned data can be rotated normally or
The inversion circuit consists of a logic circuit whose forward/inversion operation is controlled by a control signal indicating which of the bit line pairs to select the memory cell connected to, and a flip-flop which latches the output of this logic circuit. The logic circuit disables the unstable period of sense amplifier output data when selecting a memory cell (Dlsabl).
・ ) state (non-output state).

As a result, during the unstable period of sense amplifier output data when memory is selected, the output data of the flip-flop circuit that latches the previous output data remains unchanged, resulting in unnecessary amplitude changes in the output. This eliminates the risk of malfunction due to noise, and improves the reliability of memory operation.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

Figure 1 shows an lPRO that uses an open bit line method.
5 shows a part of M, except that the data normal rotation/inversion circuit 10 is different from the configuration described above with reference to FIG. Therefore, the explanation will be omitted. The data normal rotation/inversion circuit 10 includes a control signal A representing address selection on the left (or right) side of the sense amplifier SA, a delay circuit 11 that delays the large input by a predetermined amount, and the output data of the sense amplifier 8A and the above data. When the output of the delay circuit 11 is input and the control signal φL' becomes active, exclusive OR processing is performed and output, and the control signal φL'
an exclusive OR circuit 12 which is in a disabled state when is in an inactive state;
and a flip-flop circuit 13 that latches the output of.

Next, the operation of the above configuration will be explained with reference to FIG. The operation from address change to latching operation of sense amplifier SA is the same as that of the conventional example shown in FIG.

At this time, in the data normal rotation/inversion circuit 10, the control signal φL' is in phase with the sense latch signal φL and becomes inactive (low level in this example) at the same time, and is exclusive during the bit line precharge period and free running period. Since the digital OR circuit 12 is brought into a discontinuous state, the 7-lip 70 logic circuit 13 does not change, and the circuit output terminal 14 remains at the state 1 before the address change. Then, the latch sense signal φL becomes active and the sense amplifier SA performs a latch operation, and around the time when the output data S becomes stable and is input to the exclusive OR circuit 12, the control signal φ
L becomes active. That is, the control signal φL is set to become active with a delay of a certain time Δt compared to the latch sense signal φL. Furthermore, when the control signal A6 is input to the delay circuit 11 in response to an address change, it is delayed by a certain time td, and the delayed control signal A is generated before the latch sense signal φL becomes active, causing exclusive input to the logical OR circuit 12. Therefore, when the control signal φ1' becomes active, exclusive OR processing is performed and its output is latched by the flip-flop circuit 13. Therefore, when the delay control signal φ1' is present, the sense amplifier 7 'SA output data S @118. "'0' corresponds to each O".

When the delay control signal A o/ is not present, the output data S of the sense amplifier SA is inverted to “1” and output.
0#, $11" remains at its logic level (non-inverted state,
output in normal rotation state). That is, the normal rotation/inversion operation of the data normal rotation/inversion circuit 10 is switched in accordance with the left and right address selections of the eight sense amplifiers, so that the physical state and logical state of the memory cell data correspond to each other. Become.

According to the operation of the data normal rotation/inversion circuit 10 as described above, the data output remains unchanged until the control signals φ,' become active, and when the signal φL becomes active, the data output changes. Update (same logical level t''
In the worst case, the data output level transitions only once (in the case where the logic level is inverted due to the data output update mentioned above). Since unnecessary amplitude changes are no longer included in the data output, memory malfunctions due to unnecessary amplitude changes do not occur, and the reliability of memory operation is improved.

'Note that FIG. 3 shows an example in which the data normal rotation/inversion circuit 10 is constituted by an 0MO8 (complementary insulated dart type) circuit. That is, the delay circuit 11 includes CMOS inverters 31 and 32 connected in series, and a capacitor 33 connected between this connection point and the V□ potential (ground potential). The two-man exclusive OR circuit 12 includes a CMOS inverter 34 .
35 and N-channel enhancement fiMO8) Transistor Nt~N1 and P-channel enhancement type MO8
) The transistors P1 to Ps are connected as shown. Further, the flip-flop circuit 13 includes CMOS inverters 36 and 37 connected in antiparallel.

According to the above CMO8 circuit, when the control signal φ1' is in an inactive state, the N-channel transistor N! ,N,
is off, the output of the inverter circuit 35 “1#6
p channel transistor P! eP5 is also turned off. Therefore, during the precharge period, the output data S of the sense amplifier 7'SA changes to the logic level '''' as the bit line potential changes.
1”.

Even if the potential is at an intermediate potential of θ', no buy-back current flows through the CMO8 circuit, making it possible to reduce power consumption.

Note that the present invention is applicable not only to the open bit line method as in the above embodiment but also to a semiconductor memory employing a folded bit line method.
Shown in the figure.

That is, mutually adjacent bit lines BL and BL connected in a folded manner to the sense amplifier SA have a plurality of memory cells MC and one reference cell R corresponding to each other.
C are connected to word lines WL and C, respectively.
Selected by...

In this case, when the memory cell MC on the bit line BL side is selected, the reference cell RC on the bit line BL side is selected, and conversely, when the memory cell MC on the bit line n side is selected, the bit line The reference cell RC on the line BL side is selected. Then, a control signal A corresponding to selecting one of the memory cells MC on the side of the T line (for example, BL).

and the output data S of the sense amplifier SA are guided to the data normal rotation/inversion circuit 10 similar to the previous embodiment and processed.

〔Effect of the invention〕

As described above, according to the semiconductor memory of the present invention, the sense amplifier output can be normally rotated or reversed so that unnecessary amplitude changes do not occur in the data output, and the reliability of memory operation can be improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a data forward/inversion circuit in a semiconductor memory of the present invention, FIG. 2 is a timing waveform diagram showing a read operation of the memory shown in FIG. 1, and FIG. 3 is a diagram similar to that shown in FIG. A circuit diagram showing a specific example of the data normal rotation/inversion circuit inside, FIG. 4 is a circuit diagram showing another embodiment of the present invention,
FIG. 5 is a circuit diagram showing a data forward/inversion circuit in a conventional semiconductor memory, and FIG. 6 is a timing waveform diagram showing a read operation of the memory shown in FIG. SA...Sense amplifier, BL, BL...Bit line,
MC...Memory cell, RC...Reference cell, An...
・Control signal, 10...-Data forward rotation/inversion circuit, 11.
...Delay circuit, 12...Exclusive OR circuit, 13...
- Frizzofrog circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (2)

[Claims] (1) It has an open bit line method or a folded bit line method, and in order to match the physical state and logical state of memory cell data, the memory cell is connected to which bit line of the bit line pair. In a semiconductor memory having a data normal rotation/inversion circuit that performs normal rotation/inversion of the output data of a sense amplifier depending on whether the data is selected, the data normal rotation/inversion circuit is connected to which bit line of the bit line pair. The logic circuit has a logic circuit in which normal/inverted data operation is controlled by a control signal indicating whether to select a memory cell selected by the memory cell, and a flip-flop circuit that latches the output of this logic circuit. 1. A semiconductor memory characterized in that the semiconductor memory is controlled to be in a non-output state during an unstable period of sense amplifier output data. (2) The semiconductor memory according to claim 1, wherein the logic circuit is an exclusive OR circuit that performs exclusive OR processing on the sense amplifier output data and the control signal.