JPS59231792A - 多重ポ−ト・メモリ・システム - Google Patents

多重ポ−ト・メモリ・システム

Info

Publication number
JPS59231792A
JPS59231792A JP59026215A JP2621584A JPS59231792A JP S59231792 A JPS59231792 A JP S59231792A JP 59026215 A JP59026215 A JP 59026215A JP 2621584 A JP2621584 A JP 2621584A JP S59231792 A JPS59231792 A JP S59231792A
Authority
JP
Japan
Prior art keywords
transistor
line
transistors
coupled
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59026215A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0210516B2 (de
Inventor
ケリ−・バ−ンスタイン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS59231792A publication Critical patent/JPS59231792A/ja
Publication of JPH0210516B2 publication Critical patent/JPH0210516B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP59026215A 1983-05-31 1984-02-16 多重ポ−ト・メモリ・システム Granted JPS59231792A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US499730 1983-05-31
US06/499,730 US4616347A (en) 1983-05-31 1983-05-31 Multi-port system

Publications (2)

Publication Number Publication Date
JPS59231792A true JPS59231792A (ja) 1984-12-26
JPH0210516B2 JPH0210516B2 (de) 1990-03-08

Family

ID=23986459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59026215A Granted JPS59231792A (ja) 1983-05-31 1984-02-16 多重ポ−ト・メモリ・システム

Country Status (4)

Country Link
US (1) US4616347A (de)
EP (1) EP0127023B1 (de)
JP (1) JPS59231792A (de)
DE (1) DE3479616D1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010537351A (ja) * 2007-06-25 2010-12-02 クゥアルコム・インコーポレイテッド 並列多次元ワードアドレス可能メモリアーキテクチャ
JP2013152778A (ja) * 2013-02-28 2013-08-08 Qualcomm Inc 並列多次元ワードアドレス可能メモリアーキテクチャ
WO2015019411A1 (ja) * 2013-08-06 2015-02-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4535428A (en) * 1983-03-10 1985-08-13 International Business Machines Corporation Multi-port register implementations
US4616347A (en) * 1983-05-31 1986-10-07 International Business Machines Corporation Multi-port system
US4577292A (en) * 1983-05-31 1986-03-18 International Business Machines Corporation Support circuitry for multi-port systems
US4719602A (en) * 1985-02-07 1988-01-12 Visic, Inc. Memory with improved column access
US4742487A (en) * 1986-04-15 1988-05-03 International Business Machines Corporation Inhibit and transfer circuitry for memory cell being read from multiple ports
US4815038A (en) * 1987-05-01 1989-03-21 Texas Instruments Incorporated Multiport ram memory cell
JPH01178193A (ja) * 1988-01-07 1989-07-14 Toshiba Corp 半導体記憶装置
US4937781A (en) * 1988-05-13 1990-06-26 Dallas Semiconductor Corporation Dual port ram with arbitration status register
US4873665A (en) * 1988-06-07 1989-10-10 Dallas Semiconductor Corporation Dual storage cell memory including data transfer circuits
US5532958A (en) * 1990-06-25 1996-07-02 Dallas Semiconductor Corp. Dual storage cell memory
US5629907A (en) * 1991-06-18 1997-05-13 Dallas Semiconductor Corporation Low power timekeeping system
US5544078A (en) * 1988-06-17 1996-08-06 Dallas Semiconductor Corporation Timekeeping comparison circuitry and dual storage memory cells to detect alarms
US5287485A (en) * 1988-12-22 1994-02-15 Digital Equipment Corporation Digital processing system including plural memory devices and data transfer circuitry
US5235543A (en) * 1989-12-29 1993-08-10 Intel Corporation Dual port static memory with one cycle read-modify-write
US5142540A (en) * 1990-03-13 1992-08-25 Glasser Lance A Multipart memory apparatus with error detection
US5189640A (en) * 1990-03-27 1993-02-23 National Semiconductor Corporation High speed, multi-port memory cell utilizable in a BICMOS memory array
US5502683A (en) * 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control
US5579206A (en) * 1993-07-16 1996-11-26 Dallas Semiconductor Corporation Enhanced low profile sockets and module systems
US5528463A (en) * 1993-07-16 1996-06-18 Dallas Semiconductor Corp. Low profile sockets and modules for surface mountable applications
US8397034B1 (en) 2003-06-27 2013-03-12 Cypress Semiconductor Corporation Multi-port arbitration system and method
US7516280B1 (en) 2004-03-30 2009-04-07 Cypress Semiconductor Corporation Pulsed arbitration system and method
US7813213B1 (en) 2005-05-04 2010-10-12 Cypress Semiconductor Corporation Pulsed arbitration system

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2135625B1 (de) * 1971-07-16 1973-01-04 Ibm Deutschland Gmbh, 7000 Stuttgart Schaltungsanordnung zur automatischen Schreib-Unterdrückung
US3896417A (en) * 1973-11-30 1975-07-22 Bell Telephone Labor Inc Buffer store using shift registers and ultrasonic delay lines
US4078261A (en) * 1976-01-02 1978-03-07 Motorola, Inc. Sense/write circuits for bipolar random access memory
US4104719A (en) * 1976-05-20 1978-08-01 The United States Of America As Represented By The Secretary Of The Navy Multi-access memory module for data processing systems
US4090258A (en) * 1976-12-29 1978-05-16 Westinghouse Electric Corp. MNOS non-volatile memory with write cycle suppression
US4183095A (en) * 1978-09-01 1980-01-08 Ncr Corporation High density memory device
US4314164A (en) * 1979-11-05 1982-02-02 Gte Automatic Electric Labs Inc. Computer channel access circuit for multiple input-output devices
US4535428A (en) * 1983-03-10 1985-08-13 International Business Machines Corporation Multi-port register implementations
US4558433A (en) * 1983-05-31 1985-12-10 International Business Machines Corporation Multi-port register implementations
US4616347A (en) * 1983-05-31 1986-10-07 International Business Machines Corporation Multi-port system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010537351A (ja) * 2007-06-25 2010-12-02 クゥアルコム・インコーポレイテッド 並列多次元ワードアドレス可能メモリアーキテクチャ
US8773944B2 (en) 2007-06-25 2014-07-08 Qualcomm Incorporated Concurrent multiple-dimension word-addressable memory architecture
JP2013152778A (ja) * 2013-02-28 2013-08-08 Qualcomm Inc 並列多次元ワードアドレス可能メモリアーキテクチャ
WO2015019411A1 (ja) * 2013-08-06 2015-02-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9515076B2 (en) 2013-08-06 2016-12-06 Renesas Electronics Corporation Semiconductor integrated circuit device
JPWO2015019411A1 (ja) * 2013-08-06 2017-03-02 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9711512B2 (en) 2013-08-06 2017-07-18 Renesas Electronics Corporation Semiconductor integrated circuit device
US9972629B2 (en) 2013-08-06 2018-05-15 Renesas Electronics Corporation Semiconductor integrated circuit device

Also Published As

Publication number Publication date
EP0127023B1 (de) 1989-08-30
EP0127023A3 (en) 1986-11-12
US4616347A (en) 1986-10-07
JPH0210516B2 (de) 1990-03-08
DE3479616D1 (en) 1989-10-05
EP0127023A2 (de) 1984-12-05

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