JPS59228736A - Multilayer interconnection method - Google Patents

Multilayer interconnection method

Info

Publication number
JPS59228736A
JPS59228736A JP10379383A JP10379383A JPS59228736A JP S59228736 A JPS59228736 A JP S59228736A JP 10379383 A JP10379383 A JP 10379383A JP 10379383 A JP10379383 A JP 10379383A JP S59228736 A JPS59228736 A JP S59228736A
Authority
JP
Japan
Prior art keywords
electrode
layer
lower layer
insulating layer
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10379383A
Other languages
Japanese (ja)
Other versions
JPH0337734B2 (en
Inventor
Sadazumi Shiraishi
白石 貞純
Yukio Motoyoshi
本吉 幸雄
Katsuaki Saida
斉田 克明
Seiji Kuwabara
誠治 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP10379383A priority Critical patent/JPS59228736A/en
Publication of JPS59228736A publication Critical patent/JPS59228736A/en
Publication of JPH0337734B2 publication Critical patent/JPH0337734B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To prevent the disconnection in a stepwise difference of an interlayer insulating layer of an upper layer electrode by forming a quasi-electrode in addition to a lower layer electrode pattern on the lower layer of the stepwise difference of the interlayer insulating layer, thereby utilizing the stepwise fifference due to the quasi-electrode. CONSTITUTION:An interlayer insulating layer 1 is formed of a lower layer electrode wiring pattern having a lower layer electrode 5 and a polyimide resin, and an upper layer electrode 4 is formed through the layer 1, thereby forming a multilayer interconnection structure. A lower layer electrode 6 which is conducted with the electrode 4 is formed via a through hole 2 on the lower layer of the stepwise difference 3 of the structure. Further, a quasi-electrode 8 is formed adjacent to the electrode 6, a sharp rise of the difference 3 is eliminated, thereby flattening the difference 3 as a whole. Then, the disconnection in the difference 3 of the insulating layer of the electrode 4 can be prevented.

Description

【発明の詳細な説明】 本発明はポリイミド樹脂によって形成さtた眉間絶縁層
金もつ多層配線において、該眉間絶縁層の段差部におけ
る上層電極の断線を防止することを目的としたものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The object of the present invention is to prevent disconnection of the upper layer electrode at the stepped portion of the glabellar insulating layer in a multilayer wiring having a glabellar insulating layer made of polyimide resin.

従来の方法ではポリイミド樹脂kFfa間絶縁層として
用いる場合、フォトリソ工程によって層間絶絶層パター
ンを形成しスルーホールなどを設けるが、その際層間絶
縁層パターンの段差部が必要とする層間絶縁層の厚み以
上に盛シ上がるため、上層電極形成時に段差部分で上層
電極の断線が生じやすいという欠点がおる。この欠点を
図面に基づいて説明する。第1図はポリイミド樹脂を層
間絶縁層とした場合の従来の多層配線構造の例を示す断
面および平面図である。眉間絶縁層lにおいてスルーホ
ール2を形成する場合にはフォトリソ工程によるわけで
あるが、その際該スルーホール2の段差部分3は必要と
する厚み以上に盛シ上がってしまうことが避けらtない
。この盛り上がシが鋭いために第2図に示すように上層
電極4を蒸着する際に、該上層電極4が該層間絶縁層1
の該段差部分3において断線してしまう。あるいは第3
図のように、蒸着時に断線しなくとも該上層電極4をフ
ォトリソ工程によって形成する場合、該段差部分3にお
けるフォトレジスト層7が薄いため該段差部分3におい
て該上層電極4がエツチング液によって侵食さし断線し
てし1う。このようにポリイミド樹脂を用いた場合の従
来の多層配線構造では、眉間絶縁層の段差部での鋭い盛
シ上がシに起因する上層電極の断線が発生しやすい。
In the conventional method, when polyimide resin kFfa is used as an interlayer insulation layer, an interlayer insulation layer pattern is formed by a photolithography process and through holes etc. are provided. Because of the increased height, there is a drawback that the upper layer electrode is likely to be disconnected at the step portion when forming the upper layer electrode. This drawback will be explained based on the drawings. FIG. 1 is a cross-sectional and plan view showing an example of a conventional multilayer wiring structure in which polyimide resin is used as an interlayer insulating layer. When forming the through hole 2 in the glabella insulating layer 1, a photolithography process is used, but in this case, it is inevitable that the stepped portion 3 of the through hole 2 will be raised to a thickness greater than the required thickness. . Because the raised edges are sharp, when the upper layer electrode 4 is deposited as shown in FIG.
The wire breaks at the stepped portion 3. Or the third
As shown in the figure, when the upper layer electrode 4 is formed by a photolithography process even if there is no disconnection during vapor deposition, the photoresist layer 7 at the step portion 3 is thin, so the upper layer electrode 4 at the step portion 3 is eroded by the etching solution. The wire was disconnected. In the conventional multilayer wiring structure using polyimide resin as described above, disconnection of the upper layer electrode is likely to occur due to sharp creases at the stepped portion of the glabella insulating layer.

本発明はこのような層間絶縁層段差部分における上層電
極の断線を防止することを目的としたものであシ、段差
部分下層に下層電極配線パターンに刃口えて擬似電極を
設けること全特徴としている。この方法は第1図に示し
たように、ポリイミド樹脂を用いた層間絶諜層が下層電
極配線パターンによる段差全そのまま反映して形成さn
ることを積極的に利用するものである。
The purpose of the present invention is to prevent disconnection of the upper layer electrode at such a stepped portion of the interlayer insulating layer, and the present invention is characterized in that a pseudo electrode is provided below the stepped portion in a manner similar to the lower layer electrode wiring pattern. . In this method, as shown in Figure 1, an interlayer secret layer made of polyimide resin is formed by reflecting all the steps caused by the lower electrode wiring pattern.
This means actively taking advantage of the fact that

以下に本発明を図面に基づいて詳細に説明する。第4図
および第5図は本発明の好適な応用例を示す図である。
The present invention will be explained in detail below based on the drawings. FIGS. 4 and 5 are diagrams showing preferred application examples of the present invention.

第4図に示すようにスルーホール2を介して上層電極4
と導通する下層電極6に隣接して擬似電極8を設ける。
As shown in FIG. 4, the upper layer electrode 4 is
A pseudo electrode 8 is provided adjacent to the lower layer electrode 6 which is electrically connected to the lower layer electrode 6.

段差部分3における層間絶縁層1の盛り上がりはこの場
合も避けらtないが、同時に該擬似電硬8による段差も
あるため該段差部分3は従来のような鋭い盛υ上がシを
もたず、全体とし、て該段差部分3を平担にすることが
できる。あるいは第5図に示すように該下層電極6に隣
接する下層電極5の、該スルーホール2と平行な部分の
幅を該スルーホール2の側に広げることによっても同様
の効果をもたせることができる。
Although the protrusion of the interlayer insulating layer 1 at the stepped portion 3 is unavoidable in this case as well, since there is also a step due to the pseudo electric hardening 8, the stepped portion 3 does not have a sharp protrusion υ as in the conventional case. As a whole, the stepped portion 3 can be made flat. Alternatively, as shown in FIG. 5, the same effect can be achieved by widening the width of the portion of the lower layer electrode 5 adjacent to the lower layer electrode 6 that is parallel to the through hole 2 toward the through hole 2 side. .

以上のように本発明によって、層間絶縁層段差部分にお
ける鋭い盛シ上がシを下層に設けた擬似電極に、しる段
差を利用して緩和することができ、ポリイミド樹脂を層
間絶縁層として用いた場合に生じやすい上層電極の層間
絶縁層段差部分における断線を防止することができる。
As described above, according to the present invention, it is possible to soften the sharp embossment in the step portion of the interlayer insulating layer in a pseudo electrode in which the upper layer is provided as the lower layer by using the step, and polyimide resin can be used as the interlayer insulating layer. It is possible to prevent disconnection at the step portion of the interlayer insulating layer of the upper layer electrode, which is likely to occur when the upper layer electrode is exposed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はポリイミド樹脂を層間絶縁層とする場合の従来
の多層配線構造の例を示す図、第2図および第3図は従
来の方法による欠点を示す図、第4図および第5図は本
発明の好適な応用例金示す図である。 1゜。ポリイミド樹脂を用いft層間絶縁層2゜。スル
ーホール 3゜。層間絶R層の段差部分 4゜。上層電極 5゜。下層電極 6゜、スルーホールのある下層電極 7゜。フォトレジスト層 8゜。擬似電極 以上 出願人 株式会社第二精玉舎 代理人 弁理士最上  務
Figure 1 is a diagram showing an example of a conventional multilayer wiring structure when polyimide resin is used as an interlayer insulation layer, Figures 2 and 3 are diagrams showing drawbacks of the conventional method, and Figures 4 and 5 are FIG. 3 is a diagram showing a preferred application example of the present invention. 1°. ft interlayer insulation layer 2° using polyimide resin. Through hole 3°. The step part of the interlayer R layer is 4°. Upper layer electrode 5°. Lower layer electrode 6°, lower layer electrode 7° with through hole. Photoresist layer 8°. Pseudo electrode and above Applicant Daini Seigokusha Co., Ltd. Agent Patent attorney Tsutomu Mogami

Claims (1)

【特許請求の範囲】[Claims] 下層電極配線パターンおよびポリイミド樹脂によって形
成さtた層間絶縁層および上層電極配線パターンとから
成る多層配線構造において、該層間絶縁層の段差部分の
下層に該下層電極配線パターンに加えて擬似電極を設け
たことを特徴とする多層配線方法。
In a multilayer wiring structure consisting of a lower electrode wiring pattern, an interlayer insulating layer formed of polyimide resin, and an upper electrode wiring pattern, a pseudo electrode is provided in addition to the lower electrode wiring pattern in the lower layer of the stepped portion of the interlayer insulating layer. A multilayer wiring method characterized by the following.
JP10379383A 1983-06-10 1983-06-10 Multilayer interconnection method Granted JPS59228736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10379383A JPS59228736A (en) 1983-06-10 1983-06-10 Multilayer interconnection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10379383A JPS59228736A (en) 1983-06-10 1983-06-10 Multilayer interconnection method

Publications (2)

Publication Number Publication Date
JPS59228736A true JPS59228736A (en) 1984-12-22
JPH0337734B2 JPH0337734B2 (en) 1991-06-06

Family

ID=14363274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10379383A Granted JPS59228736A (en) 1983-06-10 1983-06-10 Multilayer interconnection method

Country Status (1)

Country Link
JP (1) JPS59228736A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61193454A (en) * 1985-02-20 1986-08-27 Mitsubishi Electric Corp Semiconductor device
JPS6412552A (en) * 1987-07-07 1989-01-17 Nec Corp Wiring structure of semiconductor device
JPH0543565U (en) * 1991-11-13 1993-06-11 三洋電機株式会社 Multi-beam semiconductor laser device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61193454A (en) * 1985-02-20 1986-08-27 Mitsubishi Electric Corp Semiconductor device
JPH0580140B2 (en) * 1985-02-20 1993-11-08 Mitsubishi Electric Corp
JPS6412552A (en) * 1987-07-07 1989-01-17 Nec Corp Wiring structure of semiconductor device
JPH0543565U (en) * 1991-11-13 1993-06-11 三洋電機株式会社 Multi-beam semiconductor laser device

Also Published As

Publication number Publication date
JPH0337734B2 (en) 1991-06-06

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