JPS5922427A - Accumulator - Google Patents

Abstract

PURPOSE:To obtain a general-purpose accumulator, by performing bit slice when the length of word to be calculated is long. CONSTITUTION:The accumulator accumulates function values and shifted sum of accumulation. An adder 6 adds the function values, the sum of accumulation and a carry signal of a low-order bit group. An adder 7 calculates the polarity of the sum of accumulation. A register 8 receives the high-order bits of the adder 6 and stores the numerical part of the shifted sum of accumulation. The adders 6, 7 constitute an adder in combination with each other. The polarity of the sum of a half is applied to the adder 6 by connecting a switch 11 to the position (b), and the polarity bits of the sum of a half of the polarity bits of the function value or a constant are summed by the adder 7 and the polarity of the partial sum is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic circuit for a digital filter, and in particular to an arithmetic circuit for a digital filter using a shift-addition method.For a calculation algorithm for a digital filter using a shift-addition method, see Japanese Patent Publication No. 53-30972 Alan.

A digital filter invented by Croisier et al.

Japanese Patent Application No. 55-040146 Three inventions of Shigeyoshi Kawarai, such as digital filters, are described in detail in the specifications and drawings.

For example, to briefly explain the shift-and-add method using Japanese Patent Application No. 55-040146, the output of a second-order cyclic digital filter is calculated as follows.

Filter input ZO11 sample time delayed, filter input Z2 delayed by 2 sample times, filter output Z3 delayed by 1 sample time. and the filter output 2+ delayed by 2 sample times are respectively expressed as binary numbers Z i −Z M2 ” −′ −2 i ′
z j2 '−' −−−−・−−−−++11
J −11 Z' , Z'Z' , Zj) is a function ψ, and 12'34 and constant ψ are cp''Aq(Zj, , zi, z4.zi,, zj)
仝Σ αi ZJ ・・・・・・・・・・−
・・・・・・・・・・・・・・・・・・ f21-0
1 M++61' ・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・131ψ −
Go, z, a″ (where αi is the filter characteristic, that is, the transfer function H (
When the output signal Y of the digital filter (hereinafter the filter output signal Y (!: omitted) is calculated as 0, that is, ψ is the fill transfer function HVJ) is applied to the digital filter. It can be seen as a snack that has been replaced with the function value. From a different perspective, the digital filter here obtains an output signal by applying a transfer function to the input signal 2. Therefore, the characteristics of the filter are low frequency, high frequency, band rejection, and band pass. Of course, it is possible to assume the concept of digital filters in a broad sense, including circuits with transfer function functions such as equalizers and delay devices.0 Reinventing equation (4) yields y=( 9M + 1 + (,,,'+...+[ψ1
+...+(ψ3+(ψ2+912-1)2-1.2
-1...]2-1...]2]2 ・
・・・・・・・・・・・・・・・・・・・・・・・・(5)
Then, the cumulative sum ψj is ψj=ψj+[ψj−J+...+(ψ3+(ψ2+9
1 ' 2- ' ) 2-1) 2 ...] 2-1
・・・・・・・・・・・・・・・・・・・・・・・・
・If (6), then ψi−ψj+ψj−12−1 ・・・・・・
・・・・・・・・・・・・・・・ [7) (However, ψ=0) M+1, and if the filter output Y is expressed as the final cumulative sum ψ, then Y=f 2 ・・・・・・・・・・・・
・・・・・・・・・・・・IRI. Here ψj is a portion of ψ (some ψ
) is the sum of products M+1 accumulated by shifting, and ψ is the accumulation up to the final value of 0. Therefore, the basic operation of a shift-addition digital filter is the calculation of the binary number expressed by the formula c.
Multiplying by /2 means shifting the data by 1 bit to the right, so Equation 1 (7) is an operation of shifting the cumulative sum ψj -1 to the right and adding the function value ψj. An accumulator that is the object of the present invention is an apparatus that performs calculations of the equation (7) and the equation IP, which indicate the following.

The structure of a second-order cyclic digital filter using a conventional accumulator is shown in FIG. 1. In FIG. 1, I is an accumulator. A digital filter using a conventional accumulator operates as follows. 01 is a delay circuit, and the Φ0 filter consists of several delay circuits. The zero filter output Y, which is applied to the storage device 2 in order from the least significant digit Z% to the most significant digit Z': The signals are applied to the storage device 2 in this order. Delay rotations 1a, lb, and Ic each have the function of delaying the applied signal by one sample time,
The filter input is delayed by 1 sample time and 2 sample times LtT: 'Zr:, 7r'', -2z7 Oyohi Z', Z:, -..., Z';;
Za (Za, bow r・”・r zl: ) is delayed by one sample time and output as 2:, 2,..., 2τ. The storage M+1 product device 2 stores the function ψ and the constant ψ. Then, the applied vector (zJzJ,..., 31 months is 0
' + 4 outputs the function ψj, outputs the 1Mth function value ψ'', and then automatically outputs this constant ψ.The accumulator performs shift addition M+1 times and outputs the filter output Y. In other words, the adder 4 calculates the function value ψj and the partial sum ψ
By receiving and adding the value ψj -1/2 obtained by multiplying 1-1 by 1/2, a partial sum ψj is output. Register 7 receives the partial sum ψ1 by shifting it to the right by 1 bit, and stores the value ψI/2, which is the cumulative sum ψJ multiplied by 1/2.
By repeating this operation M+1 times,
The filter output Y is output from the adder The integer value of the pictogram, and the filter output from formula 9 fil is @
Since it is the value obtained by multiplying the final cumulative sum ψM+1 by 2M, the final cumulative sum ψM″−1 is shifted to the left by M bits (after shifting this,
The filter output Y is the value obtained by subtracting the bits and nodes below the decimal point.
The filter output Y is from the 1st bit to the Mth bit after the decimal point of the final cumulative sum ψM+1 of F=0, that is, 2.

However, when designing a conventional digital inverter, the specifications such as the number of filter input/output bits, the number of bits of the function ψ, and the number of digits of the adder are determined according to the type of V filter and the purpose of the digital filter. Since an accumulating device was installed for each digital filter, it was inconvenient that the same accumulating device could not be applied to other digital filters. The purpose of the present invention is to eliminate the drawbacks and provide a general-purpose accumulator that can be used for all digital filters with the same basic circuit configuration. This enables operations to be performed by bit slicing when the word length is long, and the basic configuration of the arithmetic circuits for each slice section is the same.

2) The carry signal of the lower accumulator is added by the calculator in the upper accumulator.

3) When multiplying the cumulative sum ψj by 1 of a power of 2, the discarded signal can be applied to the lower accumulator, and the discarded signal applied from the upper accumulator can be
The upper digits of the adder in the F-order accumulator are
With the strained place.

4) By arranging n accumulators side by side and connecting them, the operation word length can be expanded by n times. The cluster of hints divided by bit slicing the to-be-valued number will be called a bit group.0 Figure 2 is a diagram showing the basic configuration of an A type accumulator according to the present invention.0 This is a bit group. This accumulator is exemplified when the word length of is 4 bits.
and the shifted $ product sum ψj/2 are added. nawachi 4
Figure 2 shows the basic configuration of the accumulator in the case of slicing. An adder 7 performs an addition operation, and 7 receives the function value ψ'', the most significant bit of the shifted cumulative sum ψ''/2, and the carry signal (carry) of the adder 6, and performs an addition operation to calculate the cumulative sum. An adder 8 receives the top three pins of the output of the adder 6, and stores them as the numerical part of the shifted cumulative sum ψJ/2 (here, in the example of binary operation, it is a register to the right). It is shifted by 1 bit.)
9 is a register for storing the polarity of the shifted cumulative sum ψj/2 obtained as the output of the adder 7, and 10 is a signal that is discarded when calculating the shifted cumulative sum ψJ/2. A register 11 stores the least significant bit of the adder 6, and a register 11 selects the signal fa) discarded by the upper accumulator and the polarity of the shifted cumulative sum ψj/2, and stores the least significant bit of the adder 6. 0 also, which is a switch that applies to the bit.

B is the input terminal that receives the carry signal from the accumulator that calculates the immediately lower bit group, and B is the carry signal of the adder 6 (
An output terminal that outputs the carry signal) to an accumulator that calculates the most significant bit group, and C is the shifted cumulative sum ψj/
Is it an accumulator that calculates the nearest lower bit group of the signal (lower information) that is discarded when calculating 2? D is an input terminal that receives the signal (lower bit information) to be discarded by the most recent high-order accumulator, and the output of the adder 6 is output from the accumulator as a filter output Y after the accumulation is completed. Output. In the sliced most significant bit group accumulator, D
No signal from the terminal is required and switch 11 is in position b.0 For operation on the sliced word (lowest and middle bits), switch 11 is in position a. Adder 7
and register 9 are circuit components necessary for the most significant bit group. The switching function of the switch 11 can be replaced by the wiring method.

? ! , 3 show the first embodiment of the present invention. This is an A-type accumulation device, and "0" is always applied to terminal A, and switch 11 is connected to terminal B. Due to this connection, the first embodiment 1 The circuit is the same as the accumulator shown in Figure 1. 0, that is, addition n?;r 6 and adder 7 are combined to form a 5-bit jJO calculator.
The switch 11 is connected to b (this means that the polarity of the half profit ψ1/2 is the maximum J=
(The i bit is input, and the adder 7 adds the polarity bit of the function 1 direct ψj or the constant and the polarity bit of the half-partial profit ψ!/2, and extracts the polarity of the two-part sum ψj + I by dt. In addition, since the terminal ``i 0'' is applied, the input of the lowest bit of the adder 6 is only the lowest bit of the function value ψj or constant and the least significant bit of the shifted cumulative sum ψj/2. So, in the end, the 5-bit adder in Figure 3 is the first
This is the same as adder 4 in the figure. In the first embodiment, register 1
0, terminals B, C, and D have no function.

FIG. 4 shows a second embodiment of the present invention, in which two A-type accumulators shown in FIG. 2 are used to construct a digital filter with an operation word length of 8 bits.

In Fig. 4, a spring I is applied to the terminal U-b, and the terminal A of -H-a is connected to the terminal B of n-6.
Terminal C of 7a is connected to terminal C of 7a. Also, the switch 11 of If-a is connected to b, and the switch 11 of H-su is connected to a. 0 By connecting in this way, H-a and n-b are combined as shown in Figure 1. It operates in the same way as the accumulator shown in . However, the word length is doubled, and the calculation accuracy can be increased by 1. In other words, since "0" is always applied to terminal A of n-b, the input of adder 6 of n-b is The upstream signal input is always '0'', and the adder 61 of ■-a adds the carry signal of U-b to n-b as the carry signal input of JE66.
Since the voltage is applied through the terminal lj of n-a and the terminal A of l-a, the adders 6, 7 . The adder 6 of 11-b and 11-b together operate as a 9-bit addition n5. The upper 4 bits of the O function value ψj or the constant ψ"1 are sent to the adder 6 of l-a, and the lower 4 bits are The top three bits of the lower four bits of the accumulated sum ψj/2 which are applied to the adder 6 of n-b and shifted respectively are applied to the adder 6 of n-b from the register 8 of n-b.
The lower 3 bits of human power (this is returned, the 4th bit is 11
-a's registers 10 to 11-a's terminals c, n-b's terminals are shifted to the fourth bit from the bottom of n-b's adder 6 via the switch 11 of It-b. The upper 3 bits of the remaining upper 4 bits of the accumulated 40ψj/2 are transferred from register 8 of l-a to F of adder 6 of II-a.
The polarity focus is fed back from the register 9 of II-a to the fourth bit from the bottom of the adder 6 of If-a via the switch 11 together with the adder 7 of U-a.

registers 8', 9, 10 . and n-b registers 8 operate simultaneously, r It'
a + n-b performs the calculation of equation +71. (M+
1) After accumulation times, the upper 4 bits of the filter output Y are I
From l-a, the lower 4 bits are 0 output from n=b.
The present invention can be applied and developed as follows.For example, in the above equation f5), M=2L-1.

Y=[ψ2L+ψ2 L −12−! + [ψ2L−
2+...Good [ψ2 k(-...Good (ψ4+ψ32-'+
(ψ2+ψI2-])2-212-2...]2...
・〕２ ・・・〕２ ・・・・・・・・・・・・
・・・・・・・・・fql becomes 9 partial sum ψ, 2 21(21(-1121(-2ψ, = ψ +9
2-+〔ψ +...Good (ψ4+932'+(
ψ2+912-1) 272)2...]2
・・・・・・・・・・・・
...... (If it is 11, the basic operation of the shift-addition digital filter is 2' 21 (2J (-1-12-2...)
...It is expressed as OD ψ = ψ +9 2 + ψ -12 (however, ψ2-0). If output Y is expressed as cumulative sum, ¥=ψ, 2
・・・・・・・・・・・・・・・・・・
...becomes O3.

Equation (11) indicates that the conventional two-time shift-addition is performed in one operation.0 Since one conventional shift-addition is an operation corresponding to one bit (digit) of the input/output data of the filter, Equation (10) can be said to be a method of calculating shift and addition for two digits at the same time (two-digit timeft addition method). If this method is used, the number of accumulations is L(.

= L) times is sufficient.

Therefore, the number of accumulations (
Since it is half compared to M+1 > times, the calculation time is reduced by half. In general, the basic operation of the P digit time shift JJn calculation method is M=P
-L-1 as ψ = ψ +9 2 +-0, ten ψ
Pj<-(P-112-(P-1)+ψ,-12
・・・・・・・・・・・・・・・・・・
(It becomes 1, and if the output Y is expressed using the partial sum ψζ, then Y
:ψL2 ・・・・・・・・・・・・
・・・・・・641. Therefore, the calculation time when using the p#T simultaneous shift and addition method is reduced by 1/Pζ compared to the conventional method.The basic circuit configuration of the modified bit slice accumulator is shown in Fig. 0 This is called Bri-eve. Here again, the case where the word length of the bit group is 4 bits will be exemplified.

This B-type accumulating device has a configuration that can be applied to a two-digit simultaneous addition type accumulating device. Also, the difference from the configuration in Figure 2 (A type) is that a register 2 for storing -1 is added to the function value ψ2, 21<-1, and the function value ψ is received and stored. 4 from the least significant bit of adder 6 after being temporarily stored until the addition of 4
Apply to the bit. The most significant bit of the function value ψ is applied to the lower 21 (-1 to 5th bit) of the adder 6 and the adder 7.
It is applied directly to the bits from the 5th bit to the adder 7.
The most significant bit of the function value ψ2 is applied to ◎Also.

The output from the third bit to the fifth bit of the adder 6 is temporarily stored in the register 8 as a shifted cumulative sum ψ1□/4, and the output is applied to the third bit from the least significant bit of the adder 6. The partial sum 2 output from the 0 adder 7
The polarity bit of ゛ψk is temporarily stored in register 9I.

0 applied to the 4th and 5th bits of adder 6 and adder 7I
Furthermore, the carry signals α and β of the adder 6 are applied to the adder 7, and the adders 6 and 7 are applied to the first 21 (−+
2kIA number 1 direct f/2.凋) 2 [row 1 straight ψ and soft size 1,) this cumulative bond uf ni, /4 is weighted and the cumulative sum is
Output.

Addition (2 bits of the F position of the output of ν are the signals that are noisy and unnecessary by multiplying the 11th ψ1ゝ by 1/4, and the lowest 1q bits are accumulated via j・1 and E. Output to the outside of device d.

The second bit is temporarily stored in register 10!
, are output to the outside of C via IM child C. When two or more B-type accumulators are connected and used in C, the lowest 1 digit i of the adder 6 receives the second input value ψ via the terminal G.
1 bit of 2 is applied.

Switch II is the same as the A type accumulator, and the adder 6
With the switch that selects the 4th bit of human power.

When the accumulator is connected to the top 117, it selects the signal input to terminal 1) through contact a, and when it is not connected, it selects the accumulated sum = Irk/
The 0 switch 13 in which the unity bit of 4 is selected is υLl.
) W Selects the input of the two-man power adder A that constitutes the device C. When the Main Island 92 device is connected to the upper level, the terminal F When the signal is not connected, the output of the three-man power adder A is selected via contact C.

Note that the registers 8, 9, and 10 are the cumulative sum ψ of the adders 6, 7.
After □ is calculated, it operates to store each input at the same time.

FIG. 6 shows a third embodiment of the present invention, which is a 4-bit digital filter using a B type accumulator according to the present invention. At 0 rin, which is a device.

Switch 11 is always connected, switch 13
0 is always connected to C. 0'' is always applied to the terminals A and G. By making this setting, the adders 6 and 7 are combined and operate as a 5-bit three-man power adder, so the third embodiment It operates as a 4-bit two-digit simultaneous addition type digital filter.That is, the function value ψ of the 12th one is stored in the register 12), and is applied to the fourth bit from the least significant bit of the adder 6. .

Next, the second function value ψ is applied to the 2nd to 5th bits of the adder 6, and the shifted cumulative A value ψ, /4 stored in registers 8 and 9I is added. By repeating this operation (M+1)/2 times, 4
The bit filter output Y is calculated and output from the accumulator. Figure 7 shows the fourth embodiment of the present invention. 2 An 8-bit digital filter using two B-type accumulators of the present invention. It is. In the fourth embodiment, (2) in FIG. 1 is replaced with two B-type accumulators f of the present invention.

The calculation speed and calculation accuracy are calculated by -F. FIG. 7 (Here, terminal A of I-a and terminal 13 of I-b, terminal C of l-a and terminal J of [-b), terminals E and J of II'-a:
Connect terminals F of F-b respectively, and switch 1 of I-a.
Connect 1 to BL and switch 13 to df, respectively.
Input the output γ of the storage device 2 to the terminal Gζ of N-a and
By constantly applying Iko@0'' to the terminals A and G of -b, the carry signal of adder 6 of i-b is applied to the carry input of the adder of N-a, and Since the output of the three-manpower adder used in the adder 6 of I-a is applied to the input of the two-manpower adder A used in the adder 6 of I-b, the adder of N-a 6, 7. and I
-b adders 6 are combined to form a 10-bit three-manufactured adder. Therefore, the three-manpower adder A of the adder 6 of Ib and the adder 7 are not used. Further, the lower 3 bits of the shifted cumulative sum f knee 1/4 are fed back from the I-b register 8 to the i-b adder 61, and the 4th bit is 1. -a's register 10 is fed back to ib's adder 6, and the upper three bits and the polarity bit are fed back from -a's registers 8, 9 to ib's adders 6, 7.

Furthermore, the lower 4 bits of the first function value ψ2t1 are I-b
In register 12, the upper 4 bits are register 1 of
2, and the lower 3 bits of the second function value ψ2 are I
-b adder 61.

The 4th bit is connected to the adder 6 of I-a via the terminal G of I-a.
The upper 4 bits are applied to adder 6.7 of I-a, and are applied to registers 8, 9, 10 . and i-b registers 8 operate simultaneously.

1-a and lb operate as 8-bit two-digit simultaneous addition type digital filters. Therefore C1M
+1)/2 After the completion of the accumulation, the top of the filter output Y (
The 4 bits of Xr are output from the adder 6 of [-a, and the lower 4 bits are output from the adder 6 of I-b.0 As explained above, if the accumulator of the present invention is used, Digital filters with arbitrary operation word lengths can be configured, so
Even if the specifications of the filter change, the same accumulator can be used to configure the digital filter, which is very convenient.

In addition, although the least significant bit of the output of the adder 6 is temporarily stored in the register 10 and outputted through the terminal C in FIG.
, the output of each bit of the circuit 6 becomes the input of the register 10, which is more convenient because the operation word length can be changed in units of 1 bit.

For example, if the length of n words is desired to be 3 bits, the output of the second bit from the bottom of the adder 6 may be selected as the manual input of the register 10, and the least significant bit of the function value ψj may be set to "0".

As explained above, the present invention relates to a bit slice type accumulator used in a digital filter in a broad sense.
The present invention provides a circuit that uses the same basic circuit configuration and can perform calculations on each of the highest, middle, and lowest bit sliced bits by changing a few connections or changing a switch.

Therefore, it is possible to simplify and share one circuit, and to realize a high-performance (in a broad sense) digital filter. In the 1990s, the middle part was claimed, and in Clause 3, the lowest part was claimed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional digital filter. FIG. 2 is a diagram V showing the basic configuration of an A type accumulation device according to the present invention, FIG. 3 is a configuration diagram of a first embodiment of the present invention, and FIG. 4 is a configuration diagram of a second embodiment of the present invention. , FIG. 5 is a diagram showing the basic configuration of a B-type accumulation device according to the present invention, FIG. 6 is a configuration diagram of a third embodiment of the invention, and FIG. 7 is a diagram of the configuration of a fourth embodiment of the invention. are shown respectively. 1 is a delay circuit, 2 is a storage device, 3 is a parallel-serial conversion circuit, 4
, 6.7 are adders, 5.8.9, 10, 12 are registers, 11.13 are switches, A, B, C, D. E, F, G are terminals, A is a two-man power adder, B is a three-man power adder, two ports are D1-IX2-1, /% represents ψj. Agent: Patent Attorney Ryutabe Koike (Figure 1, Figure 2) Kasumi, 5'4 jfa 'l'z yt'')'4 Ya
Yz Yt

Claims (2)

[Claims] (1) Binary code sample containing N M bits positive and negative) L' value J = ZiM, ZiM-1, ..., Zi 1 (
7) N hit information zz,...zf...,zi
Means (1) for generating M pieces of . ON-1 The N-bit information zz,...Zi,...l ”fl
-1 and the value ψ corresponding to the function value and constant value determined by the transfer function L HfZ)
It is used in a digital filter which receives a binary code input signal containing 2M bits of positive and negative signals and generates an output signal Y. An accumulator that performs a bit slice operation: receives a signal from a cough storage device, calculates a cumulative sum, and outputs a cumulative sum or filter output. a first adder (6) that also receives and accumulates the carry signal of the bit sliced nearest lower bit group and outputs a signal; a code signal from the storage device; and the first adder a second adder (7) for receiving and adding the carry signals of and calculating a sign corresponding to the cumulative sum accumulated by the first adder; the second adder outputs A fil register (9) that stores the code and outputs it to the @2 adder as information for the secondary code operation; receives the cumulative sum accumulated by the first adder and uses it as is; or a second register f81 that shifts the stored cumulative sum to the right by a predetermined bit and stores it, and in a secondary accumulation operation shifts the stored cumulative sum to the right by a predetermined bit, or inputs it as it is to the adder; and a third register information that receives and stores the lower bit information to be truncated by the adder, and then outputs the bit-sliced nearest lower bit group to the adder. (2) Binary code sample (fi Zi = Z'!', Z';-', -, Z!) containing N M bits with positive and negative values
Hiy) Information Z', "'II
A means for generating M pieces of 1 zz (-1) the N-bit information zz, . . .
1 and the value ψ corresponding to the function value and constant value determined by the transfer function 1 (HVJ)
It is used in a digital filter that receives a binary code input signal containing 2M bits of positive and negative signals and generates an output signal Y. An accumulator that performs a bit slice operation: receives the signal of the storage device, calculates a cumulative sum, and outputs a cumulative sum or filter output. It also receives and accumulates the bit-sliced carry signal of the most lower-order bit group, and outputs a carry signal for the bit-sliced most-order upper bit group. an adder (6) that receives and accumulates the lower bit information that is truncated by the cumulative sum accumulated in the bit-sliced most significant bit group; receives the cumulative sum accumulated by the adder and continues it as it is; Alternatively, the first register (8) and the adder are shifted to the right by a predetermined bit and stored, and in the secondary accumulation operation, the stored cumulative sum is shifted to the right by a predetermined bit, or inputted as is to the adder. An accumulator comprising a second register 01 which receives and stores the lower-order hit information to be truncated, and then outputs the bit-sliced immediately lower-order bit group to an adder. CtI Binary code sample value Zi=z'! containing N M bits of positive and negative values. ', ZM-', "-, Z! (J)
N Hit information Z1. ...zz..., zz
Means 11+ for generating M pieces of; -1 the N-bit information Zj, . . . Zj, . . . , Zj;
and the transfer function l N7+ HW) ,! : A digital filter that receives a binary code input signal including positive and negative signals from the 2M via 1- and generates an output signal Y. used. An accumulator that performs a bit slice operation: receives a signal from the storage device, accumulates a cumulative sum, and outputs a cumulative sum or filter output. Focus and output a carry signal to the sliced most significant bit group. an adder +61 that receives bit information and accumulates it; an adder +61 that receives the bit information and accumulates it; an accumulator comprising a register (8) that stores the accumulated sum as it is, or shifts it to the right by a predetermined bit, and in a primary accumulation operation shifts the stored cumulative sum to the right by a predetermined bit, or outputs it as it is to the adder; .