JPS6410966B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic circuit for a digital filter, and particularly to an arithmetic circuit for a shift-add digital filter.

For the calculation algorithm of the shift-addition digital filter, see Japanese Patent Publication No. 53-30972, Digital Filter Invented by Alain Croisier et al.
No.) It is described in detail in the specifications and drawings of the digital filter, etc., invented by Shigeyoshi Kawarai.

For example, Japanese Patent Application No. 55-040146 (Japanese Patent Application No. 56-040-
137725) as an example, the shift-and-add method is briefly explained.The output of the second-order cyclic digital filter is calculated as follows. Filter input Z ₀ , filter input Z ₁ delayed by one sample time,
A filter input Z ₂ delayed by two sample times, a filter output Z ₃ delayed by one sample time, and a filter output Z ₄ delayed by two sample times are respectively M
Bit binary number Z _i =Z ^M _i 2 ^M-1 + _M-1 〓 ^{j=1 Z j} _i 2 ^j-1 ...(1) (However, Z ^j _i is 0 or 1), and Z ₀ , Z ₁ , Z ₂ , Z ₃ , Z ₄ (Z ^j ₀ , Z ^j ₁ , Z ^j ₂ , Z ^j ₃ , Z ^j ₄ ) as a vector, and constant ^M+1 as ^j △ = (Z ^j ₀ , Z ^j ₁ , Z ^j ₂ , Z ^j ₃ , Z ^j ₄ ) △ = ₄ 〓 ⁱ⁼⁰ α _i Z ^j ₁ …(2) ^M+1 △ = -1/2 ₄ 〓 ^{i= 0} α _i …(3) (However, α _i is the filter characteristic, that is, the transfer function H
(a constant determined by (z)), then the digital filter output signal Y
(hereinafter abbreviated as filter output signal Y) is calculated as follows: Y= ^M+1 〓 ^j=1 _i 2 ^j-1 (4). In other words, can be seen as the amount obtained by replacing the filter transfer function H(z) with a function value suitable for the digital filter. From a different perspective, the digital filter here obtains an output signal by applying a transfer function to the input signal _Z0 . Therefore, the characteristics of the filter are low frequency,
The concept of a digital filter in a broad sense can be assumed, which includes not only high-frequency, band-elimination, and band-pass filters, but also circuits having a transfer function function, such as an equalizer and a delay device.

Rewriting equation (4), Y=[ ^M+1 + [ ^M +…+ [ ^j +…+ { ³ + ( ² + ¹ 2 ^-1 ) 2 ^-1 } 2 ^-1 …] 2 ^-1 …] 2 ^-1 ]2 ^M …(5), and the cumulative sum Ψ ^j is Ψ ^j = ^j + [ ^j-1 +… + { ³ + ( ² + ¹ 2 ^-1 )2 ^-1 }
twenty ^one
…〕2 ^-1 …(6) Then, Ψ ⁱ = ^j + Ψ ^j-1 2 ^-1 …(7) (However, Ψ ⁰ = 0), and if the filter output Y is expressed by the final cumulative sum Ψ ^M+1 , Y=Ψ ^M+1 2 ^M …(8). Here, Ψ ^j is the cumulative sum obtained by shifting a portion (of some parts) as defined by equation (6), and Ψ ^M+1 is the cumulative sum up to the final value.

Therefore, the basic operation of the shift-addition digital filter is expressed by equation (7). In binary operations, multiplying data by 1/2 means shifting the data by 1 bit to the right, so the formula
(7) indicates that the cumulative sum Ψ ^j-1 is bit-shifted to the right and the function value Ψ ^j is added. formula
A device that performs calculations of equations (7) and (8) is an accumulation device that is the object of the present invention.

FIG. 1 shows the configuration of a second-order cyclic digital filter using a conventional accumulator. In FIG. 1, is an accumulator. A digital filter using a conventional accumulator operates as follows.
1 is a delay circuit and consists of several delay circuits.

Filter input Z ₀ is from the least significant digit Z ¹ ₀ to the most significant digit Z ^M ₀
The voltage is applied to the storage device 2 in sequence up to . Filter output Y is delayed by one sample time from parallel-to-serial conversion circuit 3.
Z ¹ ₃ , Z ² _{3 .} . . , Z ^M ₃ are applied to the storage device 2 in this order.
The delay circuits 1a, 1b, and 1c each have a function of delaying the applied signal by one sample time, and delay the filter input by one sample time and two sample times to provide Z ¹ ₁ , Z ² ₁ , ..., Z ^M ₁ and Z ¹ ₂ , Z ² ₂ , ...,
Z ^M ₂ are output in this order, and Z ¹ ₃ , Z ² ₃ , . . . , Z ^M ₃ are delayed by one sample time and output as Z ¹ ₄ , Z ² ₄ , . . . , Z ^M ₄ .
The storage device 2 stores functions and constants ^M+1 , and outputs a numerical table output ^j according to the applied vectors (Z ^j ₀ , Z ^j ₁ , ..., Z ^j ₄ ), and the M-th number Table output
After outputting ^M , it automatically outputs the constant ^M+1 . The accumulator performs a shift-add operation M+1 times and outputs a filter output Y. That is, the adder 4 receives the numerical table output ^j and the value Ψ ^{j- 1} /2 obtained by multiplying the cumulative sum Ψ j-1 by 1/2, and adds them together to output the cumulative sum Ψ ^j . Register 5 receives the cumulative sum Ψ ^j shifted one bit to the right and stores it, thereby outputting the cumulative sum Ψ ^j /2. By repeating this operation M+1 times, the filter output Y is output from the adder 4. However, when the first accumulation is executed, 0 is output from the register 5 as the initial value.

By the way, the filter output Y is an M-bit integer value as shown in equation (1), and from equation (8), the filter output is the value obtained by multiplying the final cumulative sum Ψ ^M+1 by 2 ^M.
After shifting the final cumulative sum Ψ ^M+1 to the left by M bits, the value obtained by quantizing the bits below the decimal point is the filter output Y. In other words, the filter output Y is from the 1st bit to the Mth bit after the decimal point of the final cumulative sum Ψ ^M+1 .

However, when designing a conventional digital filter, first the specifications such as the number of filter input/output bits, the number of function bits, and the number of adder digits are determined according to the type of filter and the purpose of the digital filter, and then the specifications are adjusted according to these specifications. Since the accumulator was designed based on the design of the accumulator, there was a problem in that each development cost was high and the digital filter was expensive.

Therefore, the present invention eliminates this drawback, and by making the accumulating device general-purpose, it is possible to provide a low-cost digital filter by using the same accumulating device for any specification. be.

The gist of the present invention to achieve this object is to realize a desired digital filter by arranging a plurality of accumulators of the present invention in parallel according to specifications after the accumulator has a bit slice structure. It's there. In addition, the specific means for realizing the bit slice structure is to separate the adder for code calculation and the adder for data calculation, and in the top-level accumulation device, adder for code calculation and adder for data calculation are separated. Connect the adders so that both of them operate, and only the adder for data calculation operates on the other accumulator; Output the carry signal of the adder for data calculation;
The upper accumulator receives this signal as the least significant bit input of the adder; the signal that is truncated when the output of the adder for data calculation is shifted to the right by a predetermined number is stored in a register and then output, and The accumulator receives this as the most significant bit input of the adder for data calculation.

Here, the operation word length per accumulator according to the present invention will be referred to as the slice word length.

FIG. 2 shows a first embodiment of an accumulating device according to the invention. In this embodiment, the word length of the slice is 4 bits. This accumulator adds one table output ^j and the cumulative sum Ψ ^j /2. That is, it is a 4-bit slice type accumulator. In Figure 2, 6 is
Number table output ^j applied to ₁ to ₄ , cumulative sum Ψ ^j /2
and an adder for data calculation that receives the carry signal of the lower accumulator and performs an addition operation, 7 is the most significant bit of the numerical table output ^j and the cumulative sum Ψ ^j /2, and adder 6
An adder 8 calculates the sign of the cumulative sum by receiving and adding the carry signals of the sum Ψ ^j /2. A register 9 receives and stores the output of the adder 7, that is, the cumulative sum Ψ ^j /2
10 is the cumulative sum Ψ ^j /
A register 11 stores the truncation signal that is truncated when calculating 2, and selects the truncation signal a of the upper accumulator and the sign b of the cumulative sum Ψ ^j /2, and applies it to the most significant bit of the adder 6. It's a switch.
Further, A is an input terminal that receives a carry signal from the immediately lower accumulator, B is an output terminal that outputs the carry signal of the adder 6 to the immediately upper accumulator, and C is the shifted cumulative sum Ψ. An output terminal that outputs the truncated signal that is truncated when calculating ^j /2 to the nearest lower accumulator, D is an input terminal that receives the truncated signal from the nearest higher accumulator, and the output of adder 6 is the accumulator. After completion, the filter output Y is outputted from _Y1 to _Y4 .

This is a first application example of the first embodiment of the present invention shown in FIG. 3, in which one accumulation device of the first embodiment of the present invention is used as an accumulation device. FIG. 3 shows an accumulator according to the first embodiment of the present invention, with terminal A
"0" is always applied to switch 11.
is connected to b. By connecting in this way, the accumulator operates as the same circuit as the accumulator shown in FIG. That is, the adder 6 for data calculation and the adder 7 for code calculation are combined to operate as a 5-bit adder.

FIG. 4 shows a second application example of the first embodiment of the present invention, in which a digital filter with an operation word length of 8 bits is constructed using two accumulators of the first embodiment of the present invention. be. In Figure 4, -b terminal A
"0" is always applied to , terminal A of -a is connected to terminal B of -b, and terminal C of -a is connected to -
They are respectively connected to terminals D of b. Also-
Switch 11 of a is switched to b, and switch 11 of -b is switched to b.
are connected to a, respectively. By connecting in this way, -a and -b perform combined operation,
It operates as the accumulator shown in FIG. This doubles the word length, making it possible to construct a digital filter with higher precision. That is -
Since "0" is always applied to terminal A of b, the carry signal input of adder 6 of -b is always "0", and the carry signal input of adder 6 of -a is always applied to -b. Since the carry signal of adder 6 of -a is applied through terminal B of -b and terminal A of -a, adders 6, 7 of -a and -
The b adders 6 together operate as a 9-bit adder.

FIG. 5 shows a second embodiment of the invention. The accumulator of the second embodiment is applied to a two-digit simultaneous addition type digital filter. That is, the differences from the first embodiment are (1) the addition of a register 12 for storing the numerical table output ^2k-1 , and (2) the addition of the 5th bit from the bottom of the adder 6 and the adder. The point where the most significant bit of the number table output ^2k-1 is applied to 7, and (3) the second number table output
^2K is directly applied to the second to fifth bits of the adder 6, and the most significant bit of the numerical table output ^2k is applied to the adder 7. Also, the 3 of adder 6
The outputs from the 5th bit to the 5th bit are temporarily stored in the register 8 as the cumulative sum Ψ ^2k-1 /4, and the output is applied to the adder 6 from the least significant bit to the 3rd bit. The sign bit of the cumulative sum Ψ ^2k output from the adder 7 is temporarily stored in the register 9 and applied to the fourth and fifth bits of the adder 6 and the adder 7. Furthermore, the carry signal of adder 6 is sent to adder 7.
, the adders 6 and 7 add the first numerical table output ^2k-1 /2, the second numerical table output ^2k , and the cumulative sum Ψ ^2k-1 /4 to obtain the cumulative sum Ψ ^2k Output.

The lower two bits of the output of the adder 6 are signals that become unnecessary when the cumulative sum Ψ ^2k is multiplied by 1/4, and the lowest bit is outputted to the outside of the accumulator via the terminal E.
The second bit is temporarily stored in the register 10 and then outputted to the outside via the terminal C. When two or more accumulation devices of the second embodiment are used in combination, one bit of the second numerical table output ^2k is applied to the most significant bit of the adder 6 via the terminal G.

The switch 11 is a switch that selects the 4th bit input of the adder 6, as in the accumulating device of the first embodiment, and when the accumulating device is connected to the upper level, it is input to the terminal D via the contact a. Select the signal you want to
When not connected, the polarity bit of the shifted cumulative sum Ψ ^2k /4 is selected via contact b. The switch 13 selects the input of the two-input adder A constituting the adder 6, and selects the signal input to the terminal F via the contact d when an accumulator is connected to the upper level. , when not connected, selects the output of 3-input adder A via contact C.

Note that the registers 8, 9, and 10 operate to simultaneously store their respective inputs after the cumulative sum Ψ ^2k is calculated by the adders 6 and 7.

FIG. 6 shows a third application example using the second embodiment of the present invention, which is a 4-bit digital filter using the accumulator of the second embodiment of the present invention.
FIG. 6 shows an accumulating device according to a second embodiment of the present invention. , switch 11 is always connected to b, and switch 13 is always connected to c. Also, terminals A and G are always “0”
is applied. With this setting, the adders 6 and 7 are combined and operate as a 5-bit 3-input adder, so the third embodiment operates as a 4-bit 2-digit simultaneous addition type digital filter. In other words, first the first numerical table output
^2k-1 is stored in the register 12 and applied to the fourth bit from the least significant bit of the adder 6. Next, the second numerical table output ^2k is applied to the 2nd to 5th bits of the adder 6, and the shifted cumulative sum Ψ ^2k-1 /4 stored in the registers 8 and 9 is added thereto. By repeating this operation (M+1)/2 times, the 4-bit filter output Y is calculated.
Output from the accumulator.

FIG. 7 shows a fourth application example of the present invention, which is an 8-bit digital filter using two accumulators according to the second embodiment of the present invention. The fourth application example is one in which the two accumulators of the second embodiment of the present invention are used in place of the one shown in FIG. 1 to increase the calculation speed and accuracy. In Fig. 7, terminal A of -a and terminal B of -b, terminal C of -a and terminal D of -b, -
Connect terminal E of a and terminal F of -b, respectively.
- Switch 11 of a to b, switch 13 to d
and storage device 2 to terminal G of -a.
By inputting output ₄ of , and always applying "0" to terminals A and G of -b, the carry signal of adder 6 of -b is applied to the carry input of adder of -a, and - 3 used in adder 6 of a
Since the output of input adder A is applied to the input of two-input adder A used in adder 6 of -a, adders 6 and 7 of -a and adder 6 of -b become one. Configures a 10-bit 3-input adder. Therefore, the three-input adder a of adder 6 of -b and adder 7 are not used. Furthermore, the lower three bits of the cumulative sum Ψ ^2k-1 /4 are fed back from the register 8 of -b to the adder 6 of -b, and the fourth bit is fed back from the register 10 of -a to the adder 6 of -b.
The upper three bits and the polarity bit are fed back from registers 8 and 9 of -a to adders 6 and 7 of b. Furthermore, the lower 4 bits of the first numerical table output ^2k-1 are stored in the -bk register 12, and the upper 4 bits are stored in the -bk register 12.
The bit is applied to the -a register 12 and the second
Adder 6 of lower 3 bits-b of numerical table output ^2k
Then, the 4th bit is -a to the adder 6 through the terminal G, and the upper 4 bits are -a to the adder 6,
7, -a registers 8, 9, 10,
Since the registers 8 and -b operate simultaneously, -a and -b operate as an 8-bit two-digit simultaneous addition type digital filter.
Therefore, after (M+1)/2 accumulations are completed, the higher 4 bits of the filter output Y are output from the -a adder 6, and the lower 4 bits are output from the -b adder 6, respectively.

As explained above, by using the accumulating device of the present invention, a digital filter with any operation word length can be constructed, so even if the specifications of the filter change, the same accumulating device can be used to construct the digital filter. It is very convenient.

In addition, in FIG. 2, the least significant bit of the output of the adder 6 is temporarily stored in the register 10 and outputted via the terminal C, but a switch is provided to select the input of the register 10, and the output of each bit of the adder 6 is It is more convenient if the input word is input to the register 10, since the operation word length can be changed in units of 1 bit. For example, if it is desired to set the operation word length to 3 bits, the output of the second bit from the bottom of the adder 6 may be selected as the input to the register 10, and the least significant bit of the numerical table output ^j may be set to "0".

As explained above, by using the accumulating device of the present invention, there is no need to design each digital filter with different specifications, and the cost of the digital filter can be kept low.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional digital filter.
FIG. 2 is a diagram showing the basic configuration of an accumulator according to the first embodiment of the present invention, FIG. 3 is a configuration diagram of the first application example of the invention, and FIG. 4 is a diagram showing the configuration of the second application example of the invention. FIG. 5 is a diagram showing the basic configuration of an accumulating device according to a second embodiment of the present invention, and FIG.
FIG. 7 shows a configuration diagram of a fourth application example of the present invention. 1 is a delay circuit, 2 is a storage device, 3 is a parallel-to-serial conversion circuit, 4, 6, 7 are adders, 5, 8, 9, 10,
12 is a register, 11 and 13 are switches, A,
B, C, D, E, F, G are terminals, A is a 2-input adder, B is a 3-input adder, B is Ψ ^j-1 ×2 ^-1 , C is ^j
shows.

Claims (1)

[Scope of Claims] 1. Receive successively arriving M-bit binary code sample values Zi containing N positive and negative values, and sequentially, according to N-bit information constituted by each bit of the sample values, By reading the numerical table output or constant value from the storage device and accumulating the numerical table output or constant value, the filter output Y expressed by the function Y= _N-1 〓 ⁱ⁼⁰ α _i Z _i can be obtained. In the digital filter that obtains: Receives the most significant carry signal as the input for the least significant digit, receives the most significant digit signal of the cumulative sum as the input for the most significant digit, and receives the above numerical table output or constant value and cumulative sum. and a first adder 6 that combines and adds; a second adder that receives and adds the most significant digit signal of the numerical table output or constant value, the carry signal of the first adder, and the sign of the cumulative sum; an adder 7; a first register 8 for storing the signal of the output of the first adder excluding lower predetermined bits and outputting it as a cumulative sum; storing the output of the second adder; a second register 9 which outputs the sign of the cumulative sum; and a third register 9 which stores a predetermined bit removed from the output of the first adder and outputs it as a truncated signal.
and a register 10; receives the most significant truncation signal and the sign of the cumulative sum, and when it is the most significant, the sign of the cumulative sum; otherwise, the most significant truncated signal is the most significant digit of the cumulative sum; Switch 1 that outputs as a signal
1, and by connecting the carry signal and the immediately lower carry signal, and the truncation signal and the immediately higher order truncation signal,
An accumulator characterized in that an operation word length can be increased in units of the number of digits of the first adder.