JPS617716A - Digital filter - Google Patents

Abstract

PURPOSE:To use a logical element of low power consumption and to make feed forward calculation of high-speed digital signals, by performing the feed forward calculation by using bit slice pipeline operation. CONSTITUTION:Adders 21 which add input data X and feed forward data multiplied by a coefficient 2<-m> at a coefficient multiplier 23 through a unit delaying element 22 to each other are respectively installed to full adders 1-3 of (n) bit input constituting a digital filter and each adder 23 produces the added output S of inputs A and B. Moreover, the carry input of the full adder 1 is set to ''0'' and its carry output is supplied to the lower-order full adder 2 as a carry input through an FF14 which is delayed by one sampling cycle and, in the same way, the carry output of the full adder 2 is supplied to the full adder 3 through an FF15. Then, by using a bit slice pipeline operation system and a low-speed logical element of low power consumption, a cyclic digital filter is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] J This invention relates to a digital filter, and particularly to a digital filter suitable for use in signal processing of high-speed data such as digital video signals.

[Foreground technology and its problems]

As digital filters, there are acyclic (FIR) digital filters and cyclic digital filters (IIR).
) is the name tag.

In applications such as steep band-limiting filters for digital video signals, cyclic digital filters that can obtain the desired characteristics with a lower order, i.e., simpler hardware, are used compared to acyclic digital filters. It is hoped that this will come true. One possible method for configuring a recursive digital filter is to configure the denominator part of the transfer function and its numerator part separately, and to configure it using only a two-input adder.

In this case, it is necessary to perform feedpack calculations and feedforward calculations, so it must be constructed using high-speed logic elements, so power consumption is low, but
There was a problem that CM'OS, which has a slow operating speed, could not be used.

[Purpose of the invention]

Therefore, an object of the present invention is to provide a digital filter that can perform feedforward calculations even in the case of high-speed data such as digital video signals, and can realize a cyclic filter using low-power, low-speed logic elements. It is.

[Summary of the invention]

This invention divides the input data into multiple bits when adding or subtracting data, and adds the multiple bits with a delay in the higher-order bits of the divided multiple bits. An arithmetic method (referred to as bit slice pipeline arithmetic) is used in which a pipeline register is provided for each propagation path.

This invention divides an input digital signal into every n bits (n is a positive integer), and inputs a (a is a positive integer) of the input digital signal to one input of a plurality of adders, the higher the n-bit group. In addition, the carry output of the lower adder is delayed by a sampling period and supplied to the carry input of the next adder, and after the input is delayed for a predetermined time, Or, a digital filter that obtains desired filter characteristics by multiplying by a coefficient of 1/2 to a power of 2 and supplying the result to the other input of the adder, in which each of the n-bit input digital signals is divided into two systems. A digital filter characterized in that one of the two is supplied to the other input of the adder, and the other is supplied to the other input of an adder higher or lower than the adder. be.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Fig. 1, 1.2.3 indicates full adders, and these full adders 1.2.3 generate an addition output S of inputs A and B, and carry input from the previous stage and a carry input to the next stage. It has a carry output terminal. In this embodiment, as shown in FIG. 2, an adder 21 adds feedforward data that has been passed through a unit delay element 22 and multiplied by a coefficient of 2-'' by a coefficient multiplier 23, and input data X. It is configured to do this.

Full Adder 1.2.3 is configured using a bit slice pipeline calculation method in which data with a word length of 3n points are added together. Figure 3 shows full adder 1.2.3
This shows a bit-slice pipeline adder configured with one input data X with a word length of 3n bits.
and the other input data Y with a word length of 3n bits are each n
Divided into bits. In other words, one input data
from the lowest to XL X2. X3, and the other input data Y is divided into Yl, Y2 . It is divided into Y3.

This input data XL X2. X3 is delayed by the upper n bits (in this example, x2 is delayed by one sampling period from Xi, and x3 is delayed by one sampling period from X2.) One input terminal of full adder l, 2.3 and input data Yl, Y2. Y3 is similarly delayed as the upper bit group increases, and full adder 1.2.3
is supplied to the other input terminal of

The carry input of the full adder 1 is set to 0, and its carry output is made the carry input of the lower full adder 2 via the flip-flop 14 with a delay of one sampling period. The carry output of the full adder 2 is input to the lower full adder 3 via a flip-flop 15 with a delay of one sampling period.

According to the above-mentioned adder with the n-bit slice pipeline configuration, it is possible to operate at the limit of the repetitive operation of Full Adder 1.2.3, compared to when 30 bits are added together using one adder. A lower speed version can be used as a full adder 1.2.3.

In this embodiment, in order to feed forward the input data x1, 2 and x3 by multiplying them by a coefficient of 2-1', the input data is shifted to the right by m bits and sent to the other input terminal of the full adder. supply Therefore, input data x 1
, ×2, X3 to one input terminal of each of the full adders 1.2.3, and input data ×1,
are divided into lower m bits and upper (n-m)' bits, and each of these upper (n-m) bits is transmitted through registers 1i and 12.13 of delay amount for one sampling period. The lower (
n − m) Supply to the focus.

At the same time, since there is a timing difference of one sampling period between inputs x1 and χ2 of full adders 1 and 2, the lower m bits of input x2 of full adder 2 are transferred to the other input of full adder 1 without going through a register. Supplies the upper m bits of the terminal.

Similarly, for inputs x2 and X3 of full adders 2 and 3,
Since there is a timing difference of one sampling period, the lower m bits of the input x 3 of the full adder 3 are supplied to the upper m bits of the other input terminal of the full adder 2 without passing through the register. Furthermore, data of all 0s is supplied as the upper m bits of the other input terminal of the full adder 3.

According to the above configuration, the output S of each full adder 1.2.3
L, S2. S3 is the input data X1. X2. X
The input data XI is obtained by multiplying the data delayed by 3 by 2-''
, X2°×3, and feedforward addition similar to that shown in FIG. 2 can be performed. In one embodiment of the invention shown in FIG. 1, the number of bits that can be shifted to the right is up to n bits.

FIG. 4 shows another embodiment of the invention. In this example, 2' is used as a coefficient when performing feedoff, -word addition.
(j!≧0), that is, the present invention is applied to the case of l-bit shift to the left.

In FIG. 4, each of 31, 32, and 33 is an n-bit full adder, and input data XI, X2°×3 is supplied to one input terminal of the full adder 31, 32, and 33. At the same time, input data Xi, X2°x3 are supplied to registers 41b, 42b, and 43b. These registers provide a delay of one sampling period. The carry output of the full adder 31 is made to be the carry input of the full adder 32 via the flip-flop 44, and the carry output of the full adder 32 is made to be the carry input of the full adder 33 via the flip-flop 45.

In this embodiment, the output of the full adder is shifted to the left by β bits, so the upper l bits of the input data of the full adder are supplied to the lower side of the other input terminal of the lower full adder. In this case, since there is a delay amount of one sampling period for every n bits, l bits passed through the registers 41a, 42a, and 43a are supplied to the lower side of the other input terminal of the lower full adder. All 0 data is added to the lower l bits of the other input terminal of the full adder 31.

Further, the upper (n-#) bits of the other input terminal of the full adder 31, 32, and 33 include registers 41b, 42b,
The lower (n-ρ) bits of its own input data from 43b are supplied. According to another embodiment of the invention, the output SL, S2.53 of each full adder 31.32.33 is:
Input data XI, X2. 2L for delayed X3
is multiplied by , and added to the input data XI, X2° x 3. In this other embodiment, it is possible to shift any l bits not only when (l≦n) but also when (Il≧n). However, each time the n-bit full adder boundary is skipped and shifted to the left, it is necessary to delay an extra sampling period.

As described above, according to the present invention, feedforward addition can be realized by n-bi node slice pipeline addition. Although the CMO3 full adder is slow, pipeline addition in which a digital video signal with a sampling period of 73 nsec is processed by 8-bit slices or 10-bit slices is sufficiently practical.

In the above embodiment, the simplest coefficients such as 2"1 or 2I were used, but with a multi-input adder,
Coefficients that can be resolved into powers of two can be used.

Furthermore, when the feedforward coefficient is negative, a complementer may be provided at the input end of the full adder.

The transfer function of any IIR filter can be factorized into the product of a first-order transfer function and a second-order transfer function, so the second-order IIR
If IR filters can be configured, all IIR filters can be realized by cascading them.

FIG. 5 shows an example of the second order section of an IIR filter. In FIG. 5, 51.52 is an adder, 5
3.54 is a delay element, and 55.56.57.58 is a coefficient multiplier. Since the adders 51 and 52 are 3-input adders, if the configuration is changed to a 2-input adder, it will be as shown in FIG. 6.

That is, the denominator transfer function of the transfer function of the IIR filter in FIG. 5 is realized in the circuit portion 60 shown surrounded by a broken line in FIG. 6, and the numerator transfer function is realized in the circuit portion 70 shown surrounded by the broken line. Ru. Circuit portion 60 includes adders 61 .
62, delay elements 63, 64, and coefficient multipliers 65, 66, and performs feedback calculations, and the circuit section 7
0 is an adder 71.72, a delay element 73.74.75,
It is composed of coefficient multipliers 76 and 77, and performs feedforward calculations.

A transfer function is determined by setting the input data of the IIR filter shown in FIG. 6 to X and the output data to Y.

Assuming that the output of the adder 61 is W, the output of the adder 62 is 2, the output of the delay element 64 is U, and the coefficients of the coefficient multipliers 65 and 66 are bl and b2, the following equation holds true. however,
Z −1 is a unit delay operator.

V=WZ-'+b I Z-'V W=X+b 2 Z-'V ,, V/X= Z-'/ (1-b I Z-'-b
2 Z-”) Also, the coefficients of the coefficient multipliers 76 and 77 are
, a2, (V+a I Z-"V)Z-"+VZ-'a 2=Y
,・,Y/V=Z-" (1+a I Z-'+a 2
Therefore, the transfer function is Y/X-((1+a I Z-'+a 2 Z-")
/ (1-b I Z-'-b 2 Z-2) )
・It is found as z-3. This transfer function is expressed as II shown in FIG.
The term z-3 is added to the transfer function of the R filter. In other words, the fixed delay is only increased by three stages, and both can be considered as equivalent IIR filters.

As a coefficient, (al-=L a2=1/2.bl=1
/8. b2=1/16) is shown in FIG. 7 and FIG. 8, respectively. Figure 7 shows
The circuit portion 60 of FIG. 6, that is, the circuit configuration for realizing the denominator term of the above-mentioned transfer function, is shown, and FIG. 8 shows the circuit portion 70 of FIG. shows.

In FIG. 7, 81, 82, 83, 84 indicate full adders of 8 bits each, and the lower 8 bits XL of input data Full adder 82
The upper 8 bits of input data X are input to one input terminal of
is provided via register 86. Output data of full adder 81 is supplied to one input terminal of full adder 83 via register 87, and output data of full adder 82 is supplied to one input terminal of full adder 84 via register 88. The output data of the full adder 83 is passed through the register 89 to the lower 8 bits UL of the output of the circuit section 60.
The output data of the full adder 84 is taken out as the upper eight bits of the output of the circuit section 60 via the register 90.
It is extracted as H.

The full adders 81 and 82 constitute an adder 61, and the full adders 83 and 84 constitute an adder 62. Registers 87 and 88 correspond to delay element 63 , and registers 89 and 90 correspond to delay element 64 .

Since (bl=1/8), the upper 5 bits of registers 89 and 90 are fed back to the lower 5 bits of the other input terminals of full adders 83 and 84. The data of the lower three bits of the output of the full adder 84 is supplied to the upper three bits of the other input terminal of the full adder 83, the data of 0 is supplied to the upper three bits of the other input terminal of the full adder 84, and the data is shifted three bits to the right. Full adders 83 and 84 add the delayed output and the output of register 87 and the 8th day.

(b2=1/16), the upper 4 bits of registers 89 and 90 are feedhacked to the lower 4 bits of the other input terminals of full adders 81 and 82, respectively.

The data of the lower 4 bits of the output of the full adder 84 is supplied to the upper 4 bits of the other input terminal of the full adder 81,
Data of 0 is supplied to the upper four bits of the other input terminal of the full adder 82, and the outputs of the registers 85 and 86 are added to the delayed output shifted four bits to the right by the full adders 81 and 82.

The output data UL and UH of the circuit section 60 described above are input to the circuit section 70 shown in FIG. In Figure 8, 91
．． 92, 93, and 94 each indicate an 8-bit full adder. The lower 8 bits UL of data U with a word length of 16 bits are supplied to one input terminal of the full adder 91 via the register 95, and one input terminal of the full adder 92 The upper 8 bits UH of data U are supplied to the input terminal via a register 96. Output data of full adder 91 is supplied to one input terminal of full adder 93 via register 97, and output data of full adder 92 is supplied to one input terminal of full adder 94 via register 98. full adder 9
The output data of the full adder 94 is taken out as the lower 8 bits YL of the output Y of the IIR filter, and the output data of the full adder 94 is taken out as the upper 8 bits YH of the output y of the IIR filter.

Full adders 91 and 92 constitute an adder 71, and full adders 93 and 94 constitute an adder 72. Registers 95 and 96 correspond to delay element 73, and registers 97 and 9 correspond to delay element 75.

(al=1), so the data UL from the previous stage,
UH is supplied to the other input terminals of full adders 9I and 92, and the delayed outputs of registers 95 and 96 and data UL, U
Addition with H is performed by full adders 91 and 92.

Since (a2=1/2), the output of the register 97 and the output of the register 95 shifted by 1 bit to the right are added by the full adder 93.

In this case, a two-stage register 99 corresponding to the delay element 74
and 100, the upper 7 bits of the output of the register 95 are supplied to the lower 7 bits of the other input terminal of the full adder. The most significant bit of the full adder 93 contains register 9.
The least significant bit of the output of 6 is provided via flip-flop 101.

The reason why one stage of flip-flop 101 is sufficient is because there is a delay amount difference of one stage between the input data UL and UH. Similarly, the output of register 98 and the output of register 96 which has been shifted one bit to the right and passed through registers 1O2 and 103 are added by full adder 94. A 0 bit may be supplied to the most significant bit of the other input terminal of the full adder 94.

〔Effect of the invention〕

According to the present invention, by performing a feedforward operation using a bit slice pipeline operation, it is possible to construct a digital filter using a relatively slow but low power consumption element such as a CMO3.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of this invention, FIGS. 2 and 3 are block diagrams used to explain one embodiment of this invention, and FIG. 4 is a block diagram of another embodiment of this invention. 5 and 6 are block diagrams used to explain an example of an IIR filter to which the present invention can be applied, and FIGS. 7 and 8 are block diagrams showing a case where the present invention is applied to the IIR filter shown in FIG. FIG. 2 is a block diagram showing the configuration. I, 2.3.31.32.33: Full adder with n-bit input, 81.82.83.84.91.92.93.9
4: Full adder with 8-bit input.

Claims (1)

[Claims] The input digital signal is divided into n bits (n is a positive integer), and the higher the n-bit group is input to one input of a plurality of adders, the more the a (a is a positive integer) sampling period delay of the input digital signal. At the same time, the carry output of the lower adder is delayed by the a sampling period and is supplied to the carry input of the next adder, and after the input is delayed for a predetermined time, A digital filter that obtains desired filter characteristics by multiplying a coefficient of 1 to a power of 2 and supplying the resultant to the other input of the adder, wherein each of the n-bit input digital signals is It is characterized in that it is divided into two systems, one of which is supplied to the other input of the adder, and the other is supplied to the other input of an adder higher or lower than that adder. digital filter.