JPS5922365A - Polycrystalline thin-film transistor - Google Patents

Abstract

PURPOSE:To obtain the thin-film transistor of uniform characteristics by specifying the length of a region, in which carriers are made to travel, and mean crystalline grain size in a semiconductor thin-film. CONSTITUTION:The surface is coated with an SiO2 film 3 in the thickness of 5,000Angstrom through a vapor growth method, and windows for source and drain regions are bored to the film 3. N<+> layers 4 are formed in the source and drain regions through implantation in the quantity of dosage of 1X10<16>/mm.<2> of P<+> ions of 100keV energy and heat treatment for 30min at 600 deg.C in a N2 atmosphere. An oxide film 5 for a field is left and SiO2 is removed, and the surface is coated with a SiO2 film 6 for a gate oxide film in the thickness of 7,500Angstrom through the vapor growth method again. Holes for contacts with electrodes are bored through a photoetching process, Al is evaporated to the whole surface and Al is processed through the photoetching process, and the source electrode 7, the drain electrode 8 and the gate electrode 9 are formed. The thin-film MOS field-effect transistor in which a channel of 20mum length is formed to the surface layer of a polycrystalline silicon film is shaped through heat treatment for 30min at 400 deg.C in a H2 atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor made of a polycrystalline semiconductor thin film formed on an insulating substrate.

The transistor of the present invention is useful, for example, when it is integrated into a display substrate of a flat display device using a liquid crystal, an introluminescent device, or the like, and utilized as a semiconductor device used for driving.

Conventionally, a flat display device using a liquid crystal is formed as an integrated circuit that integrates a two-dimensional switching matrix of MO8') transistors and a peripheral scanning circuit on a single-crystal Si substrate. A method is adopted in which a liquid crystal sealed between a circuit element and a counter electrode is driven by the single crystal 81 integrated circuit element. In this case, since the substrate is made of a single crystal, there is a limit to the size of the substrate that can be manufactured, and therefore there is a limit to the size of the screen of the liquid crystal flat display device that can be manufactured. For example, the maximum diameter of Si wafers that can be produced at present is 5 inches;
It is not possible to create a screen large enough to draw on a 5-inch or larger brown monitor. The inability to increase the area is a major drawback as an imaging device.

In order to eliminate the disadvantages of nitride, an amorphous semiconductor film or a polycrystalline semiconductor film is formed on an amorphous substrate, and the above-mentioned integrated circuit elements are formed using these amorphous semiconductors or polycrystalline semiconductors as materials. However, a method for driving a flat display device has also been proposed.

In this case, since a semiconductor thin film formed by a method such as vacuum evaporation on an amorphous substrate is used, it is possible to create a large area with a diameter of more than 5 inches, and it is possible to make a large area of a flat optical display device. It becomes possible to

However, when an amorphous semiconductor film is used, the carrier mobility of the amorphous semiconductor thin film is extremely low, so there is a drawback that the characteristics of a transistor formed using the amorphous semiconductor thin film as a material are poor. On the other hand, when using a polycrystalline semiconductor thin film, the carrier mobility is high enough to be used as a display element, but when the crystal grain size and the current path (channel) length of the element are approximately the same, However, due to the presence of grain boundaries, there is a drawback that the characteristics of each fc crystal vary. In other words, a current path in one element may cross a grain boundary, but a current path in another element may not cross a grain boundary, and carrier conduction may be affected by the grain boundary depending on each element. I may not receive it. Therefore, transistor characteristics such as transfer conductance differ depending on each element.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and provide a thin film transistor with excellent transistor characteristics and uniform characteristics.

The present invention provides a polycrystalline thin film transistor in which a polycrystalline silicon thin film is formed on a predetermined substrate, and has at least a pair of electrode regions for causing carriers to travel through the polycrystalline semiconductor thin film, and means for controlling the carrier IJ. With this in mind, the length of the region in which the carriers are made to travel is at least 10 times the average crystal grain size in the substantial carrier travel direction, and the average crystal grain in the region in which the carriers are made to travel at least 5 times. This is a polycrystalline thin film transistor characterized by having a diameter of 150 nm or more. Seventh, the ratio of the thermal expansion coefficient of the substrate to the thermal expansion coefficient of the polycrystalline semiconductor thin film is 0.3.
It is preferable to set it in the range of ~3.0.

As described above, in the present invention, a polycrystalline semiconductor film is formed on a predetermined substrate, and when a semiconductor device is formed using this polycrystalline semiconductor film, at least the length of the region where the capacitor travels is determined by the crystal grain size. (If the crystal grain has a flat shape, the major axis) is 10 times or more. Note that in this specification, the crystal grain size means "average crystal grain size." In other words, the device characteristics depend on the number of grain boundaries encountered during carrier travel. Since there are a sufficiently large number of crystal grains in the region where carriers travel, the Q and R are affected by a large number of crystal grain boundaries, so when a large number of semiconductor devices are manufactured, the uniformity of their characteristics is good. becomes. From the viewpoint of this characteristic fluctuation, it is preferable that the length of the region in which the carriers travel is 50 times or more the crystal grain size, and the characteristic fluctuation can be suppressed well.

However, on the other hand, if each crystal grain size is too small, the characteristics of the semiconductor material (for example, carrier mobility) will deteriorate, so it is more preferable that the crystal grain size is at least 150 nm or more.

Of course, even if the crystal grain size is smaller than this, the relationship between the length of the carrier running area and the crystal grain size described above is useful in reducing variations in device characteristics and making the heel element uniform. Needless to say.

Further, it is extremely useful to form a semiconductor film having an average grain size of about 300 nm or less from the viewpoint of ease of manufacturing. That is, it can be sufficiently realized and controlled only by the steaming method in an ultra-high vacuum as described later.

In the circuit design of a semiconductor device, when the length of the carrier regular region (for example, in the case of a field effect transistor, this corresponds to the channel length) is determined, the polycrystalline grain size is adjusted. On the other hand, if the crystal grain size is limited due to constraints on the conditions for forming a polycrystalline thin film, it is necessary to design elements and circuits accordingly.

In this way, the average grain size of a polycrystalline semiconductor, i.e., a polycrystal in which most of the crystal grain sizes are 150 nm or more, is +4 +4, and the length of the region where carriers travel is substantially the average crystal grain size in the carrier travel direction. It is important to configure the semiconductor device It so that the particle size is 10 times or more larger than the grain size.

Although there is no upper limit to the length of the carrier travel area in terms of design H1, it is probably 100 μm or less in practice. Further, although it is difficult to set a lower limit of the particle size, carrier mobility can be practically ensured at 100 Å or more. Therefore, the practical upper limit of the ratio between the length of the carrier traveling area and the particle size would be about 10,000 times.

As long as a channel is formed, the thickness of the semiconductor layer may be at least 100 nm or more.

Furthermore, a thickness of 500 nm or more is more preferable.

As the substrate, amorphous or polycrystalline substrates such as glass substrates and ceramic substrates are useful.

One reason is the cost, especially glass substrates. Furthermore, a translucent substrate can be used as the substrate.

Furthermore, the ratio of the thermal expansion coefficient (Csub) of the substrate to the thermal expansion coefficient (Csemi) of the semiconductor material to be formed (Csub/Cs
It is important to set the emi) in the range of 0.3 to 3.0 in order to realize a semiconductor device with no variations. Although the details of the physical reason are unknown, it is presumed that this is due to the way strain is applied to the semiconductor layer based on the difference in thermal expansion coefficient between the substrate and the semiconductor layer.

Note that a preferred method for sterilizing a polycrystalline semiconductor film is as follows.

The vacuum evaporation apparatus capable of achieving 5 J of ultra-high vacuum may be a evaporation apparatus having a normal ultra-high vacuum apparatus.

The degree of vacuum during evaporation is set to a high vacuum of 1 x 10"l'orr. Furthermore, since 02 in the residual gas during evaporation has a negative effect on the characteristics, the oxygen partial pressure is set to 1 x 10"l'torr.
less than r.

Deposition rate is i,ooo people/hour to 10,000 people/hour
Use 人/hour.

The purpose of controlling the particle size can be achieved to some extent by controlling the thickness of the deposited film, the substrate temperature, the deposition rate, and the degree of vacuum. 1st
The figure shows that the substrate source is 60011:' and the deposition rate is 5000.
person/hour, degree of vacuum during deposition 5x1o-''l'or
FIG. 3 is a diagram showing the relationship between the film thickness of a silicon vapor layer film and the average crystal grain size under conditions of r. The film thickness was measured using a crystal oscillator.

Further, depending on the case, the particle size may be controlled by means such as laser annealing.

In order to fabricate a semiconductor device by processing a polycrystalline silicon film, it is necessary to go through several steps, but the heat treatment temperature in these steps must be kept below 820C, which is the softening point of ultra-hard glass. Accordingly, the advantages of the present invention can be fully utilized. When using a glass substrate with a low softening point, it is possible to keep the softening point even lower, for example, 550C or less. Below, as an example of a transistor, a case will be described in which an MO8 field effect transistor is formed on a glass substrate with a low softening point.

In general, a gate oxide film is obtained by thermal oxidation of a silicon substrate, but thermal oxidation requires a high temperature of 100°C or more, so it cannot be used for the present purpose. In this example, Si
React H4 and 02, or 400C or higher and 800C
By reacting 5ihit and NO2 at the following temperature, 5iQ
A z film is grown in a vapor phase, and the 3iQ2 film grown in a vapor phase is used as a gate oxide film.

Furthermore, conventionally, in order to form a source region and a drain region, a method of forming a p+ layer or an n4' layer by thermal diffusion has been generally used. However, since this method requires heat treatment at about 1150C, it cannot be used for the current purpose of forming a transistor on a glass substrate having a low softening point. In the present invention, instead of thermal diffusion, 94 layers or n
+ Use a method to form a layer. After ion implantation, heat treatment is performed to electrically activate the material, but at this time, the heat treatment temperature must be kept below the softening point of the substrate used. Therefore, for example, if we implant an ion such as BF2+ that can be highly activated by heat treatment at a low temperature of about 55 (I'), or if we implant B1 ion, etc., immediately before the reverse annealing effect occurs. A method such as heat treatment at a temperature of about 500C to 600C is adopted.In the case of p+ ions, As+ ions, etc.
Although the reverse annealing effect is not as pronounced in the case of B'' ions, it can be sufficiently activated by heat treatment at about 500°C to 600°C. Therefore, both 91 layers and n layers can be formed in a low temperature process of about 50°C to 600°C. When using a substrate having a softening point higher than 800C, such as ultra-hard glass, it is of course possible to perform heat treatment at a temperature of 800C.

By using the above manufacturing method, it is possible to make a large area or a long length, and the mobility of the carrier is 1 rust 2 /
It is possible to obtain a semiconductor material having a value of v-m or more.

Hereinafter, the present invention will be explained in detail with reference to Examples.

Example A cross-sectional view for explaining the process is shown below for an example of fabricating an n-channel MO8i field effect transistor with a structure in which a polycrystalline silicon film is formed on a glass substrate and a channel is provided in the surface layer of this polycrystalline silicon film. I will explain using

First, the substrate is mounted in a vacuum deposition apparatus capable of achieving an ultra-high vacuum. The equipment may be of general type.

Glass substrate (borosilicate glass 5.xboro-8i
licated glass H thermal expansion coefficient = 32XlO
-/C) 1, substrate temperature 600 Q, vacuum degree during evaporation 8 x 10-"forr, evaporation rate 5000 people/h
A silicon film 2 is deposited to a thickness of 1.5 μm by vacuum deposition under the conditions of o u r (Fig. 2 (a)).
. The formed silicon film 2 is made of p-type polycrystalline silicon slightly doped with boron, and the crystal grain size is approximately 200 mm.
0 person, carrier mobility is approximately 2 vice 2/V-m. The thermal expansion coefficient of this silicon film is approximately 25×10-7/C (30
0'K).

Next, the vapor phase growth method was performed at a substrate temperature of 400c.
A film 3 is deposited to a thickness of 500 OA (FIG. 2(b)).

Next, as shown in Figure 2 (C), a source,
Open windows in the air and drain areas. The distance between the source region and the drain region is 20 μm.

Therefore, the channel length is 20 μm. Next 100ke■
The P1 ion with energy is I x 1016/lyn
3 at 600c in N atmosphere.
By performing heat treatment for 0 minutes, an n+ layer 4 is formed in the source and drain regions (FIG. 2(d)). Next, as shown in FIG. 2(e), the field oxide film 5 is left and 5i
Remove Qz. A 5iQz film 6 for a siggate oxide film is deposited again to a thickness of 7500 mm by vapor phase growth (FIG. 2(f)). Furthermore, a hole for contacting the stain electrode is made by a photo-etching process as shown in FIG. 2(g), and after At is deposited on the entire surface, a photo-etching process is carried out! 7A7 is processed to form a source electrode 7, a drain electrode 8, and a gate electrode 9 (FIG. 2(h)). After this, 400 in H2 atmosphere
Heat treatment is performed for 0.30 minutes. Through the above steps, a thin film MO8 field effect transistor having a structure in which a channel with a length of 20 μm was provided in the surface layer of a polycrystalline silicon film was manufactured. This semiconductor device exhibits good and stable characteristics as a transistor.

Figure 3 shows an example of the characteristics of the prototype MO8F'ET at room temperature. This is a characteristic with respect to drain voltage Vns compared to drain current with gate voltage VG as a parameter.

In this example, for a channel length of 20 μm, the crystal grain size is approximately 2000 μm. Therefore, a sufficiently large number of crystal grains exist in the traveling direction of the carrier, the carrier is influenced by a large number of crystal grain boundaries, and the effects of this influence make the characteristics uniform when many devices are manufactured.

FIG. 4 shows the results of comparing the transconductance (trHnsconduct2nce) of semiconductor devices similar to those described above formed by forming silicon films with various average grain sizes. The values are shown as relative values, with the representative value of a particle size of 150 nm taken as 1.

It is understood that when the average grain size becomes 150 layers or less, the transconductance decreases significantly.

MO8 type field effect transistors having various gate lengths were manufactured using semiconductor layers with average grain sizes of 150 m, 200 m, and 300 m, and variations in transconductance were tested. When the ratio of the carrier travel distance to the average particle diameter is less than 1'o times, the transconductance (relative value) shows a variation of about (C) (7) with respect to 1. means that it is inoperable.

On the other hand, when the ratio is 10 to 50 times, ±0.7 to ±0
．． The variation is about 8, and if the ratio exceeds 50 times, it is ±0.
Even if the ratio was about 200 to 1000 times, the variation was about ±0 upper limit to about 0.4.

Therefore, it is understood that the ratio of carrier travel distance to average particle size should be at least 10 times or more, preferably 50 times or more.

Table 1 shows the transconductance (
The results of measuring G m ) are shown. Transistors with good characteristics cannot be obtained using quartz glass or soda lime glass. It is preferable to set the ratio of thermal expansion coefficients of the substrate and the semiconductor layer mounted thereon to a predetermined value.

Table 1

[Brief explanation of drawings]

Figure 1 is a diagram showing the relationship between the thickness of the deposited film and the crystal grain size.
Figures (a) to (h) show MOSFE using a polycrystalline semiconductor film.
FIG. 3 is a characteristic diagram of the MOSFET of the example, and FIG. 4 is a diagram showing the relationship between average grain size and transconductance. Process: Substrate, 2: Polycrystalline silicon film, 6: Insulating film, 12th layer: 0 thickness Scissor cape: 3rd figure ρ /ρ 2ρ 3/4ρ 5ρV, sρ(
l/) No. 4-Ku 262

Claims (1)

[Claims] 1. A polycrystalline silicon thin film is formed on a predetermined substrate. In a polycrystalline thin film transistor having at least a pair of electrode regions for causing carriers to travel through the polycrystalline silicon thin film and means for controlling the carriers, the length of the region for causing carriers to travel is substantially equal to 10 times or more the crystal grain size in the running direction of the carrier, and each crystal grain size in at least the region where the carriers run is necessarily 150 nm or more, and the thermal expansion coefficient of the substrate and the thermal expansion of the polycrystalline silicon thin film The coefficient ratio is 0.3~
3.0.