JPS58196049A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS58196049A JPS58196049A JP7930482A JP7930482A JPS58196049A JP S58196049 A JPS58196049 A JP S58196049A JP 7930482 A JP7930482 A JP 7930482A JP 7930482 A JP7930482 A JP 7930482A JP S58196049 A JPS58196049 A JP S58196049A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- layer
- film
- film transistor
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010408 film Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 17
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000004020 conductor Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000012298 atmosphere Substances 0.000 claims description 4
- 229910052793 cadmium Inorganic materials 0.000 claims description 3
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 239000011521 glass Substances 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 5
- 239000000203 mixture Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 239000012212 insulator Substances 0.000 description 7
- 239000005083 Zinc sulfide Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229910052984 zinc sulfide Inorganic materials 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 4
- WUPHOULIZUERAE-UHFFFAOYSA-N 3-(oxolan-2-yl)propanoic acid Chemical compound OC(=O)CCC1CCCO1 WUPHOULIZUERAE-UHFFFAOYSA-N 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 229910052980 cadmium sulfide Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- PFNQVRZLDWYSCW-UHFFFAOYSA-N (fluoren-9-ylideneamino) n-naphthalen-1-ylcarbamate Chemical compound C12=CC=CC=C2C2=CC=CC=C2C1=NOC(=O)NC1=CC=CC2=CC=CC=C12 PFNQVRZLDWYSCW-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910003446 platinum oxide Inorganic materials 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は薄膜トランジスタの製造方法に関するものであ
り、相互コンダクタンスの大きなかつドレイン電流の安
定性に優′ｎた薄膜トランジスタを均一にかつ容易に製
造できるようにすることを目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thin film transistor, and an object thereof is to uniformly and easily manufacture a thin film transistor having a large mutual conductance and excellent drain current stability. do.
薄膜トランジスタは、ソース、ドレイ／電極間の導電体
の電気伝導度を導電体と接する絶縁物層を介して設けら
れた第３の電極（ゲート電極）に印加する電圧によって
制御するいわゆる電界効果型トランジスタとして知られ
ている。従来薄膜トランジスタは、大面積にわたってス
イッチングアレー全形成し易い点、あるいは材料が安価
なため低コストになり得るなどの点でイメージセンサあ
るいはディスプレイ素子用のスイッチングアレー全目的
に研究が続けられている。A thin film transistor is a so-called field effect transistor in which the electrical conductivity of a conductor between a source and a drain/electrode is controlled by a voltage applied to a third electrode (gate electrode) provided through an insulating layer in contact with the conductor. known as. Conventionally, thin film transistors have been studied for the purpose of switching arrays for image sensors or display devices because they are easy to form in a switching array over a large area, and because materials are inexpensive, the cost can be reduced.
例えば薄膜トランジスタの主な技術分野の１つは、大面
積の平板形表示パネルである。そのような装置では薄膜
トランジスタのアレイは、基板上に配置さｎ、かつ表示
パネルの全面にわたって構成される幾つかの表示セルの
うちの特定の表示セルと関連した個々の表示媒体を制御
してそれをドライブするために用いられる。このような
目的に用いられるトランジスタの重要な動作パラメータ
は、第１にトランジスタが高い相互コンダクタンスを有
することである。すなわち、表示情報が一連の表示素子
に蓄積されかつ更新フレームが生じるまでかなり一定の
レベ！ルに保持さｎなければならない。アドレ゛ス付け
のために、トランジスタが高いオン・オフ比全必要とす
るからである。第２にトランジスタの動作特性全ドリフ
トさせる原因となる導電体層中や導電体ｊ−と絶縁体層
との界面でのキャリアのトラップ密度が低いことである
。For example, one of the main technical fields of thin film transistors is large area flat display panels. In such devices, an array of thin film transistors is arranged on a substrate and controls an individual display medium associated with a particular one of several display cells arranged over the entire surface of the display panel. used for driving. The important operating parameters of transistors used for such purposes are firstly that the transistors have high transconductance. That is, the display information is stored in a series of display elements at a fairly constant level until an update frame occurs! must be kept in place. This is because the transistor requires a high on/off ratio for addressing purposes. The second problem is that the trap density of carriers in the conductor layer or at the interface between the conductor j- and the insulator layer is low, which causes a total drift in the operating characteristics of the transistor.
第３には、これらの薄膜トランジスタの優れた特性及び
ドレイン電流の大きさがパネル全面にわたって均一であ
ることである。Thirdly, the excellent characteristics of these thin film transistors and the magnitude of the drain current are uniform over the entire panel.
従来の薄膜トランジスタの構成の一例を第１図に示す。An example of the structure of a conventional thin film transistor is shown in FIG.
ガラス等の絶縁性基板１上に数ミクロンから数千ミクロ
ンの所定の幅と長さを有するクロム、金、アルミニウム
等の金属からなるゲート電極２が設けられており、この
電極を覆って厚さ数千オングストローム呼二酸化シリコ
ン（５ｉＯｚ ）や窒化シリコン（５ｉ３Ｎａ ）や酸
化アルミニウム（五１２０３）などからなる絶縁物層３
が設けられており、上記ゲート電極２上の絶縁物層３表
面に硫化カドミウム（ＣｄＳ）やセレン化カドミウム（
ＣｊａＦ３ｅ ）等の半導体材料からなる導電体層４が
設けられ、この導電体層に接して数ミクロンから数十ミ
クロンの所定の間隔を隔ててソース電極６およびドレイ
ン電極６が設けらｎている。A gate electrode 2 made of a metal such as chromium, gold, or aluminum and having a predetermined width and length of several microns to several thousand microns is provided on an insulating substrate 1 made of glass or the like. An insulating layer 3 consisting of several thousand angstroms of silicon dioxide (5iOz), silicon nitride (5i3Na), aluminum oxide (51203), etc.
is provided, and cadmium sulfide (CdS) or cadmium selenide (
A conductive layer 4 made of a semiconductor material such as CjaF3e) is provided, and a source electrode 6 and a drain electrode 6 are provided in contact with this conductive layer at a predetermined interval of several microns to several tens of microns.
この薄膜トランジスタの動作原理は半導体としてＣｄ’
ｓ ｔ−考えると、ゲート電極２に正の電圧を加えて、
絶縁物層３に接する導電体層４表面の電子に対する電位
全低下させ、この部分にソース電極６から電子全注入し
て低抵抗のチャンネル領域を形成する。すなわち、ゲー
ト印加電圧ｖＧの変化をチャンネル領域の伝導度変化に
結びつけ、ドレイン電流ＩＤ１７）変化として出力に取
り出すものである。The operating principle of this thin film transistor is that Cd' is used as a semiconductor.
s t- Considering, applying a positive voltage to the gate electrode 2,
The potential for electrons on the surface of the conductor layer 4 in contact with the insulator layer 3 is completely lowered, and all electrons are injected from the source electrode 6 into this portion to form a low-resistance channel region. That is, a change in the gate applied voltage vG is linked to a change in the conductivity of the channel region, and this is taken out as an output as a change in the drain current ID17).
従来の薄膜トランジスタでは、通常絶縁膜層３としては
ＳｉＯ２やムβ２０５ ｋ、導電体層４としてはＣｄ８
ｅ−ｐｃｄｓなどを用いているが、これらの各層を構成
する材料は互にその結晶構造も格子定数も異なる。その
ため、絶縁膜層３と導電体層４との界面には結晶構造差
異による不連続から生ずる結晶不整が起こる。これは第
一には離党的に界面準位を形成、しチャンネル中の電子
を捕獲し、ソース電極６からチャンネル領域への電子の
注入効率を低下する。第二には絶縁膜／ＩＩＩａ上に形
成した導電体層４の結晶性を悪くしキャリアの移動度を
低下させたりバルク準位を形成したりする。これらの作
用により従来の薄膜トランジスタでは相互ＩＤ
：ｌ ンタクタ７ス９ｍ （＝、ＶＧ ）が小さく捷た
ドレイン電流より も不安定であった。In conventional thin film transistors, the insulating film layer 3 is usually made of SiO2 or β205k, and the conductive layer 4 is made of Cd8.
Although e-pcds and the like are used, the materials constituting each of these layers have different crystal structures and lattice constants. Therefore, crystal irregularity occurs at the interface between the insulating film layer 3 and the conductor layer 4 due to discontinuity due to a difference in crystal structure. This firstly forms interface states in a dissociative manner and traps electrons in the channel, reducing the efficiency of electron injection from the source electrode 6 to the channel region. Secondly, the crystallinity of the conductor layer 4 formed on the insulating film/IIIa is deteriorated, resulting in a decrease in carrier mobility and the formation of a bulk level. Due to these effects, in the conventional thin film transistor, the mutual ID:l contactor 7m (=, VG) was smaller and less stable than the drain current.
さらに、パネル全面（例えば１５ｃＩＩｌ×１６６Ｉｎ
。Furthermore, the entire panel (for example, 15cIIl x 166In
.
薄膜トランジスタのアレイとしては４５０素子×４５０
素子）にわたっての薄膜トランジスタのドレイン電流及
び相互コンダクタンスの大きさは不均一であり各々の最
大と最小とでは１桁以上の違いを生じている。このため
同一バイアス条件で薄膜トランジスタを駆動すると電流
が過大すぎて表示媒体が破壊したり、逆に電流が過小す
ぎて表示が不十分であるといった不都合が生じるという
問題があった。450 elements x 450 thin film transistor array
The drain current and mutual conductance of a thin film transistor are non-uniform over the device, and the maximum and minimum values differ by more than one order of magnitude. For this reason, if thin film transistors are driven under the same bias conditions, there is a problem that the current is too large and the display medium is destroyed, or the current is too small and the display is insufficient.
本発明は上記従来例の欠点全除去したものであり、相互
コンダクタンスの大きな安定な薄膜トランジスタ全均一
に容易に製造する方法全提供するものである。The present invention eliminates all the drawbacks of the above-mentioned conventional examples, and provides a method for easily and uniformly manufacturing a stable thin film transistor with a large mutual conductance.
本発明はセレン化カドミウムｃｄｓｅ薄膜を真空中もし
くは不活性ガスもしくは還元性ガス雰囲気中でＳＯＯ℃
以上の熱処理を施ですことにより抵抗率が１０ Ω・ｃ
ｒｒＬ捏度の高抵抗膜になり、一方前記セレン化カドミ
ウムＣｄ５ｅｌ膜をカドミウムＣｄ雰囲気中で３００℃
程度の熱処理を施すと抵抗率が１０５〜１０’Ω・儂程
度の低抵抗膜になる事実を見出したことに基づき、前記
高抵抗膜を薄膜トランジスタの絶縁物層に、前記低抵抗
膜を導電体層に用いた同−材料全各々絶縁物層と導電体
層に用いる事全特徴とする薄膜トランジスタの製造方法
に関する。In the present invention, a cadmium selenide CDSE thin film is formed at SOO℃ in vacuum or in an inert gas or reducing gas atmosphere.
By applying the above heat treatment, the resistivity is reduced to 10 Ω・c.
On the other hand, the cadmium selenide Cd5el film was heated at 300°C in a cadmium Cd atmosphere.
Based on the discovery that a low-resistance film with a resistivity of about 105 to 10' Ω can be obtained by heat treatment for a certain amount, the high-resistance film can be used as an insulator layer of a thin film transistor, and the low-resistance film can be used as a conductor. The present invention relates to a method for manufacturing a thin film transistor characterized in that the same materials are used for the insulator layer and the conductor layer, respectively.
以下、図面を用いて本発明の詳細について説明する。Hereinafter, details of the present invention will be explained using the drawings.
第２図はセレン化カドミウムｃｄｓｅ薄膜抵抗値の熱処
理による変化を示したものである。真空度が１０＝６程
度のベルジュア中で抵抗加熱法によりガラス基板上に蒸
着したセレン化カドミウムＣａ５ｅ薄膜の抵抗値は膜作
製直後では１ｏ６Ω・儂程度の抵抗値ヲ有するが真空中
もしくは否活性ガスもしくは還元性ガス、例えば水素１
０％窒素９０％のグリーンガス中で数時間熱処理を施す
ことにより、１６０℃ｌｆｉ ＩＪｊではセレン化カド
ミウムＣｄＳｅと電少するためにその抵抗率は減少する
。さらに高温になるとＣｄ５５中のカドミウムＣｄが蒸
発してＣａ５ｅ中のドナーとして作用していたＳｅ空孔
全減少させｅｄｇｅの化学量論的組成に近づく。このた
めＣ（１８６の抵抗率は高くなり５００’ｃ程度以上の
熱処理では１ｏ１２Ω・ｃＩｒＬ捏度の値となり飽和す
る。このＣｄＳｅ抵抗値の熱処理特性はＣｄＳｅの蒸着
条件や熱処理時間に工り若干異なるが、いずれの場合も
化学量論的組成になるように６ｏｏ℃程度に加熱すると
高抵抗率のＣｄＳｅ膜が得られることは共通している。FIG. 2 shows the change in resistance value of a cadmium selenide CDSE thin film due to heat treatment. The resistance value of a cadmium selenide Ca5e thin film deposited on a glass substrate by the resistance heating method in a Verdure with a degree of vacuum of about 10=6 has a resistance value of about 106 Ω・I immediately after the film is prepared, but in a vacuum or in an inert gas. or a reducing gas, such as hydrogen 1
By performing a heat treatment for several hours in a green gas containing 0% nitrogen and 90%, the resistivity decreases at 160° C.lfi IJj due to the electrical interaction with cadmium selenide CdSe. When the temperature is further increased, cadmium Cd in Cd55 evaporates, and the Se vacancies acting as donors in Ca5e are completely reduced, approaching the stoichiometric composition of the edge. For this reason, the resistivity of C(186) becomes high, and becomes saturated at a value of 1o12Ω/cIrL when heat treated at temperatures higher than about 500'C.The heat treatment characteristics of this CdSe resistance value vary slightly depending on the CdSe deposition conditions and heat treatment time. However, in all cases, it is common that a CdSe film with high resistivity can be obtained by heating to about 60° C. to achieve a stoichiometric composition.
また、ＣｄＳｅで見出さｎたこの特性はＣｄＳや硫化亜
鉛ＺｎＳ 、セレン化亜鉛ｚｎｓｅ等にも共通している
性質である。Furthermore, the characteristics found in CdSe are also common to CdS, zinc sulfide (ZnS), zinc selenide (ZnS), and the like.
次に第３図（Ｉｋｌ〜ｔｅ＋を用い本発明の薄膜トラン
ジスタの製造方法の一例を述べる。Next, an example of the method for manufacturing the thin film transistor of the present invention will be described using FIG. 3 (Ikl to te+).
無アルカリの高融点ガネスからなる基板７、例えばコー
ニング社製の＃７０５９（商品名）上に高融点の電極材
料８、例えば白金や酸化錫を所定の形状に真空蒸着法な
どにエフ付着形成する（第３図（ａ））。A high melting point electrode material 8, such as platinum or tin oxide, is deposited in a predetermined shape on a substrate 7 made of alkali-free high melting point glass, such as #7059 (trade name) manufactured by Corning Inc., using a vacuum evaporation method or the like. (Figure 3(a)).
次に、前記基板上の所定領域に周知の写真蝕刻法全用い
て例えばシリコン酸化膜５１０２又は多結晶シリコン膜
９をｃＶＤ法などに、Ｃり約１μｍの厚さに形成する。Next, for example, a silicon oxide film 5102 or a polycrystalline silicon film 9 is formed on a predetermined region on the substrate using a known photolithography method to a thickness of approximately 1 μm using a cVD method or the like.
不活性ガス雰囲気中でのモノシランガス５１ｇ４の熱分
解で作製する多結晶シリコン膜の場合には、その作製温
度を８００℃程度に高め多結晶シリコンのグレインサイ
ズ’１１０００程度度にすると多結晶シリコン膜の表面
には数１ｏＯｏ人の凹凸が生じ、後の工程で都合のよい
膜状態となる（第３図（ｂ））。In the case of a polycrystalline silicon film produced by thermal decomposition of 51 g of monosilane gas in an inert gas atmosphere, if the production temperature is raised to about 800°C and the grain size of the polycrystalline silicon is about 11,000 degrees, the polycrystalline silicon film becomes The surface has irregularities of several tens of thousands of degrees, and becomes a convenient film state in a later process (FIG. 3(b)).
この後、ガラス基板７及びゲート電極８及び多結晶シリ
コン膜９上に、１０− ’ Ｔｏｒｒ 程度の真空中で
セレン化カドミウムＣｄ５ｅｆ蒸着し約６０００人のＣ
（１８１５薄膜１０を形成する。つづいて、ガラス基板
７に接着したヒータ゛あるいは赤外線加熱器を用いて真
空中で前記ＣｄＳ ｅ薄膜１０’１５００’Ｃ〜ｓｓｏ
’ｃの温度で６０分程度加熱処理を施す。Thereafter, cadmium selenide (Cd5ef) was vapor-deposited on the glass substrate 7, gate electrode 8, and polycrystalline silicon film 9 in a vacuum of about 10-' Torr, using about 6,000 carbon atoms.
(A 1815 thin film 10 is formed. Next, the CdSe thin film 10'1500'C~sso is heated in vacuum using a heater bonded to the glass substrate 7 or an infrared heater.
Heat treatment at a temperature of 'c' for about 60 minutes.
これによりＣ（１８１５薄膜１ｏは化学量論的組成比に
近くなり、その抵抗値は１ｏ１２Ω・儂程度と非常に大
きくなる。基板温度が６０℃以下になった状態テ、次［
Ｃｄ５６薄膜１０上にカドミウム０６層１１を１００人
程入り厚さに真空蒸着で形成する（第３図（Ｃ））。As a result, the C(1815 thin film 1o has a composition ratio close to the stoichiometric ratio, and its resistance value becomes very large, about 1o12Ω・min. When the substrate temperature is below 60°C, the next
A cadmium-06 layer 11 is formed on the Cd56 thin film 10 by vacuum evaporation to a thickness of about 100 people (FIG. 3(C)).
つづいてガラス基板７を例えば弗酸ＨＦと硝酸ＨＮＯｓ
と酢酸ＣＨｓ Ｃ０ＯＨとの混合液中に浸せさし多結晶
シリコン層９をエツチング除去する。この時、多結晶シ
リコン層９の表面の凹凸が大きいと、多結晶シリコン層
９上に付着しているＣｄ８ｅｑ膜１０やＣｄｌ膜１１が
クラックや断切ｎの多い不連続膜となり多結晶シリコン
層９のエツチングが容易となる。多結晶シリコン層９の
除去と同時に、その上に付着形成されていたＣａ５ｅ薄
膜１０やＣｄ薄膜１１も同時に除去される。この後、Ｃ
ｄ層１１及びガラス基板７上にクロムやアルミニウム等
の金属を数１０００人の厚さに真空蒸着し、周知の写真
蝕刻法を用いて所定のパターンを形成し各々ソース電極
１２．ドレイン電極１３とする。さらにＣｄ薄膜１１及
びソース電極１２．ドレイン電極１３上に３０００人程
度０厚さのシリコン酸化膜ＳｉＯ２もしくはシリコン窒
化膜５ｉ３ｈ４あるいは酸化アルミニウムム１２０３等
の表面保護膜１４（ｉ７ｃＶＤ法もしくは真空蒸着法で
形成する。この保護膜は、Ｃ（１８６層１ｏへのゴミや
雰囲気ガス・湿度の付着・吸着を防ぐと同時に、後の熱
処理工程でＣ（１が蒸発するのを防ぐ作用もしている（
第３図（（１１，）。Next, the glass substrate 7 is made of, for example, hydrofluoric acid HF and nitric acid HNO.
The polycrystalline silicon layer 9 is etched away by immersing it in a mixed solution of acetic acid and CHsCOOH. At this time, if the surface unevenness of the polycrystalline silicon layer 9 is large, the Cd8eq film 10 or the Cdl film 11 attached on the polycrystalline silicon layer 9 becomes a discontinuous film with many cracks and breaks. Etching becomes easier. At the same time as polycrystalline silicon layer 9 is removed, Ca5e thin film 10 and Cd thin film 11 deposited thereon are also removed. After this, C
A metal such as chromium or aluminum is vacuum-deposited to a thickness of several thousand layers on the d-layer 11 and the glass substrate 7, and a predetermined pattern is formed using a well-known photolithography method to form source electrodes 12. A drain electrode 13 is used. Further, a Cd thin film 11 and a source electrode 12. On the drain electrode 13, a surface protective film 14 (formed by VD method or vacuum evaporation method) such as silicon oxide film SiO2, silicon nitride film 5i3h4, or aluminum oxide film 1203 with a thickness of about 3000 mm is used. At the same time as preventing the adhesion and adsorption of dust, atmospheric gas, and humidity to the 186 layer 1o, it also prevents C(1) from evaporating in the subsequent heat treatment process.
Figure 3 ((11,).
次に基板７を空気中もしくは不活性ガス中で例えば４０
０．℃に加熱し、例えば３時間放置する。Next, the substrate 7 is placed in air or an inert gas for 40 minutes, for example.
0. ℃ and left for example for 3 hours.
この熱処理によりｃａ薄膜１１のＣ（１はＣｄ’ｓ薄膜
１ｏ中に拡散してＳｅ空孔を作り約１００ｏ人の厚さの
低抵抗率のＧｅ１Ｓｅ薄膜１６を形成する。この１０６
０・ｍ程度の抵抗率を有した低抵抗Ｃ４Ｓｅ薄膜１６が
薄膜トランジスタの導電層となりＣａＥ３ｅ薄膜１０が
絶縁体層になる（第３図（６１）。Through this heat treatment, the C(1) of the Ca thin film 11 diffuses into the Cd's thin film 1o to form Se vacancies and form a low resistivity Ge1Se thin film 16 with a thickness of approximately 100o.
The low resistance C4Se thin film 16 having a resistivity of about 0.m becomes a conductive layer of the thin film transistor, and the CaE3e thin film 10 becomes an insulating layer ((61) in FIG. 3).
一般に薄膜トランジスタの飽和ドレイン電流ＩＤ。Generally, the saturation drain current ID of a thin film transistor.
相互コンダクタンスｃｉｍは導電体層および絶縁体層の
厚さに依存している。本発明による薄膜トランジスタの
製造方法では、最終工程の熱処理条件により前記各層の
厚さを調整することができる。The transconductance cim depends on the thickness of the conductor and insulator layers. In the method for manufacturing a thin film transistor according to the present invention, the thickness of each layer can be adjusted by adjusting the heat treatment conditions in the final step.
またトランジスタ特性を測定しながら、トランジスタア
レー全面、もしくは一部分を再加熱して前記各層の厚さ
の最適化とアレー全体のトランジスタ特性の均一化を図
ることが可能である。この時のトランジスタアレーの一
部分を再加熱するには、所定のトランジスタ表面に集光
した赤外線光またはレーザー等を照射することに、Ｊ：
り容易に実現できる。Further, while measuring the transistor characteristics, it is possible to reheat the entire surface or a portion of the transistor array to optimize the thickness of each layer and to make the transistor characteristics uniform throughout the array. In order to reheat a part of the transistor array at this time, it is necessary to irradiate the surface of a predetermined transistor with focused infrared light or laser.J:
This can be easily realized.
以上本発明の実施例２ＣｄＳｅｉ例にとり述べたが、Ｃ
ａＳやＺｎＳ 、 ＺｎＳ などノｎ −Ｖｌ族化合物
半導体についても同様の効果を有する。The above has been described with reference to the example of Embodiment 2 CdSei of the present invention.
Similar effects can be obtained with non-Vl group compound semiconductors such as aS, ZnS, and ZnS.
以上に述べたように本発明による薄膜トランジスタの製
造方法によれば、ゲート絶縁体層にｃｄの拡散により導
電体層全形成してゆくために、絶縁体層と導電体層との
間の格子不整は全く生じずこの部分でのキャリアの捕獲
確立を極めて少なくし相互コンダクタンスを大幅に改善
することができる。As described above, according to the method for manufacturing a thin film transistor according to the present invention, since the entire conductor layer is formed in the gate insulator layer by diffusion of CD, there is a lattice misalignment between the insulator layer and the conductor layer. This does not occur at all, making it possible to extremely reduce the probability of carrier capture in this portion and greatly improving mutual conductance.
さらに本発明による製造方法では、各トランジスタの特
性を測定しながら絶縁層や導電層の厚さを最適化できる
ために、大面積にわたって優：ｉｌた特性を有する薄膜
トランジスタを均一に作製することが非常に容易になる
。Furthermore, in the manufacturing method according to the present invention, the thickness of the insulating layer and conductive layer can be optimized while measuring the characteristics of each transistor, so it is extremely possible to uniformly manufacture thin film transistors with excellent characteristics over a large area. becomes easier.
第１図は従来の薄膜トランジスタの断面図、第２図はセ
レン化カドミウムの抵抗率の熱処理温度による変化を示
す図、−第３図（！Ｌ）〜（６１は本発明の薄膜トラン
ジスタの製造方法の１例を示す断面図である。
１．７・・・・・・基板、２．８・・・・・・ゲート電
極、６゜１２・・・・・・ソース電極、６．１３・・・
・・・ドレイ／電極、１０．１５・・・・・・Ｃｄ５６
薄膜、１１・・・・・・Ｏ（ｉ薄膜、１４・・・・・・
表面保護膜、１６・・・・・・低抵抗率半導体層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
１ ２FIG. 1 is a cross-sectional view of a conventional thin film transistor, FIG. 2 is a diagram showing changes in resistivity of cadmium selenide depending on heat treatment temperature, and FIG. It is a sectional view showing one example. 1.7...substrate, 2.8... gate electrode, 6°12... source electrode, 6.13...
...Dray/electrode, 10.15...Cd56
Thin film, 11...O (i thin film, 14...
Surface protective film, 16...Low resistivity semiconductor layer. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure 1 2
Claims (1)
形状の半導体層を形成する工程、前記半導体層の組成比
を概略化学量論的組成比にするための第１の熱処理工程
、前記半導体層上に金属薄膜層を形成する工程、前記金
属薄層上にソース電極及びドレイン電極となる第２の導
電体層を形成する工程、前記金属薄層を構成する物質を
前記第１の半導体層中に所定の深さだけ拡散するための
第２の熱処理工程を含むことを特徴とする薄膜トランジ
スタの製造方法。 （２）第１の熱処理工程を非酸化性ガス雰囲気中で５０
０″Ｇ以上の温度で行うことを特徴とする特許請求の範
囲第１項記載の薄膜トランジスタの製造方法、。 （３）第２の導電体層を形成する工程の後、少なくとも
金属薄膜層上に絶縁膜を形成する工程を含むことを特徴
とする特許請求の範囲第１項記載の薄膜トランジスタの
製造方法。 （４）半導体層にセレン化カドミウム、金属薄層にカド
ミウムをそれぞれ用いることを特徴とする特許請求の範
囲第１項記載の薄膜トランジスタの製造方法。 （５）金属薄層の厚さを１００人程程度すること全特徴
とする特許請求の範囲第１項記載の薄膜１ランジスタの
製造方法。[Scope of claims] a first heat treatment step, a step of forming a metal thin film layer on the semiconductor layer, a step of forming a second conductor layer serving as a source electrode and a drain electrode on the metal thin layer, and forming the metal thin layer. A method for manufacturing a thin film transistor, comprising a second heat treatment step for diffusing a substance to a predetermined depth into the first semiconductor layer. (2) The first heat treatment step is performed in a non-oxidizing gas atmosphere. 50 inside
A method for manufacturing a thin film transistor according to claim 1, characterized in that the manufacturing method is carried out at a temperature of 0″G or higher. (3) After the step of forming the second conductor layer, at least the metal thin film layer is A method for manufacturing a thin film transistor according to claim 1, characterized by including the step of forming an insulating film. (4) Cadmium selenide is used for the semiconductor layer, and cadmium is used for the thin metal layer. A method for manufacturing a thin film transistor according to claim 1. (5) A method for manufacturing a thin film transistor according to claim 1, characterized in that the thickness of the metal thin layer is about 100 layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7930482A JPS58196049A (en) | 1982-05-11 | 1982-05-11 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7930482A JPS58196049A (en) | 1982-05-11 | 1982-05-11 | Manufacture of thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58196049A true JPS58196049A (en) | 1983-11-15 |
| JPH0359585B2 JPH0359585B2 (en) | 1991-09-11 |
Family
ID=13686098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7930482A Granted JPS58196049A (en) | 1982-05-11 | 1982-05-11 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58196049A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62140465A (en) * | 1985-12-16 | 1987-06-24 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor |
-
1982
- 1982-05-11 JP JP7930482A patent/JPS58196049A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62140465A (en) * | 1985-12-16 | 1987-06-24 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0359585B2 (en) | 1991-09-11 |
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