JPH0325951B2 - - Google Patents
Info
- Publication number
- JPH0325951B2 JPH0325951B2 JP10088081A JP10088081A JPH0325951B2 JP H0325951 B2 JPH0325951 B2 JP H0325951B2 JP 10088081 A JP10088081 A JP 10088081A JP 10088081 A JP10088081 A JP 10088081A JP H0325951 B2 JPH0325951 B2 JP H0325951B2
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- layer
- temperature
- resistance value
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 31
- 239000010408 film Substances 0.000 description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 238000010438 heat treatment Methods 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 239000012535 impurity Substances 0.000 description 8
- 238000000137 annealing Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
【発明の詳細な説明】
本発明は、電界効果型トランジスタ、特に低温
プロセスで製造可能にした非晶質半導体による
MOSトランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field-effect transistor, particularly a field-effect transistor based on an amorphous semiconductor that can be manufactured using a low-temperature process.
Regarding MOS transistors.
従来のMOSトランジスタは、基板として単結
晶シリコン層又は多結晶シリコン層を用いる等高
温プロセスで製造されるために、熱的に弱い例え
ばガラス上あるいは有機物フイルタ上に製造する
ことは困難であつた。一方、低温プロセスで非晶
質シリコンによるMOSトランジスタを作る場合
に問題となるのは、ソース領域及びドレイン領域
の抵抗を下げるときである。普通は不純物を
CVD（化学気相成長）時にドーピングし、あるい
はイオン注入によつてドーピングし、熱処理して
活性化し抵抗を下げるが、熱をかけると非晶質シ
リコン全体が微小な多結晶に変化し、ゲート部
（活性層）を非晶質シリコンで構成することがで
きない。 Conventional MOS transistors are manufactured by high-temperature processes using single-crystal silicon layers or polycrystalline silicon layers as substrates, so it is difficult to manufacture them on thermally weak surfaces, such as glass or organic filters. On the other hand, when manufacturing a MOS transistor using amorphous silicon using a low-temperature process, a problem arises when lowering the resistance of the source and drain regions. Usually impurities
Doping is done during CVD (chemical vapor deposition) or by ion implantation, and heat treatment is used to activate and lower the resistance. However, when heat is applied, the entire amorphous silicon changes to minute polycrystals, and the gate area (active layer) cannot be made of amorphous silicon.
本発明は、上述の点に鑑み、特にパルスレーザ
を用いてソース及びドレイン領域のみを選択的に
アニールし、活性層の非晶質半導体を変質させる
ことなく低温プロセスで製造できるようにした
MOSトランジスタを提供するものである。 In view of the above-mentioned points, the present invention selectively anneals only the source and drain regions using a pulsed laser, thereby making it possible to manufacture the amorphous semiconductor in the active layer in a low-temperature process without altering its properties.
It provides MOS transistors.
以下、図面を用いて本発明を説明する。 The present invention will be explained below using the drawings.
本発明においては、第１図に示すように少くと
も表面が絶縁物である基板、例えばガラス基板１
上に300℃以下で形成可能なプラズマCVDを用い
SiH4の分解によつて非晶質シリコン層２を形成
する。この非晶質シリコン層２上に例えば380℃
の熱分解炉を利用してSiO2によるゲート絶縁膜
３を形成し、又他部に同様にしてSiO2による厚
い絶縁層４を形成し、そのソース及びドレイン領
域に対応する部分に窓孔５，６を形成する。又ゲ
ート絶縁膜３上に例えば金属によるゲート電極７
を形成する。そして、窓孔５，６を通じて夫々イ
オン注入法にて所要の不純物を打ち込み、非晶質
シリコン層２及びゲート電極７上にプラズマ
CVDによつて300℃以下でキヤツピング用のSiO2
層を形成する。しかる後パルスレーザ（例えば波
長1.06μm）を用いてイオン注入領域を選択的に
アニールし、ソース領域８及びドレイン領域９を
形成する。なお、キヤツピング層にＰ，As，Ｂ
などの不純物を含むSiO2層を用いる場合には、
Si+をイオン注入してそこから非晶質シリコン層
２中に不純物を導入することができる。この選択
アニールでソース及びドレイン領域８及び９のみ
微小な多結晶領域となり、チヤンネル部１３は非
晶質領域として残る。300〜500℃の温度で約30分
間熱処理を行い、非晶質領域と多結晶領域の間に
存在する障壁の影響を取除く。その後、両領域８
及び９にソース電極１０及びドレイン電極１１を
形成し、目的のMOSトランジスタ１４を得る。 In the present invention, as shown in FIG.
Using plasma CVD, which can be formed at temperatures below 300℃,
An amorphous silicon layer 2 is formed by decomposing SiH 4 . For example, 380°C is applied on this amorphous silicon layer 2.
A gate insulating film 3 made of SiO 2 is formed using a pyrolysis furnace of , 6. Further, a gate electrode 7 made of metal, for example, is formed on the gate insulating film 3.
form. Then, necessary impurities are implanted through the window holes 5 and 6 by ion implantation, and plasma is applied onto the amorphous silicon layer 2 and the gate electrode 7.
SiO 2 for capping below 300℃ by CVD
form a layer. Thereafter, the ion implantation region is selectively annealed using a pulsed laser (for example, wavelength 1.06 μm) to form a source region 8 and a drain region 9. In addition, P, As, and B are used in the capping layer.
When using a SiO 2 layer containing impurities such as
Impurities can be introduced into the amorphous silicon layer 2 by ion implantation of Si + . By this selective annealing, only the source and drain regions 8 and 9 become minute polycrystalline regions, and the channel portion 13 remains as an amorphous region. Heat treatment is performed at a temperature of 300 to 500°C for about 30 minutes to remove the effect of the barrier that exists between the amorphous region and the polycrystalline region. After that, both areas 8
A source electrode 10 and a drain electrode 11 are formed on and 9 to obtain a target MOS transistor 14.
このようにパルスレーザを用いた場合には、イ
オン注入領域とそれ以外の領域でのレーザ光の吸
収係数の違いにより、即ちイオン注入領域ではレ
ーザ光の吸収が大きく、イオン注入されない領域
ではレーザ光の吸収が小さいことにより、イオン
注入領域に対して選択アニールが可能となる。例
えばリン（P+）を１×1015cm-2打ち込んだとき、
そのイオン注入領域は0.3J／cm2でアニールされ、
他のイオン注入されない領域は1.0J／cm2でも変化
しない。又、ゲート絶縁膜３上のみに金属層をお
くことにより、この金属層でレーザ光は反射し選
択アニールができる。さらに、レーザパルスの時
間が短かいので、熱伝導はほとんど無視でき、下
地に熱は伝わらない等の利点がある。第２図及び
第３図は、第１図のMOSトランジスタ１４の静
特性図である。第３図の曲線（）はゲート及び
ドレインをシヨートした場合、曲線（）はゲー
ト開放の場合を示す。 When a pulsed laser is used in this way, due to the difference in the absorption coefficient of the laser beam between the ion-implanted region and other regions, the absorption of the laser beam is large in the ion-implanted region, and the laser light is absorbed in the non-ion-implanted region. The small absorption of ions allows selective annealing of the ion-implanted region. For example, when phosphorus (P + ) is implanted at 1×10 15 cm -2 ,
The ion implanted region is annealed at 0.3J/ cm2 ,
Other regions where ions are not implanted do not change even at 1.0 J/cm 2 . Furthermore, by placing a metal layer only on the gate insulating film 3, the laser beam is reflected by this metal layer, allowing selective annealing. Furthermore, since the laser pulse time is short, heat conduction can be almost ignored, and there are advantages such as no heat being transferred to the substrate. 2 and 3 are static characteristic diagrams of the MOS transistor 14 of FIG. 1. The curve () in FIG. 3 shows the case when the gate and drain are closed, and the curve () shows the case when the gate is open.
実験によれば、ソース領域８及びドレイン領域
９の抵抗値は500Ω／□、チヤンネル部１３の抵
抗値は108Ω／□以上という結果が得られ、選択
的アールが達成される。これによつて得られた
MOSトランジスタの特性を下記に示す。 According to experiments, results were obtained in which the resistance value of the source region 8 and drain region 9 was 500 Ω/□, and the resistance value of the channel portion 13 was 10 8 Ω/□ or more, and selective radius was achieved. obtained by this
The characteristics of the MOS transistor are shown below.
ゲート長：7μm
ゲート巾：150μm
閾値電圧Vth：7V
相互コンダクタンスgm：1.2μ
ソース・ドレイン間電圧VDS：45V（於てID＝1nA）
上述の構成によれば、チヤンネル部１３が非晶
質シリコンで形成され、ソース及びドレイン領域
８及び９のみがパルスレーザによる選択アールで
低抵抗化されることにより、特性のよいMOSト
ランジスタが得られる。しかも、このMOSトラ
ンジスタは低温の製造プロセスで容易に製造で
き、従つて従来困難であつたガラス上あるいは有
機物フイルム上にも形成できる利点がある。な
お、上例ではゲート絶縁膜（SiO2）として380℃
の熱分解炉を利用したが、このゲート絶縁膜もプ
ラズマCVDを使うことによつて全工程を200℃以
下のプロセスでMOSトランジスタを作ることが
可能である。上記技術はMOSトランジスタに限
ぎらず、非晶質シリコンと金属とのコンタクトを
得る場合にも応用できる。なお、チヤンネル部１
３の下に第２のゲート電極を埋込んでチヤンネル
電流を倍化させることができる。この場合、基板
１の表面にAl等の金属層を選択的に形成し、こ
の上をSiO2等の絶縁層で全面おおつてから非晶
質シリコン層２を形成する。 Gate length: 7μm Gate width: 150μm Threshold voltage Vth: 7V Mutual conductance gm: 1.2μ Source-drain voltage V DS : 45V (at I D = 1nA) According to the above configuration, the channel portion 13 is amorphous. The MOS transistor is made of silicon, and only the source and drain regions 8 and 9 are made low in resistance by selective radius using a pulse laser, thereby obtaining a MOS transistor with good characteristics. Moreover, this MOS transistor has the advantage that it can be easily manufactured using a low-temperature manufacturing process, and can therefore be formed on glass or organic film, which has been difficult in the past. In the above example, the gate insulating film (SiO 2 ) was heated at 380°C.
A thermal decomposition furnace was used, but by using plasma CVD for this gate insulating film, it is possible to create a MOS transistor with the entire process temperature below 200°C. The above technique can be applied not only to MOS transistors but also to obtaining contact between amorphous silicon and metal. In addition, channel part 1
A second gate electrode can be buried under 3 to double the channel current. In this case, a metal layer such as Al is selectively formed on the surface of the substrate 1, and the amorphous silicon layer 2 is formed after covering the entire surface with an insulating layer such as SiO 2 .
非晶質シリコン層２のチヤンネルの形成されな
い部分を比較的高比抵抗にする、例えば酸素（30
原子％以下）を含む非晶質シリコン層の上に酸素
を含まない非晶質シリコン層を数百Åの厚さ形成
してオフ抵抗を高くすることができる。又、チヤ
ンネルの形成される部分を多結晶シリコン層にす
ることもでき、ゲートを下側に設けた場合その上
に順次ゲート絶縁層、多結晶シリコン層、非晶質
シリコン層を形成し、非晶質シリコン層の側から
イオン注入とレーザ照射を行う。 For example, oxygen (30
The off-resistance can be increased by forming an amorphous silicon layer that does not contain oxygen to a thickness of several hundred angstroms on top of an amorphous silicon layer that contains oxygen (at most atomic %). Alternatively, the portion where the channel is formed can be made of a polycrystalline silicon layer, and if the gate is provided on the lower side, a gate insulating layer, a polycrystalline silicon layer, and an amorphous silicon layer are sequentially formed on top of the gate. Ion implantation and laser irradiation are performed from the crystalline silicon layer side.
一方、上述の非晶質シリコンによるMOSトラ
ンジスタは表面が絶縁物である基板上に形成する
が、このMOSトランジスタの負荷として用いる
抵抗体も非晶質シリコンを用いて形成することが
できる。例えばMOSスタテイツクRAMのメモリ
ーセルはフリツプフロツプ回路が用いられ、従来
はＥ／Ｅ（エンハンスメント−エンハンスメント）
MOS回路及びＥ／Ｄ（エンハンスメント−デイプ
レツシヨン）MOS回路が使われていたが、最近
では高密度、低消費電力を可能にするために高抵
抗の多結晶シリコンを負荷素子にした抵抗負荷形
MOS回路が採用されつつある。しかし、多結晶
シリコンで高抵抗体を作る場合、多結晶シリコン
膜中のトラツプの数によつて抵抗値が非常にバラ
ツクことが判明している。従つて多結晶シリコン
による抵抗体は多結晶シリコンの生成条件によつ
て影響を受けるばかりでなく、製造プロセスの途
中に入る水素アニールによつてトラツプの数が変
化し抵抗値が大きく変化する。特に高温アニール
後の低温熱処理によつて抵抗値の変動が激しい。 On the other hand, although the above-mentioned MOS transistor made of amorphous silicon is formed on a substrate whose surface is an insulator, the resistor used as a load of this MOS transistor can also be formed using amorphous silicon. For example, the memory cells of MOS static RAM use flip-flop circuits, and conventionally, E/E (enhancement-enhancement)
MOS circuits and E/D (enhancement-depression) MOS circuits were used, but recently, resistive load types have been used that use high-resistance polycrystalline silicon as load elements to enable high density and low power consumption.
MOS circuits are being adopted. However, when making a high resistance element using polycrystalline silicon, it has been found that the resistance value varies greatly depending on the number of traps in the polycrystalline silicon film. Therefore, a resistor made of polycrystalline silicon is not only affected by the conditions for producing polycrystalline silicon, but also the number of traps changes due to hydrogen annealing performed during the manufacturing process, resulting in a large change in resistance value. In particular, the resistance value fluctuates significantly due to low-temperature heat treatment after high-temperature annealing.
これに対して、不純物がイオン注入された非晶
質シリコン薄膜にて抵抗体を構成するときは、上
記の熱処理による抵抗値変動が少ない。非晶質シ
リコンは、膜中のトラツプの数が非常に多いため
に、炉での水素アニールではほとんどトラツプ数
が影響を受けない。従つて抵抗値は活性化したキ
ヤリアの数と移動度によつてほとんど決まり、一
度高温でアールすれば、低温での処理の影響を受
けず、変動が少ない。ただし、トラツプの数が多
いので低抵抗値は得にくい。非晶質シリコンのト
ラツプの数を減らすには非晶質シリコン膜の形成
（デイポジツシヨン）時に水素又はフツ素を数10
％のオーダでドープすればよい。 On the other hand, when the resistor is made of an amorphous silicon thin film into which impurity ions are implanted, the resistance value changes less due to the heat treatment described above. Since amorphous silicon has a very large number of traps in its film, the number of traps is hardly affected by hydrogen annealing in a furnace. Therefore, the resistance value is mostly determined by the number and mobility of activated carriers, and once it is heated at a high temperature, it is not affected by low temperature processing and changes little. However, it is difficult to obtain a low resistance value because of the large number of traps. To reduce the number of traps in amorphous silicon, several dozen hydrogen or fluorine atoms are added during the formation (deposition) of the amorphous silicon film.
It is sufficient to dope on the order of %.
実験例として、夫々第４図及び第５図に示すよ
うに例えばシリコン基板２１のSiO2層２２上に
非晶質シリコン膜２３及び多結晶シリコン膜２４
を被着形成し、各膜２３及び２４にヒ素（As+）
をイオン注入して非晶質シリコンによる抵抗体２
５及び多結晶シリコンによる抵抗体２６を構成
し、以後の熱処理による抵抗値の変化を測定し
た。その結果を第６図に示す。但し、各膜２３及
び２４の膜厚は1000Å程度、イオン打ち込みエネ
ルギーは80KeVである。又熱処理は、酸素雰囲
気中で950℃、30分の熱処理（ゲート酸化膜の形
成等）、窒素雰囲気中で1000℃、20分の熱処理
（イオン注入の活性化、多層配線で絶縁層表面を
なだらかにするための絶縁層の再溶融等）、及び
フオーミングガス（N2とH2の混合ガス）雰囲気
中で400℃、60分の熱処理（Al電極のシンター、
白金シリサイド化の熱処理等）とした。第３図
中、曲線a1及びa2は夫々ドーズ量が１×1014cm-2
及び６×1014cm-2の非晶質シリコンによる抵抗体
２５の場合、曲線ｂ（総称）はドーズ量が１×
1014cm-2の多結晶シリコンによる抵抗体２６の場
合である。但し、多結晶シリコン膜にドーズ量６
×1014cm-2打ち込んだ場合の抵抗値は１〜2KΩ／
□と非常に小さい。この第６図から明らかなよう
に、多結晶シリコンによる抵抗体即ち曲線ｂの場
合には高温アール後の低温熱処理によつて抵抗値
が激しく変動する。一方、非晶質シリコンによる
抵抗体即ち曲線a1，a2の場合には高温アール後の
低温熱処理での抵抗値の変化が極めて少ない。従
つて、この非晶質シリコンの抵抗体２５において
は高温アニール後の抵抗値を制御すればよいこと
がわかる。尚、非晶質シリコンの抵抗体の場合、
もう少し抵抗値を下げたいときには不純物のドー
ズ量を増す他に、非晶質シリコン膜の被着形成
（デイポジツト）時に所定量の不純物をドープす
るとか、ヒ素ガラス（AsSG）から拡散する等の
方法もある。あるいはイオン注入法とそれらの方
法を組み合せる方法もある。又、非晶質シリコン
膜の形成は通常の例えば低温プラズマCVD（化学
気相成長）法等により行うを可とする。なお、非
晶質シリコン層２にMOSトランジスタのソース、
ドレイン形成用の不純物イオン注入と同時に抵抗
や配線用の注入を選択的に行うことができる。 As an experimental example, for example, an amorphous silicon film 23 and a polycrystalline silicon film 24 were formed on a SiO 2 layer 22 of a silicon substrate 21, as shown in FIGS. 4 and 5, respectively.
Arsenic (As + ) is deposited on each film 23 and 24.
Resistor 2 made of amorphous silicon by ion implantation
5 and polycrystalline silicon, and the change in resistance value due to subsequent heat treatment was measured. The results are shown in FIG. However, the thickness of each film 23 and 24 is about 1000 Å, and the ion implantation energy is 80 KeV. Heat treatment includes heat treatment at 950℃ in an oxygen atmosphere for 30 minutes (forming gate oxide film, etc.), heat treatment at 1000℃ in a nitrogen atmosphere for 20 minutes (activating ion implantation, smoothing the surface of the insulating layer with multilayer wiring, etc.) remelting of the insulating layer, etc.) and heat treatment at 400℃ for 60 minutes in a forming gas (mixed gas of N 2 and H 2 ) atmosphere (sintering of the Al electrode,
heat treatment for platinum silicidation, etc.). In Figure 3, curves a1 and a2 each have a dose of 1×10 14 cm -2
In the case of a resistor 25 made of amorphous silicon of 6×10 14 cm -2 , the curve b (general term) shows that the dose is 1×
This is the case of a resistor 26 made of polycrystalline silicon of 10 14 cm -2 . However, if the polycrystalline silicon film has a dose of 6.
×10 14 cm -2The resistance value when implanted is 1~2KΩ/
□ is very small. As is clear from FIG. 6, in the case of a resistor made of polycrystalline silicon, that is, curve b, the resistance value fluctuates drastically due to low-temperature heat treatment after high-temperature arcing. On the other hand, in the case of resistors made of amorphous silicon, that is, curves a 1 and a 2 , the change in resistance value during low temperature heat treatment after high temperature radiusing is extremely small. Therefore, it can be seen that the resistance value of the amorphous silicon resistor 25 after high-temperature annealing can be controlled. In addition, in the case of an amorphous silicon resistor,
If you want to lower the resistance a little more, in addition to increasing the dose of impurities, you can also do other methods such as doping a predetermined amount of impurities when depositing the amorphous silicon film, or diffusing it from arsenic glass (AsSG). be. Alternatively, there is also a method of combining ion implantation and these methods. Further, the amorphous silicon film can be formed by a conventional method such as low-temperature plasma CVD (chemical vapor deposition). Note that the amorphous silicon layer 2 has a source of a MOS transistor,
Implantation for resistors and wiring can be selectively performed at the same time as impurity ion implantation for drain formation.
上述せる如く、本発明は非晶質シリコンを用い
て低温プロセスのMOSトランジスタが容易に得
られるものであり、非晶質シリコンの抵抗体との
組合せ等、各種用途に適用できる実益がある。 As described above, the present invention allows a low-temperature process MOS transistor to be easily obtained using amorphous silicon, and has the practical benefit of being applicable to various uses such as combination with a resistor of amorphous silicon.
第１図は本発明の電界効果型トランジスタの例
を示す断面図、第２図及び第３図は夫々その静特
性図、第４図及び第５図は夫々非晶質シリコン及
び多結晶シリコンの抵抗体の例を示す断面図、第
６図はその低抗体の熱処理による抵抗値変動の状
態を示す測定図である。
１は基板、２は非晶質シリコン、３はゲート絶
縁膜、８及び９はソース及びドレイン領域であ
る。
FIG. 1 is a sectional view showing an example of a field effect transistor of the present invention, FIGS. 2 and 3 are static characteristic diagrams, and FIGS. 4 and 5 are graphs of amorphous silicon and polycrystalline silicon, respectively. FIG. 6 is a cross-sectional view showing an example of a resistor, and a measurement diagram showing the state of resistance value fluctuation due to heat treatment of the low antibody. 1 is a substrate, 2 is amorphous silicon, 3 is a gate insulating film, and 8 and 9 are source and drain regions.
Claims (1)
上にある半導体層と、該半導体層中にありソース
及びドレインとなる多結晶領域と、該半導体層中
にありソースとドレインの間にある非晶質領域
と、上記ソースとドレインの間の半導体層上に絶
縁的に形成されたゲートとを有して成る電界効果
型トランジスタ。1. A substrate whose surface is at least an insulator, a semiconductor layer on the substrate, a polycrystalline region in the semiconductor layer that serves as a source and a drain, and a polycrystalline region in the semiconductor layer between the source and drain. A field effect transistor comprising an amorphous region and a gate insulatively formed on a semiconductor layer between the source and drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10088081A JPS582073A (en) | 1981-06-29 | 1981-06-29 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10088081A JPS582073A (en) | 1981-06-29 | 1981-06-29 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS582073A JPS582073A (en) | 1983-01-07 |
| JPH0325951B2 true JPH0325951B2 (en) | 1991-04-09 |
Family
ID=14285635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10088081A Granted JPS582073A (en) | 1981-06-29 | 1981-06-29 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS582073A (en) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58127382A (en) * | 1982-01-26 | 1983-07-29 | Seiko Epson Corp | Semiconductor device |
| JPS60245172A (en) * | 1984-05-18 | 1985-12-04 | Semiconductor Energy Lab Co Ltd | Insulated gate type semiconductor device |
| JPS60245174A (en) * | 1984-05-18 | 1985-12-04 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated gate type semiconductor device |
| JPS60245173A (en) * | 1984-05-18 | 1985-12-04 | Semiconductor Energy Lab Co Ltd | Insulated gate type semiconductor device |
| JP2996887B2 (en) * | 1984-05-18 | 2000-01-11 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device |
| US4727044A (en) | 1984-05-18 | 1988-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of making a thin film transistor with laser recrystallized source and drain |
| JP2648784B2 (en) * | 1984-05-18 | 1997-09-03 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device for liquid crystal display panel |
| DE3587100T2 (en) * | 1984-10-09 | 1993-09-09 | Fujitsu Ltd | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT BASED ON THE SEMICONDUCTOR ON ISOLATOR TECHNOLOGY. |
| JPS61158185A (en) * | 1984-12-28 | 1986-07-17 | Hosiden Electronics Co Ltd | Thin film transistor |
| JPS62214669A (en) * | 1986-03-14 | 1987-09-21 | Nec Corp | Self-aligned amorphous silicon thin film transistor and manufacture thereof |
| JPS62254470A (en) * | 1986-04-28 | 1987-11-06 | Seiko Instr & Electronics Ltd | Manufacture of junction type thin film transistor |
| DE69125886T2 (en) | 1990-05-29 | 1997-11-20 | Semiconductor Energy Lab | Thin film transistors |
| JP2794678B2 (en) | 1991-08-26 | 1998-09-10 | 株式会社 半導体エネルギー研究所 | Insulated gate semiconductor device and method of manufacturing the same |
| JP3255942B2 (en) | 1991-06-19 | 2002-02-12 | 株式会社半導体エネルギー研究所 | Method for manufacturing inverted staggered thin film transistor |
| JP2845303B2 (en) * | 1991-08-23 | 1999-01-13 | 株式会社 半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| US5485019A (en) | 1992-02-05 | 1996-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JP3173854B2 (en) * | 1992-03-25 | 2001-06-04 | 株式会社半導体エネルギー研究所 | Method for manufacturing thin-film insulated gate semiconductor device and semiconductor device manufactured |
| JP2648785B2 (en) * | 1992-11-20 | 1997-09-03 | 株式会社半導体エネルギー研究所 | Method for manufacturing insulated gate field effect semiconductor device |
| JP2648783B2 (en) * | 1992-11-20 | 1997-09-03 | 株式会社半導体エネルギー研究所 | Insulated gate field effect semiconductor device for liquid crystal display panel |
| US6331717B1 (en) | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| JP3173926B2 (en) | 1993-08-12 | 2001-06-04 | 株式会社半導体エネルギー研究所 | Method of manufacturing thin-film insulated gate semiconductor device and semiconductor device thereof |
| JP2996854B2 (en) * | 1994-01-27 | 2000-01-11 | 株式会社 半導体エネルギー研究所 | Method for manufacturing insulated gate field effect semiconductor device |
| JP2648788B2 (en) * | 1994-06-10 | 1997-09-03 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device |
| JP2789168B2 (en) * | 1994-06-10 | 1998-08-20 | 株式会社 半導体エネルギー研究所 | Method for manufacturing insulated gate field effect semiconductor device for liquid crystal display panel |
| JP2500484B2 (en) * | 1994-07-11 | 1996-05-29 | ソニー株式会社 | Thin film transistor manufacturing method |
| JP2789171B2 (en) * | 1994-11-25 | 1998-08-20 | 株式会社 半導体エネルギー研究所 | Method for manufacturing insulated gate field effect semiconductor device |
| JP2996888B2 (en) * | 1994-11-25 | 2000-01-11 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device |
| JP2789170B2 (en) * | 1994-11-25 | 1998-08-20 | 株式会社 半導体エネルギー研究所 | Method for manufacturing insulated gate field effect semiconductor device |
| JP2996902B2 (en) * | 1995-09-01 | 2000-01-11 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device for liquid crystal display panel and method of manufacturing the same |
| JP4888414B2 (en) * | 2008-02-15 | 2012-02-29 | ローム株式会社 | Manufacturing method of semiconductor device |
-
1981
- 1981-06-29 JP JP10088081A patent/JPS582073A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS582073A (en) | 1983-01-07 |
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