JPS59222A - Quantizing method of binary-coded signal - Google Patents

Abstract

PURPOSE:To eliminate the need for shortening a repeated period of a clock signal, and to detect effectively an abnormal pattern having minute width or length, by expanding the width of a binary-coded signal of specified width or less, and thereafter, quantizing it. CONSTITUTION:A binary-coded signal from a signal input terminal 6 is inputted to the first pulse signal generating circuit 7 and an OR circuit 8 of the first block, and the second pulse signal generating circuit 11 and an AND circuit 12 of the second block. By this first block, only width d1 in width d1, d2 smaller than a repeated period gamma of the binary-coded signal is expanded to width (t). Subsequently, by the second block, width d2 is expanded to width (t), and outputs of the respective circuits 8, 12 are given to shift registers 13, 14. Subsequently, a clock from a clock signal generating circuit 9 is given to the registers 13, 14, and an abnormal pattern having minute width or length is detected effectively without shortening a repeated period of a clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for quantizing a binary signal using a clock signal as a reference.

(b) Background of the technology In pattern inspection of printed wiring boards, etc., the pattern to be inspected is scanned with a light beam, and the output signal obtained corresponding to the width or length of the pattern to be inspected is measured using a clock signal as a reference. The width or length of the pattern to be inspected is measured by counting the number of sampling pulses.

In the pattern inspection described in Section 2, in addition to the predetermined patterns, abnormal patterns with a width less than a predetermined width or a length less than a predetermined length that occur accidentally, such as short-circuit patterns between predetermined wiring patterns or disconnection patterns that cross predetermined wiring patterns, etc., are also inspected at the same time. It is necessary to detect.

(c) Prior art and problems The general method of quantizing a binary signal conventionally used in pattern inspection as described above is to repeat the binary signal with a repetition period τ as shown in Fig. 1. The sample is taken using the clock signal as a reference, and the binarized signal value at the time of sampling is used as a quantized signal value in units of period -τ. For this purpose, di or d in Figure 1 (a)
2, a binary signal whose width is smaller than τ and whose timing does not match the timing of the clock signal (b) is not sampled and is lost in the quantized signal (c). A situation arises. As a result, in the pattern inspection, abnormal patterns having a width or length smaller than a predetermined value are overlooked.

(d) Object of the invention An object of the present invention is to provide a method for picking up signals having a width smaller than a specific width in a binary signal as a unit quantized signal without losing them.

(e) Structure of the Invention The present invention is characterized in that in a binarized signal, a binarized signal having a specific width or less is quantized after expanding this width. Examples will be described with reference to the drawings.

In the following drawings, the same parts as in FIG. 1 are designated by the same reference numerals.

FIG. 2 is a diagram showing an enlarged example of a part of a pattern of a printed wiring board inspected by a pattern inspection apparatus to which the present invention is applied.

In the figure, 1 and 2 are patterns having a width of a predetermined value, and 3 is an abnormal pattern that causes a short circuit between patterns 1 and 2, and has a width of -2 smaller than -1. 4 is an abnormal pattern that causes a disconnection in pattern l, and its width - 3 is the width.If a pattern like the one shown in Figure 2 is scanned over the dashed arrow 5, a binary value as shown in Figure 3 ( signal is obtained.

In the present invention, the binary signal shown in FIG. 3(a) is quantized as follows.

That is, first, the binary signal (a) is input to the first pulse signal generating circuit to obtain the output signal shown in (b).

The first pulse signal generation circuit has a function of turning on at the rising edge of the binary signal (A) every time the binary signal (A) is input, and returning to the output F after generating a pulse signal with a wide width.

Next, when the binary signal (A) and the output signal (B) of the first pulse signal generation circuit are input to the OR circuit, the output signal shown in (C) is obtained. When the output signal (c) of this OR circuit is quantized using a clock signal (d) having a repetition period τ, a quantized signal 1 as shown in (b) is obtained.

- input the output signal and the binary signal (1) to the second pulse signal generation circuit to obtain the output signal shown in (2).

The second pulse signal generation circuit has a function of turning OFF at the falling edge of the binary signal (A) every time it is input, and returning to ON after maintaining F for a certain period of time.

Next, when the binary signal (A) and the output signal (H) of the second pulse signal generation circuit are input to the AND circuit, (G)
The output signal shown in is obtained. When the output signal (g) of this AND circuit is quantized using a clock signal (d) having a repetition period τ, a quantized signal 2 as shown in (h) is obtained.

Note that the time t in the output signals of the first and second pulse signal generating circuits is selected to be approximately equal to the repetition period τ of the clock signal.

Comparing Figures 3 (E) and (H) with Figure 1 (C), in Figure 1 (C) the binarized signal (
In contrast to the signal with width d1 or d2 smaller than τ in Fig. 3(e), the binary signal (logical value 1
) has been picked up and quantized as old, and
Similarly, in FIG. 3 (H), the width d is smaller than τ.
A binary signal having a value of 2 (logical value 0) is picked up and o
It is quantized as 2.

Therefore, the abnormal pattern 3 and the abnormal pattern 4 corresponding to the widths d1 and d2 in the binarized signal (A) are detected as Ql in the quantized signal 1 and g2 in the quantized signal 2, respectively. These are determined as conductive portions and non-conductive portions that exist at positions other than the predetermined positions in the pattern to be inspected.

FIG. 4 is a circuit block diagram for obtaining a quantized signal as shown in FIG. 3, in which 6 is a binary signal input terminal, 7 is a first pulse signal generation circuit, and 8 is an OR circuit. , 9
1 is a clock signal generation circuit; 10 is a shift register that stores the quantized signal l; 11 is a second pulse signal generation circuit;
12 is an AND circuit, and 13 is a shift register that stores the quantized signal 2.

FIG. 5 is a diagram showing an embodiment of the present invention.

In this embodiment, a first block consists of a first pulse signal generation circuit 7 and an OR circuit 8, and a second block consists of a second pulse signal generation circuit 11 and an 8NJ) circuit 12 shown in FIG. are connected in series, and as shown in FIG.
First, only the binary signal (logical value 1) is expanded in width in the first block, and the output signal (c) of the OR circuit is sent to the second block, that is, the second pulse signal generation circuit 1.
1 and the AND circuit 12 to expand the binary signal (logical value O) of width d2 to width t, and then quantize the output of the AND circuit 12 and store it in the shift register 14.

The time sequence of the signals in this case is as shown in FIG. 6, and in the binary signal (A), a signal (logical value 1) having a width d1 smaller than the repetition period τ of the clock signal and a signal having the same width d2. (logical value 0) is expanded to a width t in the output signal (b) of the AND circuit, and these signals are quantized by the clock signal (c), and the resulting quantized signal (d) is are stored in the same shift register as all other quantized signals as Q3 and Q4'', respectively.

(g) Effects of the Invention According to the present invention, since a binary signal having a width smaller than the width of a clock signal for quantization is quantized without being lost, minute widths can be used in pattern inspection, etc. Alternatively, there is an effect that an abnormal pattern having a long length can be detected without being overlooked. Furthermore, according to the present invention, there is no need to shorten the repetition period of the clock signal in order to quantize a binary signal with a small width, and as a result, the amount of data bits increases. This has the effect of reducing the burden on subsequent processing circuits and maintaining high processing speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the conventional quantization method of a binary signal, FIG. 2 is a diagram showing an enlarged example of a part of the pattern of a printed wiring board, and FIG. 3 is a diagram for explaining the conventional quantization method of a binary signal. FIG. 4 shows a time sequence of a signal in quantization of a signal.
The figure is a block diagram of one pass for performing quantization according to the tights sequence of Figure 3, Figure 5 is a block diagram of a circuit showing an embodiment of the present invention, and Figure 6 is a block diagram of a circuit for performing quantization according to the tights sequence of Figure 3. FIG. 3 is a diagram showing a time sequence of signals when quantization is performed by the circuit shown in the figure. In the figure, 1 and 2 are printed wiring patterns having predetermined dimensions, 3 is an abnormal pattern that causes a short circuit, 4 is an abnormal pattern that causes a disconnection, 5 is a scanning direction, 6 is a signal input terminal, and 7 is a first pulse signal. 8 is an OR circuit, 9 is a clock signal generation circuit, 10, 13 and 14 are shift registers, 11 is a second pulse signal generation circuit, and 12 is a NO circuit. PZ diagram ￥ = 5 diagrams

Claims (1)

[Claims] A method for quantizing a binarized signal, characterized in that, in quantizing a binarized signal, a binarized signal having a width below a certain width is quantized after expanding this width.