JPS59220951A - マスタスライス型半導体記憶装置の接続方法 - Google Patents

マスタスライス型半導体記憶装置の接続方法

Info

Publication number
JPS59220951A
JPS59220951A JP58096825A JP9682583A JPS59220951A JP S59220951 A JPS59220951 A JP S59220951A JP 58096825 A JP58096825 A JP 58096825A JP 9682583 A JP9682583 A JP 9682583A JP S59220951 A JPS59220951 A JP S59220951A
Authority
JP
Japan
Prior art keywords
data
data lines
memory cell
pairs
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58096825A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0444429B2 (enExample
Inventor
Hiroaki Suzuki
宏明 鈴木
Masaharu Kawachi
正治 河内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP58096825A priority Critical patent/JPS59220951A/ja
Publication of JPS59220951A publication Critical patent/JPS59220951A/ja
Publication of JPH0444429B2 publication Critical patent/JPH0444429B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP58096825A 1983-05-31 1983-05-31 マスタスライス型半導体記憶装置の接続方法 Granted JPS59220951A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58096825A JPS59220951A (ja) 1983-05-31 1983-05-31 マスタスライス型半導体記憶装置の接続方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58096825A JPS59220951A (ja) 1983-05-31 1983-05-31 マスタスライス型半導体記憶装置の接続方法

Publications (2)

Publication Number Publication Date
JPS59220951A true JPS59220951A (ja) 1984-12-12
JPH0444429B2 JPH0444429B2 (enExample) 1992-07-21

Family

ID=14175334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58096825A Granted JPS59220951A (ja) 1983-05-31 1983-05-31 マスタスライス型半導体記憶装置の接続方法

Country Status (1)

Country Link
JP (1) JPS59220951A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2607910B1 (en) * 2011-12-23 2016-03-23 Samsung SDI Co., Ltd. A device and method for estimating life of a secondary battery

Also Published As

Publication number Publication date
JPH0444429B2 (enExample) 1992-07-21

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