JPS59220927A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control the depth of etching to be extremely shallow by subjecting a semiconductor layer including Ga or As to reactive ion etching using hydrogen gas or a mixed gas of hydrogen gas and inert gas. CONSTITUTION:On a semi-insulating GaAs substrate 11, a non-doped GaAs layer 12, an N type AlGaAs layer 13, an N type GaAs layer 14 and an N type GaAs layer 15 are grown. Next, source electrodes 17 and 17' and drain electrodes 18 and 18' are formed and an element isolating region 20 is formed. Next, a mask 21 is arranged and etching is done to a depth of about 10nm in a gate region 22 of a depletion mode FET and to a depth of about 30nm in a gate region 23 of an enhancement mode by reactive ion etching method with using H2 gas as an etching gas. In this case, plasma formation and etching speed can be controlled by adding inert gas to H2 gas. Thus, it becomes possible to control the etching of a depth in the order of under 10nm or so.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a method for etching a compound semiconductor layer containing 1% of gallium or arsenic with extremely high precision.

(b) Technical Background At present, with the aim of further improving the capabilities and cost performance of information processing devices, etc., semiconductor devices are becoming faster and with lower power consumption. )Yo! 7) Very large gallium arsenide (GaAs)
Many transistors using compound semiconductors such as ) have been proposed. Among these compound semiconductor transistors, heterojunction field effect transistors (hereinafter referred to as heterojunction FE transistors) achieve an increase in carrier mobility by using electrons spatially separated from impurities through modulation doping.
(abbreviated as T).

Also, optical fiber communication, etc., uses light as an information signal medium.
In the system, optical semiconductor devices such as semiconductor lasers and photodiodes are the most important and fundamental components.

The characteristics of these optical semiconductor devices are also being improved by using a superlattice structure in which the double heterostructure active layer and the like have quantum theoretical dimensions.

As shown in the above examples, the ultra-fine design of semiconductor devices is not only about making the pattern on the surface of the semiconductor substrate into a V-sized micron, but also controlling the thickness of the semiconductor substrate to the order of tens of nanometers (nm) in the thickness direction. (C) Prior art and problems In order to form a pattern on the surface of a semiconductor substrate in the manufacturing process of a semiconductor device, selective etching is performed using a mask or the like. In FETs and the like, it is sometimes necessary to perform etching to a midpoint in the thickness direction of one semiconductor layer and control the etching accuracy to, for example, 10 [nm] or less.

As an etching method in the manufacturing process of semiconductor devices,9 for example, phosphoric acid (H
A wet etching method using a hydrofluoric acid (IF) solution or the like is used.

However, in the wet etching method, selectivity in the etching direction is usually low and side etching progresses to a large extent, resulting in a significant drop in pattern accuracy and it is extremely difficult to uniformly and precisely control the etching depth.

For the purpose of improving pattern accuracy on the surface of a semiconductor substrate and streamlining the process, the wet etching method is being replaced by a dry etching method.

Dry etching techniques include those in which the etching mechanism is based on chemical action, physical action, and chemical and physical action.

An example of a chemical dry etching method is a plasma etching method. The low-temperature gas plasma normally used in plasma etching is obtained by introducing a suitable reactive gas into a reaction tube at a pressure of about 0.1 to 10 Torr and applying high frequency power thereto. Although the degree of ionization of this gas plasma is usually low, it contains many atoms and molecules that have become excited through various collision processes. Atoms and molecules in this excited state have high chemical activity.

A chemical reaction occurs between atoms on the sample surface that comes in contact with the gas plasma, and as a result, volatile reactants are generated.
Atoms are removed from the sample surface and etched.

This plasma etching method usually has high selectivity to the material to be processed, and the etching direction is iso-directional.On the other hand, in the physical dry etching method, particles with large kinetic energy, usually ions, collide with different surfaces of the solid. This is an etching method that utilizes the sputtering phenomenon that occurs when There are 8 trades that have poor selectivity and still require attention to damage to the semiconductor substrate due to ion bombardment.

Although an inert gas is used in the sputter etching method, by using this as a reactive gas, a chemical reaction and a sputtering effect coexist, and selectivity regarding the material to be processed and the U-etching direction can be obtained. This etching method is called active ion etching or reactive spatter etching.

Among the various dry etching methods explained above, an example of application to Ga8 compound semiconductors is as follows.

Active ion etching methods using chlorine-based or fluorine-based gases, and plasma etching methods using hydrogen gas are known.

7. Using chlorine or fluorine gas. In the IJ active ion etching method, the etching speed is usually high (generally several hundred (nm/-7s) to several [am
/-1=3), and the etching depth was set to 10 [nm] in the middle of the layer.
] It is generally impossible to control the temperature below this level.

Further, in such a gas system, contamination of the semiconductor substrate surface by chloride or fluoride often becomes a problem.

On the other hand, the HW gas plasma etching method is thought to have less influence of surface contamination, but it is extremely difficult to control the etching depth. In addition, the controllability of the pattern shape is not good either.

(cll Purpose of the Invention The present invention aims to solve the above-mentioned problems by using gallium (Ga).
It is an object of the present invention to provide an etching method capable of controlling the etching depth and accuracy to about 10 Cnm or less for compound semiconductors containing arsenic (AS). The purpose is to etch a compound semiconductor layer containing at least gallium or arsenic by an active ion etching method using hydrogen gas or a mixed gas of hydrogen gas and an inert gas as an etching gas.
) consists of.

In other words, in the above-mentioned plasma etching method using H2 scum, the etching rate is too low for the purpose of the present invention because the concentration of excited neutral hydrogen atoms in the plasma is high. In contrast, in the adhesive active ion etching method of the present invention, ionized hydrogen atoms, which have a much lower concentration than neutral hydrogen atoms in the plasma, are made to enter the semiconductor substrate to be processed that is placed on the electrode. Since etching is performed using the sputtering effect in the incident direction and the chemical reaction caused by hydrogen ions, the etching speed is slow, making it possible to precisely control the etching depth and improving the accuracy of the pattern shape. It becomes extremely good.

The present invention can be practiced using a conventional reactive ion etching apparatus such as that illustrated in FIG.

Electrodes 2 and 3 are provided vertically and oppositely in the etching chamber 1, and gas is introduced and discharged through an air supply pipe 4 and an exhaust pipe 5. The lower electrode &2 is supported by the insulator 6, and high frequency power is applied between it and the upper counter electrode 3, so that plasma 7 is formed between both electrodes except in the vicinity of the electrode 2. By placing the semiconductor substrate 8 to be processed on the electrode 2, the active ion etching method described above and FIG.
FIG. 4 is a diagram showing an example of the correlation between etching rate and hydrogen gas pressure when etching is performed on a (al-xAs) semiconductor layer. However, the plasma in this example has a frequency of 13.
56 [M)12], power density 5×10-” (W/
cyn-') is generated by the electromagnetic field. In the figure, curve A is GaAs semiconductor layer 1 line BxGal
-xAs (x-0,3) The case of a semiconductor layer is shown.

In FIG. 2, curves A and B both indicate a hydrogen gas pressure of 5[
It shows a maximum value near Pa), and the etching rate at that time is 4 [nm/m) and 3Cnm/-=#)
That's about it. At this maximum hydrogen gas pressure, the ratio of ionized hydrogen atoms in the plasma becomes extremely large.
Etching treatment systems are the most stable. Note that when the hydrogen gas pressure is about 1 [Pa] or less or about 50 [Pa] or more, no plasma state is generated.

In this way, for example, by achieving an etching rate of about 4 [nm/-m] with high stability, 1
It becomes possible to easily control the etching depth with an accuracy of 0 (nm1fl) or less.

(f+ Embodiments of the Invention Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

FIGS. 3(a) to 3(C) are cross-sectional views showing an example in which the present invention is implemented in the manufacturing process of a heterojunction FET.

Referring to FIG. 3(a), non-doped GaAJ is placed on a semi-insulating GaAs substrate 11.
@1'2 to a thickness of about 300 [:nm], for example.

An n-type At0.3GaO87A13 layer 13 doped with silicon (Sl) to, for example, about 1×10 [100-1]
For example, when the thickness is about 20 (nm), the At composition ratio X gradually decreases from 0.3 to n-type A4xGa.
The l-xAEI layer 14 is sequentially grown to a thickness of about 20 [nm] and the n-type GaAe layer 15 to a thickness of about 40 [nm] by molecular beam epitaxial growth or the like. 16 is the n-type AtO of the non-doped GaAs layer 2;
This is a two-dimensional electron gas formed near the heterojunction interface with the 3GaO, 7As layer 13.

Next, the source electrodes 17 and 17' and the drain electrodes 18 and 18' are made of, for example, gold/germanium/gold (Au).
A low-resistance ohmic connection region 19 is formed by forming it using Gθ/AU) and performing a heat treatment to alloy it with the n-type GaAs layer 15 or the like. The inter-element isolation region 20 is still formed by, for example, ion implantation of oxygen (4).

FIG. 3(b) For the purpose of controlling the reference gate threshold voltage, the n-type GaAs layer 1
Selective etching is performed on the gate region No. 5 using a mask. In this example, 1, for example, silicon dioxide (
A mask 21 is provided by a film (sins) to a depth of approximately 10 Cnm for the gate region 22 of the depletion mode FET, and the enhancement mode FET is
According to the present invention, the gate region 23 is etched to a depth of about 30 [nm] using +Ht gas pressure of about 5 ['Pa].
), high frequency power density approximately 4 × 10” CW'/C
+4).

Etching speed is also controlled by high-frequency power; for example, if the high-frequency power is doubled, the etching speed will be approximately 15 times higher. However, if the power is too low, the plasma will not be formed stably, and the etching speed will be too high. In order to cause strong damage to the semiconductor substrate to be processed, the high frequency power density is I x 1.
The optimum value is selected within a range of approximately 0-'' to 4 x 10-'(w/m-''3), taking into account the above factors.

Furthermore, by adding an inert gas to the H+ gas, the degree of freedom in controlling plasma formation, etching rate, etc. can be expanded.

In the present invention, which is mainly intended for semiconductor substrates constituted by extremely thin semiconductor layers, such as the heterojunction FET of this embodiment, it is particularly important that the sputtering effect does not damage the semiconductor substrate to be processed.

In FIG. 3(C), reference gate electrodes 24 and 24' are formed of, for example, aluminum (At) on the etched surfaces of the gate regions.

The gate threshold voltage of this example is degree-7 Yonmo)
"Approximately -0-5 [V] for FET * x y enhancement mode F) Iγ0 [V] for IiT
The inter-element and in-plane distributions are significantly improved compared to the prior art.

Although the above description and examples refer to GaAB and AzGaAs as semiconductor materials, one
Similar effects can be obtained with compound semiconductors containing gallium or arsenic, such as gallium-antimony (Garb), gallium-phosphorus (Gap), indium-arsenic (GaAs), or gallium-indium-arsenic (GaInAs).

(gl) As described in detail, according to the present invention, when etching a compound semiconductor layer containing gallium or arsenic, the depth is reduced to 1
It can be easily controlled to an accuracy of 0 Cnmli degree or less, has good uniformity, and has excellent pattern accuracy, making it suitable for industrial implementation of quantum-theoretical dimensions required for, for example, heterojunction FETs. Contribute to dogs.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of an etching apparatus used in carrying out the present invention, FIG. 2 is a diagram showing an example of the correlation between etching rate and hydrogen gas pressure, and FIGS. FIG. 1 is a sectional view showing an embodiment of the invention. In the figure, 11 is a GaAe substrate, 12 is a non-doped GaAG layer, 13 is an n-type AtGaAs layer, 14 is an n-type graded AtGaAs a, 15 is an n-type GaAs layer,
16 is a two-dimensional electron gas, 17 and 17' are source electrodes,
1.8 and 0.18I are drain electrodes. 19 is an ohmic connection region, 20 is an inter-element isolation region, 2
1 is a mask, 22 and 23 are gate regions. 24 and 24' indicate gate electrodes. V-1 hydrogen at 1 pressure η r /' (3 flashes of IJ)

Claims (2)

[Claims] (1) It is characterized by comprising a step of etching a compound semiconductor layer containing at least gallium or arsenic by using hydrogen gas or a mixed gas of hydrogen gas and an inert gas as an etching gas or by an active ion etching method. A method for manufacturing a semiconductor device. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor is at least - of gallium arsenide and aluminum/gallium arsenide.