JPH0498833A - Etching method for compound semiconductor - Google Patents

Abstract

PURPOSE:To minimize the dispersion in the element characteristics for augmenting the yield by a method wherein a compound semiconductor substrate is alternately immersed in a solution for the surface oxidation and another solution for removing the surface oxide layer while the frequency is controlled to evenly etch away the oxide layer by the specific depth. CONSTITUTION:The solution oxidizing the n-GaAs layer 4 only exposed in a resist hole part 6 e.g. hydrogen peroxide is used to oxidize the surface 7 to be dried up after washing with water. Next, the solution melting down the oxidized part 7 only e.g. phospholic acid is used to remove the oxide film to be washed with water later. Through these procedures, the oxide layer can be formed always in the constant thickness thereby enabling the etching process in the constant depth to be performed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is an etching method used when etching a compound semiconductor by a minute amount, for example, in recess etching of a field effect transistor (FET). Regarding the law.

(Prior Art) Regarding the etching of compound semiconductors, there are a wet etching method that utilizes a chemical reaction in a solution, and a dry etching method that uses plasma, ions, etc.

As an example of conventional etching, a high electron mobility transistor (hereinafter abbreviated as HEMT) having a gate recess structure formed on a compound semiconductor substrate will be described here.

FIG. 2 is a cross-sectional view of the HEMT gate recess structure. H
The channel layer of an EMT is generally an undoped GaAs layer 12 on a semi-insulating gallium arsenide (GaAs) substrate 11.
．． Si-doped n-type aluminum, gallium, arsenic (n
-AIGaAs) layer 13 and n-type gallium arsenide (n-
(GaAs) layer 14. The thickness of each of these layers is about 10,000A, 300A, and 500A, respectively, and the doping concentration of the n-type layer is about I x 10” cm.
-' and high electron concentration. Therefore, when forming the gate electrode 9, a recess structure 18 is formed in the channel layer, as shown in FIG. 2, for the purpose of obtaining a desired current value and improving the gate breakdown voltage. To obtain this recessed structure,
Etching is performed by the wet method or dry method described above. At this time, due to the structure, the etching depth is required to have an accuracy of several tens of amps.

FIG. 3 shows a conventional etching method.

As shown in FIG. 3(a), an undoped GaAs layer 22. n-AlGaAs layer 23
and n-GaAs layer 24 are sequentially formed.
- A resist film 25 is formed on the GaAs layer 24, and a third
As shown in Figure (b), a resist opening 26, that is, a gate pattern, is formed by mask exposure and development. After that, as shown in FIG. 3(C), this resist film 25 is
Using this as a mask, the recess structure 28 is formed by wet etching using a mixed solution of phosphoric acid and hydrogen peroxide as an etchant, or dry etching such as reactive ion etching (RIE).

(Problem to be solved by the invention) However, with these etching methods, it is extremely difficult to stop etching a channel layer with a high electron concentration at a depth at which a desired current value is obtained, and current adjustment is extremely difficult. . FIG. 4 shows the relationship between the HEMT current value, recess depth, and etching time when recess etching is performed. According to this, the current value fluctuates considerably even with a slight change in machining/nching time.
It is difficult to determine the current value based on the etching time.

In addition, with wet etching time, the uniformity of etching depth within one surface of the wafer is poor, and it is difficult to uniformly etch the etching depth in units of tens of amps. For this reason, when manufacturing the device, the yield was quite low.

Even in dry etching, there are problems such as not being able to obtain high performance characteristics due to damage and contamination caused to semiconductor substrates, and in terms of uniformity within the same area, it is highly affected by equipment dependence, resist pattern shape, and number of substrates processed. There are drawbacks.

The present invention eliminates the above-mentioned drawbacks, and provides an etching method with good reproducibility of etching depth and good uniformity of etching depth within the plane of the wafer, thereby reducing variations in device characteristics. The purpose is to reduce the amount and improve the yield.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, in the present invention, a compound semiconductor substrate is alternately immersed in a solution that oxidizes the surface and a solution that removes this surface oxidation layer, and Control and uniformly machine and notch to the desired depth.

(Function) When a compound semiconductor substrate is immersed in a solution that oxidizes the surface,
The oxidized depth is saturated in a short time, and an oxidized layer of approximately constant thickness is formed. The oxide layer is then removed using a solution that removes the oxide layer, thereby etching the layer to a certain thickness.

(Example) FIG. 1 shows an example of the present invention. FIG. 1(a) is a sectional view showing the state before etching according to the present invention.

The n exposed in the resist opening 6 in FIG. 1(a)
- Using a solution that oxidizes only the GaAs layer 4, for example, an aqueous hydrogen peroxide solution, the surface is oxidized 7 as shown in FIG. 1(b), washed with water, and then dried. Next, the oxidized portion is dissolved and removed using a solution that dissolves only the oxidized portion, such as phosphoric acid, as shown in FIG. 1(C). After removing the oxide film, wash with water.

According to this method, the oxidation depth is saturated in a short time,
For example, even if it is immersed in a solution for 30 to 60 seconds, the oxide layer is always formed with a constant thickness. A certain amount of etching is then possible by dissolving and removing this oxide layer. Moreover, the formation of the oxide layer and the subsequent dissolution of the oxide layer are hardly affected by slight temperature changes and stirring methods. By repeating these steps, it becomes possible to perform extremely uniform and easily controlled etching to a desired depth. That is, unlike the wet etching method or dry etching method used in conventional recess etching, the method of the present invention involves repeating and stepwise steps of oxidizing the surface layer of the n-GaAs layer and removing the oxidized layer. This makes it ideal for extremely small amounts of etching.

FIG. 5 shows the etching rate of GaAs performed by the method of the present invention. According to this, it is possible to etch approximately 17 to 18 A with one oxidation and removal of the oxide layer.

Note that the present invention is not limited to n-GaAS for HEMT;
In AlGaAs, the oxidation rate is almost the same as that in GaAs.
It is possible to remove the oxide layer, including indium-gallium-arsenic-phosphorus (InGaAsP)
Of course, it can be applied to various compounds such as nP).

[Effects of the Invention] As described above, according to the present invention, it is possible to extremely uniformly and easily control minute etching depth in etching when forming a recess structure in a compound semiconductor substrate.

Figure 6 shows the HEMT obtained by conventional recess etching.
(Fig. 6(a)) and the HEMT current (C1ds) distribution obtained by recess etching according to the method of the present invention.
I d s) distribution (FIG. 6(b)).

This shows that the method of the present invention can achieve uniformity of device characteristics and improvement of yield. Furthermore, since oxidation and oxide film removal can be carried out uniformly regardless of the area of the semiconductor substrate, it is also suitable for uniformly etching a semiconductor substrate with a large area and large diameter.

[Brief explanation of drawings]

1(a) to (C) are cross-sectional views showing the steps of oxidation and oxide layer dissolution removal in the recessing step of the compound semiconductor substrate of the present invention,
Figure 182 is a cross-sectional view showing the gate recess structure of HEMT,
Fig. 3 is a cross-sectional view showing the conventional etching process, and Fig. 4 shows the etching time and HEMT in conventional wet etching.
FIG. 5 is a diagram showing the relationship between current value and recess depth, and FIG. 5 is a diagram showing the etching rate of GaAs according to the method of the present invention. ′! Figure 86 shows the HEMT current (■d
s) Distribution map comparing the distribution with that according to the conventional method. 11, 21-Semi-insulating GaAs substrate 12.22-Undoped GaAs layer 13.23-n-AlGaAs 14.24-n-GaAs 15.25...-Resist film 16-Resist opening... ...Semiconductor substrate oxidized state...7 oxidized portion removed 18.28...Recess-etched portion...
...Gate electrode, 6mm L'nu r-tH7,"F/7 II"bth

Claims (1)

[Claims] A method for etching a compound semiconductor comprising the steps of oxidizing a surface layer of the compound semiconductor and removing the oxidized layer.