JPS59217367A - Charge transfer device and driving method thereof - Google Patents

Abstract

PURPOSE:To drive the titled device at high speed without causing the decrease of S/N ratio by a method wherein a transfer gate electrode immediately before an output gate electrode is wired separately from other transfer gate electrodes. CONSTITUTION:A diffused region 9 is reset by making a reset pulse phiR at an H level at a time t'1B. The diffused region 9 is put in a floated state by making the pulse phiR at an L level at a time t2B. Charges which have been accumulated under the transfer gate electrode 4-2' are transferred to the diffused region 9 by making clock phi1L at an L level at a time t3B. At this time, the clocks phi1 and phi2 are in the same state as at the time t2B, while charges under the other transfer gate electrodes 3-1, 4-1, and 3-2 remain accumulated under the gate electrode whereon phi1 is impressed. At a time t4B, phi1 turns to an L level and phi2 to an H level, and then the charges move from under the phi1 gate to the channel potential under the phi2 gate. Therefore, the transfer gate electrode 4-2' shields the diffused region 9 from noise mixture from the transfer gate electrode 3-2; accordingly, the elongation of the period of signal output is enabled without decreasing the S/N ratio of the signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a charge transfer device and a method for driving the same.

[Prior art]

An example of a charge transfer device is shown in FIG.
By applying clock pulses (hereinafter simply referred to as clocks) φ□ and φ2 to a plurality of charge transfer gate electrodes 3-1, 4-1, 3-2, and 4-2 successively arranged via Second, charge transfer is performed using charge transfer channels formed under these transfer gate electrodes 3 and 4.

The transferred charge is a constant voltage ■. The signal is transferred to an N-type semiconductor multi-charge detection diffusion region 9 (hereinafter referred to as diffusion region 9) through a channel formed under the output gate electrode 5 to which 0 is added. A potential change in the diffusion region 9 due to the inflow of charge into the diffusion region 9 is detected by a source follower circuit consisting of an output MO8I transistor 11 and a resistor RLx4, and the output voltage is determined as (2). It is taken out from the UT terminal 13. Note that 6 is the gate electrode of the reset MOS transistor, 10 is an N-type drain diffusion region, and the transferred carriers are electrons.

Next, we will explain this normal operation using the time chart in Figure 2 and the time chart in Figure 3.
This will be explained using potential explanatory diagrams shown in FIGS. (a) to (d). Note that FIG. 3(a) is a schematic cross-sectional view of the device when a reset pulse φ is applied at time t1. becomes “H” level, and the potential of the diffusion region 9 becomes ■. Set to D. Time t2
When φ8 is at the l'l L11 level, the diffusion region 9 is in a floating state. At time t3, clock φ□ is “L”
” level, and the clock φ1 immediately before the output gate electrode 5
The charge accumulated in the channel potential under the transfer gate electrode 4-2 to which the voltage is applied is a constant bias ■.

It flows into the diffusion region 9 through the channel under the output gate electrode 5 to which 0 is added. This inflow of charges causes the potential of the diffusion region 9 to change, and this potential change is used as a signal output to the MOS transistors 11. Resistance 14! , jD as the output voltage. It is taken out from the UT terminal 13.

Here, the period in which the signal voltage is stably output is the period indicated by TH in FIG. 2. In the above normal operation, the signal output period TH is the clock φ1. Since it does not become longer than 1/2 period of φ2, during high-speed driving, for example, at a clock frequency fφ□=l OMHz, the signal output period T
In principle, the length of H is as short as 50 nsec. Moreover, in reality, it takes more than 10 n5ec for the charge to flow from the channel under the final transfer gate electrode 3 to the diffusion region 9 to which the clock φ is applied, so the signal output The period TH is 40
n5ec, or less. That is, the conventional charge transfer device has a drawback that it cannot be driven at a sufficiently high speed.

In order to eliminate such drawbacks, in normal high-speed driving, in order to lengthen the stable signal output period TH, the diffusion region 9 is placed in a floating state before signal charges flow in, as shown in the timing chart of FIG. In order to shorten the period during which this occurs, a method is adopted in which the diffusion region 9 is reset immediately before the signal charge flows into the diffusion region 9. This driving method will be explained with reference to potential explanatory diagrams in FIGS. 5(a) to 5(e). In addition, FIG. 5(a) shows a schematic cross-sectional view of the device, and FIG. 5(b) to (e) respectively show tIA l
'2A l '3A.

The potential corresponding to (a) in the same figure at t4A is shown.

At time 'IA, the reset pulse φ8 becomes "H" level, and the potential of the diffusion region 9 becomes ■. Set to D.

At time t2A, the clock φ□ goes to "L" level, and the diffusion region 9 becomes in a floating state.

At time t3A, the clock φ□ becomes L'', and charges flow into the diffusion region 9. Since the reset pulse φ□ is still at the L" level at time t4A, the diffusion region 9 is not reset and continues to maintain the potential at time t3A. However, the final transfer gate electrode 4 immediately before the output gate electrode 5
-2 changes to "H" level at time '4A.

In this way, in this driving method, as can be seen from FIG. 4, the signal output period is THI, and compared to FIG. 2, ΔT
The signal output period increases by H.

However, with this driving method, as shown in FIG. 4, noise appears as shown by the dotted line at the timing of the change of the clock φ1 from the 'L' level to the ')i' level during the signal output period THI. This noise is caused by the first
As shown in the figure, this is due to the coupling capacitance C8 existing between the final transfer gate electrode 4-2 and the diffusion region 9. As described above, the conventional device has the disadvantage that if the reset timing is shifted to increase the signal output period, noise will be mixed in the middle of the signal output period, reducing the S/N ratio.

[Purpose of the invention]

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to make it possible to lengthen the signal output period without introducing noise during the signal output period, thereby reducing the S/N ratio of the signal. An object of the present invention is to provide a charge transfer device and a method for driving the same, which can be driven at a sufficiently high speed without any problems.

[Structure of the invention]

The charge transfer device of the first invention includes a transfer gate electrode and an output gate electrode provided on a surface of a semiconductor substrate with an insulating film interposed therebetween, and at least a charge transfer device adjacent to a portion directly below the output gate electrode of the semiconductor substrate. In the charge transfer device comprising a region of conductivity type opposite to that of the semiconductor substrate disposed as a detection region, the transfer gate electrode immediately before the output gate electrode is wired separately from the other transfer gate electrodes. It consists of what has happened.

'Furthermore, in the method for driving a charge transfer device according to the second aspect of the present invention, the device according to the first aspect of the present invention is applied to the transfer gate electrode immediately before the output gate electrode and the clock pulse applied to the other transfer gate electrode. It consists of applying clock pulses with different waveforms and timings.

[Explanation of Examples]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 6 is a schematic sectional view together with a necessary circuit diagram for explaining one embodiment of the first invention.
Components that are the same as those in the conventional example shown in the figures are given the same reference symbols.

In this embodiment, in the conventional charge transfer device shown in FIG. 1, the transfer gate electrode 4-2' immediately before the output gate electrode is separated from the other transfer gate electrodes 3-1. It consists of separate wiring.

FIG. 7 shows a time chart of drive pulses and output signals in an embodiment of the second invention.

In this embodiment, the device according to the embodiment of the first invention shown in FIG. -2, and the clock pulse φ□ having a waveform and timing different from those of φ2.

Next, the operations of these embodiments are shown in FIGS. 8(a) to (e).
This will be explained with reference to the potential explanatory diagram. Note that FIG. 8 (al is a schematic cross-sectional view of the device, and FIGS. 8(b) to 8(e) are
respectively tIB r t2B r t3B r t4B
The potential corresponding to (a) in the same figure is shown.

At time "IB", the reset pulse φ8 is set to H level, and the diffusion region 9 is reset. Time t2BK IJ
The set pulse φ□ is set to ``L'' level, and the diffusion region 9 is brought into a floating state.At time '3B, the clock φ□ is set to the L'' level, and the charge accumulated under the transfer gate polarity 4-2' is removed. Transfer to the diffusion area 9. At this time,
The clocks φ□ and φ2 are in the same state as time t2B, and as shown in the eighth peak-3B, the other transfer gate electrodes 3-1
, 4-1, and 3-2 remain accumulated under the gate electrode to which the clock φ1 is applied.

As such, the charge moves from under the gate to which the clock φ□ is applied to the channel potential under the gate to which the clock φ2 is applied. What should be noted here is that the clock φ,
The transfer gate 4-2' to which 1 is applied is at time t3B.
II even at t4f3 while changing to 'L' level.
It remains at LI+ level.

Therefore, the clock φ between time t3n and t4B.

φ1. No noise (see FIG. 4) is mixed in at the time of change of φ2. Moreover, even if it occurs, it is due to the coupling capacitance between the transfer gate electrode 3-2 and the diffusion region 9 shown in FIG.
Since it is much smaller than the coupling capacitance C8 between -2' and the diffusion capacitor 9, the amount of noise introduced is negligible. In other words, it can be said that the transfer gate electrode 4-2 shields the diffusion region 9 from noise coming from the transfer gate electrode 3-2.

In this way, if the charge transfer device having the structure of this embodiment and its driving method are used, the S/N ratio of the signal will not be reduced.
It becomes possible to lengthen the signal output period.

Although the above description has been made with respect to buried channels, it goes without saying that it is also applicable to charge transfer devices in which part or all of the device is a surface channel. Furthermore, although the description has been made using two-phase drive, it goes without saying that this can also be applied to three-phase, four-phase, or phase-drive charge transfer devices.

In addition, semiconductor substrates are not limited to P-type, but have conductivity type polarity of 1.
On the contrary, 17. Of course, an N-type semiconductor substrate may be used as long as the positive and negative potentials are reversed.

〔Effect of the invention〕

As described above in detail, according to the charge transfer device and the driving method thereof of the present invention, the wiring of the final transfer gate electrode immediately before the output gate electrode is marked separately from the wiring of other transfer gate electrodes, A clock pulse having a waveform and timing different from the clock pulses applied to other transfer gate electrodes is applied to the final transfer gate electrode, and the potential of the channel potential formed under the same electrode is converted to the level of the signal output vine pulse. Since the mixing of noise due to the noise is eliminated, sufficiently high-speed operation is possible without causing a decrease in the 87N ratio of the signal.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a schematic cross-sectional view of an example of a conventional charge transfer device together with a necessary circuit diagram, Fig. 2 is a time chart of the device shown in Fig. 1 during normal operation, and Fig. 3 Figure (a
) to (d) are diagrams explaining the potential of each part of the device in normal operation of the device in FIG. 1, FIG. 4 is a time chart during operation when the signal output period is lengthened in the device in FIG. 5(a) to (e) are diagrams explaining the potential of each part of the device during operation when the signal output period is lengthened in the device of FIG. 1, and FIG. 6 is a diagram showing an embodiment of the first invention. FIG. 7 is a time chart showing a driving method of an embodiment of the second invention, and FIG. 8 is a diagram showing FIG. 6 in that case. FIG. 2 is a diagram illustrating the potential of each part of the device. 1... P-type semiconductor substrate, 2... Oxide film, 3-1°3-2, 4-1, 4-2, 4-2'.
...Transfer gate electrode, 5...Output gate electrode, 6...Gate electrode for reset MOζ transistor, 7...N-type Rigomeko expansion A pattern layer , 8...
...P-type semiconductor region, 9...N-type charge carrier, 12...Drain power supply terminal, 13...
...V terminal, 14...Resistor, φ1. φ2
．． φ1L...4'2 4th,
ψ2 φ・zo1)9−
ψノ('3 old model 4-(capital) security code''''''7'' spring 7 border θ

Claims (2)

[Claims] (1) A transfer gate electrode and an output gate electrode provided on the surface of a semiconductor substrate with an insulating film interposed therebetween; A charge transfer device comprising a region of a conductivity type opposite to that of a semiconductor substrate, wherein the transfer gate electrode immediately before the output gate electrode is marked separately from the other transfer gate electrodes. . (2) A transfer gate electrode and an output gate electrode provided on the surface of the semiconductor substrate with an insulating film interposed therebetween, and the semiconductor substrate arranged as a charge detection region adjacent to at least immediately below the output gate of the semiconductor substrate. A charge transfer device comprising a conductivity type region opposite to that of the substrate, and wiring disposed to separate the transfer gate electrode immediately before the output gate from the other transfer gate electrodes, is provided. A method for driving a charge transfer device, characterized in that the charge transfer device is driven by applying a clock pulse having a waveform and timing different from clock pulses applied to the other transfer gate electrodes to the transfer gate electrode.