JPH04354141A - Charge transfer device and its driving method - Google Patents

Abstract

PURPOSE:To reduce the leak of reset clock which appears when charge detection capacitance of a charge transfer device is charged. CONSTITUTION:A dummy transistor 9 is arranged in parallel to a reset transistor 5. A clock pulse whose polarity is opposite to the polarity of a reset clock pulse to be applied to the gate of the reset transistor 5 is applied to the gate of the dummy transistor 9. Potential change inverse to the potential change applied to a charge detection capacitance (floating diffusion capacitance) by the reset clock is simultaneously applied. Reset clock leak is reduced, and S/N of a device can be improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device and a method for driving the same, and more particularly to a charge transfer device with improved S/N ratio and a method for driving the same.

0002

2. Description of the Related Art FIG. 2(a) is a circuit diagram showing an output section of a conventional charge transfer device, which constitutes a so-called floating diffusion amplifier.

In the figure, 1 is a channel of a charge transfer element, 2 is a clock gate to which a clock φc is applied, 3 is an output gate to which a DC voltage VGO is applied, 4 is a floating diffusion capacitor CFD as a charge detection capacitor, and 5 is a floating diffusion capacitor CFD. is a reset transistor, 6 is a parasitic capacitance CC1 existing between the gate of the reset transistor 5 and the floating diffusion capacitor CFD4, 7 is a buffer amplifier for transmitting the potential change of the floating diffusion capacitor CFD4 to the output terminal 8, and A is a clock gate. 2. This is a node where the reset transistor 5 and the floating diffusion capacitor CFD4 are connected to each other, and a DC voltage VR and a reset clock φR are applied to the drain and gate of the reset transistor 5, respectively.

Next, the operation will be explained. Figure 2(b)
is a timing chart of the clock φC, the reset clock φR, and the VFD charged to the floating diffusion capacitor CFD4 in the output circuit of the charge transfer device shown in FIG. 2(a). clock φ
c becomes high level, and signal charge QSIG (not shown) is transferred to channel 1 below clock gate 2. On the other hand, at timing t1, a high level reset clock φR is applied to the gate of the reset transistor 5.
is applied, the reset transistor 5 becomes conductive, and the floating diffusion capacitor CFD4 is charged with the potential VR. If the high level of the reset clock φR at this time is VH, then the parasitic capacitance Cc1
6 is charged to the potential VR-VH, and the potential of the node A in the figure, that is, the potential VFD charged to the floating diffusion capacitor CFD is charged to VR.

Next, at timing t2, the reset clock φR becomes low level VL, the reset transistor 5 becomes non-conductive, and the charges stored in the floating diffusion capacitor CFD4 and the parasitic capacitor CC16 are distributed to each. . At this time, the potential VFD of the node A becomes the potential shown in the following equation 1, and the potential decreases by ΔV given by the following equation 2 compared to the timing t1.

[0006]

[Math 1]

[0007]

[Math 2]

Next, at timing t3, the clock φc from the clock gate 2 becomes low level, and the signal charge QSIG stored in the channel 1 under the clock gate 2 is transferred to the node A through the output gate 3. As a result, the potential VFD at the node A decreases by VSIG shown by the following equation 3.

[0009]

[Math 3]

In this operation, the output gate 3 functions as a potential barrier so that the signal charge QSIG is not transferred to the node A at timings t1 and t.

[0011]

Problems to be Solved by the Invention Since the output section of the conventional charge transfer device is configured as described above, when the reset clock φR becomes low level VL and the reset transistor 5 becomes non-conductive, At node A,
Clock leakage △V, which is a component unrelated to the original signal
The clock leakage ΔV is passed through the buffer amplifier 7 to the output terminal 8 and is amplified by an amplifier (not shown) provided after the output terminal 8, causing noise and deteriorating the S/N of the device. This caused the problem of

The present invention was made to solve the above-mentioned problems, and provides a charge transfer device and its driving method that can eliminate reset clock leakage and prevent deterioration of S/N of the device. The purpose is to obtain.

[0013]

[Means for Solving the Problems] A charge transfer device according to the present invention includes a charge detection capacitor, a charge transfer element that transfers a signal charge to the charge detection capacitor, and a reset transistor that controls the potential charged to the charge detection capacitor. A transistor is connected in parallel to the reset transistor, to which a clock pulse having a polarity inverted from that of the clock pulse applied to the reset transistor is applied.

A method for driving a charge transfer device according to the present invention includes a charge detection capacitor, a charge transfer element that transfers a signal charge to the charge detection capacitor, a reset transistor that controls the potential charged to the charge detection capacitor, and the reset transistor. In a charge transfer device having a transistor and a transistor connected in parallel, a clock pulse is applied to the gate of the reset transistor, and at the same time, a clock pulse having a polarity opposite to that of the clock pulse is applied to the gate of the transistor connected in parallel to the reset transistor. Apply a pulse to charge the charge detection capacitor to a constant potential, and then,
The signal charge from the charge transfer element is transferred to the charge detection capacitor.

[0015]

[Operation] In this invention, a clock pulse having a polarity inverted from that of the clock pulse applied to the gate of the reset transistor is applied to the reset transistor that controls the potential charged in the charge detection capacitor (floating diffusion capacitor). transistors are connected in parallel, and at the same time as the clock pulse is applied to the reset transistor, the clock pulse of the reversed polarity is applied to the transistor connected in parallel to the reset transistor. Therefore, a potential fluctuation opposite to the potential fluctuation given by the reset transistor is applied to the charge detection capacitor (floating diffusion capacitor) at the same time, and as a result, the charge detection capacitor (floating diffusion capacitor)
By reducing the potential charged to the reset clock, it is possible to reduce reset clock leakage.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1(a) is a circuit diagram showing an output section of a charge transfer device according to an embodiment of the present invention, and FIG. 1(b) is a circuit diagram showing an output section of a charge transfer device according to an embodiment of the present invention.
1A is a diagram showing a timing chart of clock φC, reset clock φR1, clock φR2, and potential VFD in the circuit shown in FIG. 1(a). FIG. The charge transfer device of this embodiment is the same as that shown in FIG. 2(a) except for the dummy transistor 9 connected in parallel to the reset transistor 5 and the parasitic capacitance CC210 present between the dummy transistor 9 and the floating diffusion capacitor CFD4. A clock φR2 having a polarity opposite to that of the reset clock φR1 is applied to the gate electrode of the dummy transistor 9.

Next, the operation will be explained. Figure 1(b)
At timing t1 shown in , the reset clock φ
R1 becomes high level VH1, and dummy transistor 9
The clock φR2 given to the output terminal becomes low level VL2. At this time, the charges QC1 and QC2 stored on the node A side of the parasitic capacitances CC16 and CC210 are, respectively,

-Math 4- QC1=(VR-VH1)CC1 -Number 5- QC2=(VR-VL2)CC2 becomes.

Further, the charge QFD stored in the floating diffusion capacitor CFD4 is expressed by the following formula: -QFD=VR·CFD. Note that the potential of node A at this time is VR.

Next, at timing t2, the reset clock φR1 becomes low level VL1 and becomes non-conductive. Further, the clock φR2 becomes high level VH2. Note that the clock amplitude of the clock φR2 at this time is important, and its absolute value may be set as appropriate.The high level VH2 and low level VL2 of the clock φR2 are set to levels that do not cause the dummy transistor 9 to become conductive. shall be taken as a thing.

[0021]The potential VFD of node A at this dimming t2 is obtained from the relationship of the following equation,

00
22]

[Math 7]

When calculating the VFD by substituting Equations 4 to 6 into Equation 7, the following Equation 8 is obtained.

[0024]

[Math. 8]

Therefore, (VH1-VL1)CC1=(V
If the value of VH2-VL2 is adjusted so that H2-VL2) CC2, VFD=V even at timing t2.
R, and the leakage of the reset clock φR is eliminated. Preferably, if the reset transistor 5 and the dummy transistor are made to have the same shape, CC1=CC2, so that VH2-VL2=VH1-VL1, that is, the amplitude of the clock φR2 and the amplitude of the reset clock φR1 are the same. If this is done, clock leakage will disappear. Note that the process from timing t3 onwards is the same as the conventional process, so the explanation will be omitted.

In the charge transfer device of this embodiment as described above,
A dummy transistor 9 is connected in parallel to the reset transistor 5, and a clock φR2 having a polarity opposite to that of the reset clock φR1 applied to the gate of the reset transistor 5 is applied to the gate electrode of the dummy transistor 9, so that the clock φR2 By adjusting the value of VH2-VL2 of (VH1-VL1)CC1=(VH2-VL
2) When the CC2 relationship holds true, even when the reset clock φR1 is inverted to VL1, VFD=VR, and the potential charged to the node A, that is, the potential charged to the floating diffusion capacitor CFD4. As a result, reset clock leakage can be reduced.

In the above embodiment, (VH1-VL1)
Although the case where CC1=(VH2-VL2)CC2 is shown, since the purpose of the present invention is to reduce reset clock leakage, the amplitude of the clock applied to the gate of the dummy transistor 9 is set from the output terminal 8 onwards. It may be changed depending on the characteristics of the amplifier connected to the amplifier and the required S/N value. That is, (VH1-VL1)CC1≠(VH2
-VL2) Even in the case of CC2, as is clear from Equation 4 above, VFD is smaller than in the past, and reset clock leakage can be reduced.

Furthermore, in the above embodiment, the timings at which the logical values of φR1 and φR2 are inverted are the same, but they do not have to be exactly the same; for example, the pulse width, rising and falling characteristics of φR2 may vary depending on the clock. It is only necessary to adjust it to an optimal value that reduces the amount of friction.

Further, in the above embodiment, the drain of the dummy transistor 9 is connected to the power supply VR, but since the charge detection capacitor is not charged in the dummy transistor, the drain must be left open or the drain itself must not be provided. Good too.

Further, in the above embodiment, the case where the signal charge is an electron is considered, but it may also be a hole, and in this case, the polarity of the voltage is all reversed.

Furthermore, in the above embodiment, the capacitance between the dummy transistor 9 and the floating diffusion capacitor CFD4 is the parasitic capacitor CC210, but this may be an independent capacitor.

[0032]

As described above, according to the charge transfer device according to the present invention, a new transistor is connected in parallel to the reset transistor that controls the potential charged to the charge detection capacitor of the output section, and Since a clock pulse with a polarity opposite to that applied to the gate of the reset transistor is applied to the gates of the transistors connected in parallel, the charge detection capacitor (floating diffusion capacitor) is supplied with a clock pulse by the reset transistor. Even when the reset clock is reversed due to a potential fluctuation opposite to the potential fluctuation applied at the same time, the potential charged to the charge detection capacitor can be reduced to reduce reset clock leakage, and the S/N can be reduced. This has the effect of providing an improved charge transfer device.

Furthermore, according to the method for driving a charge transfer device according to the present invention, there is provided a charge detection capacitor, a charge transfer element that transfers a signal charge to the charge detection capacitor, and a reset that controls the potential charged to the charge detection capacitor. A new transistor is connected in parallel to the transistor, and at the same time a clock pulse is applied to the gate of the reset transistor,
A clock pulse having a polarity inverted from that of the clock pulse is applied to the gate of a transistor connected in parallel with the reset transistor to charge the charge detection capacitor to a constant potential, and then the charge transfer element is connected to the charge detection capacitor. Since the signal charge from the oscillator is transferred, the device can be driven without the reset clock leaking in, which causes noise, and the S/N ratio of the device can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an output section circuit of a charge transfer device according to an embodiment of the present invention and a timing chart of a clock in the circuit.

FIG. 2 is a diagram showing an output section circuit of a conventional charge transfer device and a timing chart of a clock in the circuit.

[Explanation of symbols]

1 Channel of charge transfer element 2 Clock gate 3 Output gate 4 Floating diffusion capacitance (charge detection capacitance) 5 Reset transistor 6 Parasitic capacitance 7 Buffer amplifier 8 Output terminal 9 Dummy transistor 10 Parasitic capacitance

Claims (2)

[Claims] 1. A charge transfer device comprising a charge detection capacitor, a charge transfer element that transfers a signal charge to the charge detection capacitor, and a reset transistor that controls a potential charged to the charge detection capacitor, wherein the reset A charge transfer device characterized in that a transistor is connected in parallel to which a clock pulse having a polarity inverted from that of the clock pulse applied to the reset transistor is applied. 2. A charge detection capacitor, a charge transfer element that transfers a signal charge to the charge detection capacitor, a reset transistor that controls a potential charged to the charge detection capacitor, and a transistor connected in parallel to the reset transistor. A method for driving a charge transfer device, which charges the charge detection capacitor to a constant potential and then transfers a signal charge from the charge transfer element to the charge detection capacitor, includes applying a clock pulse to the gate of the reset transistor. At the same time as the clock pulse is applied, a clock pulse having a polarity opposite to that of the clock pulse is applied to the gate of a transistor connected in parallel to the reset transistor, thereby charging the charge detection capacitor to a constant potential. driving method.