JPS594792B2 - MOS Gata Bucket Brigade Te - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention (co-MOS type packet brigade device)
Regarding BBD), the purpose is to maintain a wide dynamic range of the transfer signal by compensating for the leakage of bias charge during transfer due to leakage current.

In general, impurities of a conductivity type different from that of the substrate are formed in the form of islands on a MOS type BBD (copper or in type silicon substrate).
This is "0" which utilizes this as a charge storage layer.

When such a BBD is operated at high temperatures or with a low frequency clock, the leakage current through the bonding surface between the island-like charge storage layer and the silicon substrate increases, and a large amount of bias charge leaks into 05. This also resulted in a reduction in the dynamics of the transfer signal charge in the middle stage.

The present invention aims to eliminate these problems, and one embodiment thereof will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration of a BBD according to an embodiment of the present invention. In FIG.
05 transistors each having a plurality of sources and drains connected in cascade.

4ι'' 5n channel M05 transistor for leakage current compensation, 5 (1 clock pulse terminal for compensation), 6 (1- power supply terminal to which a constant power supply voltage is applied).

1 (input signal application terminal, 8 (power supply voltage application terminal, 9
(' output terminal, 10ι is a MOS transistor for output.

20 (') This is an internal signal stage point where the drain of the transfer transistor 3 and the source of the compensation transistor 4 are connected, and the leakage current is compensated for at this part.

The operation of this circuit will be explained using FIG.

5. FIGS. 2A to 2E show signal waveforms at various parts of the circuit in FIG. 1, and the numbers on the right of each figure indicate the waveforms at each point in FIG. 1.

Each of A and B indicates a two-phase clock with a duty of 25%, which is applied to terminals 1 and 2. C is a compensating clock pulse applied to the terminal 5, which has the same frequency as the two-phase clock pulses and appears exactly in the gap between the two-phase clock pulses. This is a necessary condition in order not to disturb the transmitted signal.
D (1 shows the transfer waveform at the signal stage section 21 before the internal signal stage point 20. Now, the transfer MO on both sides of the internal signal stage point 20
When a clock pulse of C is applied to the terminal 5 of the compensation transistor 4 when no clock pulse is applied to the S transistor 3, that is, when the MOS transistors 3 on both sides are in a shielded state, the potential of the transfer stage point 20 changes to the level of the clock pulse of C. Photovoltaic voltage is applied to a value obtained by subtracting the threshold voltage of MOS transistor 4 from the voltage value. In this way, since the internal signal stage point 20 remains at a constant voltage at constant time intervals, a certain amount of the transferred charge is raised without disturbing the transferred signal voltage, and the bias charge is supplemented. It will be done. By the way, in order to raise a certain amount of charge at the internal transfer stage point 20 (1. If the amplitude of the clock pulse applied to the terminal 5 is made higher than the voltage applied to the drain terminal 6, the MOS transistor 4 becomes conductive and the bias charge is increased. It can provide supplementary light.

That is, the present invention provides one set consisting of the first MOS transistor and a bucket capacitor connected between the gate and drain of the first MOS transistor, with the source of the first MOS transistor as an input and the drain as an output. In a device for transferring signal charges through the cascade-connected circuit using a two-phase clotter pulse applied to the gate of the first MOS transistor in which a large number of MOS transistors are connected in cascade, an arbitrary number of drain terminals of the first MOS transistor; The source of one second MOS transistor is connected to the drain terminal 6 of the second MOS transistor.
(J is connected to a constant power supply, and applies a clock pulse having the same frequency but out of phase with the two-phase clock pulse applied to the gate of the first MOS transistor to the gate terminal of the second MOS transistor, and 1
The threshold voltage of the MOS transistor and the second MOS transistor may be changed (1) The parasitic capacitance between the gate and source of the first MOS transistor and the second MOS transistor may be changed, or the gate of the first MOS transistor may be changed. By changing the pulse amplitude applied to the second MOS transistor and the pulse amplitude applied to the second MOS transistor,
Drain voltage of the first MOS transistor connected to the S transistor. is periodically set to a constant voltage at a constant time, and can compensate for a decrease in via charge due to leakage current in a MOS type bucket brigade device.

Therefore, the present invention can prevent the dynamic range from becoming narrower in the middle.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a MOS type bucket brigade device according to an embodiment of the present invention. FIGS. 2A to 2E are voltage waveform diagrams of various parts in FIG. 1. 1,
2... Transfer clock pulse application terminal, 3...
...Charge transfer MOS transistor, 4...
- Current compensation transistor, 5...Clock application terminal, 20...Internal signal stage point.

Claims (1)

[Claims] 1 A plurality of first MOS transistors are connected in cascade, a bucket capacitor is connected between the gate and drain of each of the first MOS transistors, and a two-phase first clock pulse is applied to the first MOS transistor. In addition, at least one of the first MOS transistors
The source of a second MOS transistor is connected to any one of the two drain terminals, and a second clock pulse having the same frequency as the two-phase first clock pulse but out of phase with the second clock pulse is applied to the gate of the second MOS transistor. MOS type, characterized in that bias charge is replenished by periodically raising an arbitrary drain voltage of the second MOS transistor to a certain amount of charge corresponding to the second clock pulse. Bucket brigade device.