JPH0460351B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a charge transfer device and a method for driving the same.

[Prior art]

As an example of the charge transfer device is shown in FIG. 1, a plurality of charge transfer gate electrodes 3 are continuously disposed on the surface of a semiconductor substrate 1 having an N-type buried diffusion layer 7 with an oxide film 2 interposed therebetween. -1,4-1,3-
By adding clock pulses (hereinafter simply referred to as clocks) φ ₁ and φ ₂ to 2 and 4-2, charges are transferred using charge transfer channels formed under these transfer gate electrodes 3 and 4. .

The transferred charges pass through a channel formed under the output gate electrode 5 to which a constant voltage V _OG is applied, and are transferred to an N-type charge detection diffusion region 9 (hereinafter referred to as diffusion region 9). A potential change in the diffusion region 9 due to the inflow of charges into the diffusion region 9 is detected by a source follower circuit comprising an output MOS transistor 11 and a resistor R _L 14, and is taken out from the V _OUT terminal 13 as an output voltage. Note that 6 is the gate electrode of the reset MOS transistor, and 1 is the gate electrode of the reset MOS transistor.
0 is an N-type drain diffusion region, and the transferred carriers are electrons.

Next, this normal operation will be explained using the time chart shown in FIG. 2 and the potential explanatory diagrams shown in FIGS. 3 a to 3 d. Note that FIG. 3a shows a schematic sectional view of the device, and FIG. 3b to d show potentials corresponding to FIG. 3a at _t1 , _t2 , and _t3, respectively.

At time _t1 , the reset pulse _φR attains the "H" level, setting the potential of the diffusion region 9 to _VOD . At time _t2 , φ _R becomes "L" level, and the diffusion region 9 becomes in a floating state. Clock φ ₁ at time t ₃
becomes “L” level, and the transfer gate electrode ₄ to which the clock φ1 immediately before the output gate electrode 5 is applied
The charges accumulated in the channel potential below -2 flow into the diffusion region 9 through the channel below the output gate electrode 5 to which a constant bias V _OG is applied. This inflow of charges causes the potential of the diffusion region 9 to change, and this potential change is used as a signal output.
Passes through a source follower circuit consisting of a MOS transistor 11 and a resistor 14, and outputs V _OUT as an output voltage.
It is taken out from the terminal 13.

Here, the period in which the signal voltage is stably output is the period shown by TH in FIG. 2. In the above normal operation, the signal output period TH is the clock φ ₁ , φ ₂
When driving at high speed, because it does not become longer than 1/2 period of
For example, at clock frequency φ ₁ = 10MHz,
In principle, the length of the signal output period TH is as short as 50 nsec. Moreover, in reality,
Since a time of 10 ns or more is required for the charge to flow into the diffusion region 9 from the channel under the final transfer gate electrode 3 to which the clock φ ₁ is applied, the signal output period TH is 40 ns or less. I get used to it. That is, the conventional charge transfer device has a drawback that it cannot be driven at a sufficiently high speed.

In order to eliminate this drawback, in normal high-speed driving, in order to lengthen the stable signal output period TH, the diffusion region 9 is placed in a floating state before the signal charge flows in, as shown in the timing chart of FIG. A method has been adopted in which the period during which this occurs is made as short as possible, and the diffusion region 9 is reset immediately before the signal charge flows into the diffusion region 9. This driving method will be explained with reference to the potential explanatory diagrams of FIGS. 5a to 5e. Note that FIG. 5a shows a schematic cross _- sectional view _{of the} device, and _FIG.
The potential corresponding to a in the figure is shown.

At time _t1A , the reset pulse _φR goes to the "H" level, setting the potential of the diffusion region 9 to _VOD . At time _t2A, the clock _φ1 goes to "L" level, and the diffusion region 9 becomes in a floating state.

At time _t3A , the clock _φ1 becomes "L", and charges flow into the diffusion region 9. Since the reset pulse φ _R is still at “L” level at time t _4A ,
Diffusion region 9 is not reset and continues to maintain the potential at time _t3A . However, the final transfer gate electrode 4-2 immediately before the output gate electrode 5 becomes “H” at time _t4A .
Change in level.

In this way, in this driving method, as can be seen from FIG. 4, the signal output period is TH ₁ and the second
The signal output period increases by ΔTH compared to the figure.

However, in this driving method, as _shown in _FIG .
At the timing of the change from level to "H" level, noise appears as shown surrounded by a dotted line. This noise is due to the coupling capacitance Co existing between the final transfer gate electrode 4-2 and the diffusion region 9, as shown in FIG. As described above, the conventional device has the disadvantage that if the reset timing is shifted to increase the signal output period, noise will be introduced in the middle of the signal output period, reducing the S/N ratio.

[Purpose of the invention]

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to make it possible to lengthen the signal output period without introducing noise during the signal output period, thereby reducing the S/N ratio of the signal. An object of the present invention is to provide a charge transfer device and a method for driving the same, which can be driven at a sufficiently high speed without any problems.

[Structure of the invention]

According to the present invention, a transfer gate electrode and an output gate electrode are provided on the surface of a semiconductor substrate with an insulating film interposed therebetween, and a charge detection region is arranged adjacent to at least directly below the output gate of the semiconductor substrate. a conductivity type region opposite to that of the semiconductor substrate, and wiring disposed to separate the transfer gate electrode immediately before the output gate and the other transfer gate electrodes;
A charge transfer device comprising a reset transistor whose source region is the conductivity type region opposite to that of the semiconductor substrate is controlled by applying a clock pulse to the transfer gate electrode immediately before the output gate electrode and to the other transfer gate electrodes. A clock pulse is provided to form a barrier potential in the semiconductor substrate for a longer period of time and to form a charge storage potential at a timing when a barrier potential is formed in the semiconductor substrate immediately below the transfer electrode two positions before the output gate electrode. Driving the charge transfer device by applying a reset pulse to the gate electrode of the reset transistor to make the reset transistor conductive within a period in which the charge storage potential is formed by the transfer gate electrode immediately before the output gate electrode. method is obtained.

[Description of Examples]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 6 is a schematic cross-sectional view for explaining one embodiment of the first invention together with a necessary circuit diagram, and the same references are used for the same components as the embodiment shown in FIG. 1. A symbol is attached.

In this embodiment, in the charge transfer device of the embodiment shown in FIG.
It is constructed by using separate wiring from 1 and 3-2.

FIG. 7 shows a time chart of drive pulses and output signals in an embodiment of the second invention.

In this embodiment, the device according to the embodiment of the first invention shown in FIG.
The circuit is driven by applying a clock pulse φ _1L having a waveform and timing different from the clock pulses φ ₁ and φ _{2 applied to the clock pulses 3-2 and φ 2} .

Next, the operations of these embodiments are shown in FIGS. 8a to 8e.
This will be explained with reference to the potential explanatory diagram. Note that FIG. 8a is a schematic cross-sectional view of the device, and FIGS. 8b to 8e are
The potentials corresponding to a in the figure at t _1B , t _2B , t _3B , and t _4B are shown, respectively.

At time t _1B , reset pulse φ _R is set to “H”
level and reset the diffusion region 9. time
At _t2B , the reset pulse _φR is set to the "L" level, and the diffusion region 9 is placed in a floating state. At time _t3B , the clock _φ1L is set to the "L" level, and the charges accumulated under the transfer gate electrode 4-2' are transferred to the diffusion region 9. At this time, clocks φ ₁ and φ ₂ are the time
The state is the same as that at t _2B , and as shown in _{FIG .} remains stored in.

At time t _4B, clock φ ₁ goes to “L” level, and φ ₂
becomes "H" level, and as shown in FIG. 8e and _t4B , the charge moves from the channel potential below the gate to which clock _φ1 is applied to the channel potential below the gate to which clock _φ2 is applied. What should be noted here is that the transfer gate 4 to which the clock φ _1L is applied
-2' changes to "L" level at time t _3B and remains at "L" level at t _4B . Therefore,
Since the clock φ _1L does not change even at the change point of the clocks φ ₁ and φ ₂ between times t _3B and t _4B , the signal output period TH ₂ as shown in FIG. When φ ₁ and φ ₂ change, noise (see FIG. 4) does not occur. Furthermore, even if it occurs, it is due to the coupling capacitance between the transfer gate electrode 3-2 and the diffusion region 9 shown in FIG.
This capacitance is between the transfer gate electrode 4-2' and the diffusion capacitance 9.
Since it is very small compared to the coupling capacitance C _p between the capacitor and the capacitor C p , the amount of noise introduced is negligible. In other words, it can be said that the transfer gate electrode 4-2 shields the diffusion region 9 from noise coming from the transfer gate electrode 3-2.

As described above, by using the charge transfer device having the structure of this embodiment and its driving method, it is possible to lengthen the signal output period without reducing the S/N ratio of the signal.

Although the above description has been made with respect to buried channels, it goes without saying that the present invention can also be applied to charge transfer devices in which part or all of the device is a surface channel. Furthermore, although the description has been made using two-phase drive, it goes without saying that this can also be applied to three-phase, four-phase, or single-phase drive charge transfer devices.

Further, the semiconductor substrate is not limited to the P type, but may of course be an N type semiconductor substrate by reversing the polarity of the conductivity type and reversing the positive and negative potentials.

〔Effect of the invention〕

As explained in detail above, according to the charge transfer device and the driving method thereof of the present invention, the wiring of the final transfer gate electrode immediately before the output gate electrode is separated from the wiring of other transfer gate electrodes, and the final transfer A clock pulse having a waveform and timing different from the clock pulses applied to other transfer gate electrodes is applied to the gate electrode, and the potential of the channel potential formed under the same electrode is kept the same during the signal output period. This eliminates the noise introduced by the level conversion of the clock pulse, which occurs when trying to lengthen the signal output period as in the past, and enables sufficiently high-speed operation without reducing the signal-to-noise ratio. Become.

[Brief explanation of the drawing]

Fig. 1 is a schematic cross-sectional view together with a necessary circuit diagram for explaining an example of a conventional charge transfer device, Fig. 2 is a time chart during normal operation of the device shown in Fig. 1, and Fig. Figures a to d are diagrams explaining the potential of each part of the apparatus in normal operation of the apparatus in Figure 1, Figure 4 is a time chart during operation when the signal output period is lengthened in the apparatus in Figure 1, and Figure 5
Figures a to e are diagrams for explaining the potential of each part of the apparatus during operation when the signal output period is lengthened in the apparatus of Figure 1, and Figure 6 is a schematic diagram for explaining one embodiment of the first invention. 7 is a time chart showing a driving method of an embodiment of the second invention, and FIG. 8 is a diagram showing the potential of each part of the device shown in FIG. 6 in that case. FIG. 1... P-type semiconductor substrate, 2... Oxide film, 3-
1, 3-2, 4-1, 4-2, 4-2'...Transfer gate electrode, 5...Output gate electrode, 6...Gate electrode for reset NOS transistor, 7...N
Type buried diffusion layer, 8... P-type semiconductor region, 9...
Diffusion region for N-type charge detection, 10...Reset
Drain diffusion region of MOS transistor, 11...
...Output MOS transistor, 12...Drain power supply terminal, 13...V _OUT terminal, 14...Resistor,
_φ1 , _φ2 , _φ1L ...Clock pulse, _φR ...Reset pulse.

Claims (1)

[Claims] 1. A transfer gate electrode and an output gate electrode provided on the surface of a semiconductor substrate with an insulating film interposed therebetween, and the semiconductor substrate arranged as a charge detection region at least adjacent to the output gate of the semiconductor substrate. is a conductivity type region opposite to that of the semiconductor substrate, a wiring disposed to separate the transfer gate electrode immediately before the output gate from the other transfer gate electrodes, and a conductivity type region opposite to the semiconductor substrate as a source region. A charge transfer device comprising a reset transistor is configured to form a barrier potential in the semiconductor substrate on the transfer gate electrode immediately before the output gate electrode for a period longer than a clock pulse applied to the other transfer gate electrodes, and A clock pulse for forming a charge storage potential is applied at the timing when a barrier potential is formed in the semiconductor substrate immediately below the transfer electrode two places before the output gate electrode, and the transfer gate electrode immediately before the output gate electrode A method for driving a charge transfer device, characterized in that a reset pulse is applied to the gate electrode of the reset transistor to make the reset transistor conductive during a period in which a charge storage potential is formed.