JPS59217297A - Testing device of storage circuit - Google Patents

Abstract

PURPOSE:To shorten a test time by adding the 1st and the 2nd shift registers, and taking a retest from a test pattern which is supplied at preceded (N-1) times if a fail occurs instead of taking a test from the start. CONSTITUTION:A shift register 5 is a serial-in parallel-out type N-stage shift register for storing a decision result (i), its input is connected to the output of a comparing circuit 4, and the decision result (i) of up-to-date N test patterns is stored. This decision result (i) is shifted with a clock signal (a). If a fail occurs, an OR circuit 62 generates an output with logic ''0'' and a retest indication signal (e) is generated to inhibit the supply of the clock signal (a) of a test pattern generator 1; and the generation of a test pattern (c) is stopped and a flip- flop 65 is set to logic ''1'' to restart a test. A shift pattern (d) is selected by a data selector 3, so the test is started at the N test patterns (f) right before the fail occurs.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a memory circuit testing device.

[Prior art]

A conventional memory circuit testing device includes a test pattern generator that generates a test pattern consisting of test data and expected value data when a test stop signal is not supplied, and a test pattern generator that generates a test pattern consisting of test data and expected value data, and a test pattern generator that generates a test pattern consisting of test data and expected value data. a comparison circuit that compares the test result output in response to the expected value data and outputs a judgment result; and a comparison circuit that stops generating the test pattern when the judgment result indicates a failure. and a test control circuit that generates a test stop signal for stopping the test of the memory circuit.

That is, the conventional memory circuit testing apparatus uses a test pattern generator and a comparison circuit when measuring parameters of the memory circuit (access time power supply voltage margin, etc.) using a test pattern generator.

When conducting a test, set the specified parameters (strobe pulse delay time, power supply voltage, etc.) in the memory circuit to be tested prior to the test, and apply the t1 test data included in the test pattern generated by the test pattern generator. The comparison circuit compares the test result from the storage circuit with the expected value data included in the test pattern and generates a judgment result. When the expected value data and the test result match, the judgment result indicating the bus is generated. In other cases, a determination result indicating failure is output.

Such a test of a memory circuit is performed by changing the above-mentioned parameters to find the value of the parameter that is the boundary point between a bus and a fail.

A memory circuit testing device using a conventional test pattern generator stops the generation of the test pattern and changes the parameters based on the judgment result from the comparator circuit indicating a failure when 7 fail occurs in the middle of sequentially generated test patterns. After that, the pattern generation is repeated from the beginning.

Therefore, if the number of patterns is Z and the number of patterns until the first failure is F, then F test patterns from 0 to (F-+) are repeated for each test, especially when the capacity is large. In testing memory circuits, this has the drawback of increasing testing time.

[Purpose of the invention]

An object of the present invention is to provide a memory circuit testing device that can shorten testing time.

That is, the purpose of the present invention is to add a shift register and a data selector to
It is an object of the present invention to provide a memory circuit testing device which eliminates the above-mentioned drawbacks by omitting the above pattern and shortens the testing time.

[Structure of the invention]

The memory circuit testing device of the present invention includes a test pattern generator that sequentially generates test patterns when an operation stop signal is not supplied, and a test pattern generator that shifts each time a shift pattern of N stages is supplied as a shift turn. When the retest instruction signal is not supplied, the test pattern is selected, and when the retest instruction signal is supplied, the shift pattern is selected, and the test data and expected value data are stored in the first 77 register to be stored. a data selector that outputs the test pattern consisting of; and a test result outputted in response to the test data supplied to the memory circuit to be tested and the expected value data, and a judgment result is output by comparing the test result and the expected value data. a second shift register having N stages and storing the determination result for each supply of the test pattern; and at least one of the N determination results supplied in parallel.
The retest instruction signal is generated when the retest instruction signal is generated, and the operation stop signal is generated when the retest instruction signal is generated, and the retest instruction signal is N.
and a test control circuit that generates a test stop signal for stopping the test of the memory circuit when the test occurs +1 times in succession.

That is, the memory circuit testing device of the present invention includes a test pattern generator, a first shift register, and when the test pattern generator is operating, selects output data from the test pattern generator and stops the test pattern generator. a data selector that selects the output data of the first shift register and outputs it as a test pattern; a comparison circuit that compares the test result with the expected value data included in the test data; a second shift register for storing determination results; and a test control circuit for generating an operation stop signal and a test stop signal for stopping the operation of the test pattern generator according to the contents of the second shift register. and the first shift register is configured to store a test pattern output.

That is, the memory circuit testing device of the present invention includes a test pattern generator, a first
Select one of the output data of the test turn generator and the output data of the first shift register according to the operating state of the test turn generator and the test turn generator and output it as a test turn. a data selector that stores the determination result; and a second shift register that stores the determination result.
a first logic circuit that controls the operation of the notch turn generator according to the contents of the second shift register;
and a second logic circuit that generates a test stop signal according to the contents of the shift register.

[Explanation of Examples]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The memory circuit testing apparatus shown in FIG. 1 includes a test turn generator I, a shift register 2, a data selector 3, a comparison circuit 4, a shift register 5, and a test control circuit 6.

The shift register 2 is a serial-in/serial-out type shift register consisting of N stages (N22) for storing test patterns.The input is output from the data selector 3 and is supplied with a non-test pattern f. The latest N turns are stored as shift pattern d.

This shift pattern i can be shifted by the clock signal a.

The data selector 3 selects either the shift pattern d or the test pattern C from the test pattern generator 1 depending on the presence or absence of the retest instruction signal and outputs it as the test pattern f.

The comparison circuit 6 compares the test result outputted from the storage circuit to be tested with the expected value data g included in the test pattern f, and if they match, that is, if it is a bus, logic "1" is output.
If it doesn't match, that is, if it fails, is it logical? I
O++ is output as the determination result i.

The shift register 5 is a serial/parallel output format N-stage shift register for storing the judgment result i, and its input is connected to the output of the comparator circuit 4. Stone determination result i is memorized. This determination result 1 is shifted by the clock signal a.

The test control circuit 6 includes an AND circuit 61 and an OR circuit 62.
, an AND circuit 63 , a frequency divider 64 , and a Noritsu flop 65 .

The input of the AND circuit 61 outputs logic "0" when even one of the N shift registers 5 fails. This output is supplied to the OR circuit 62 and is ORed with the fail prohibition signal j. When the output of the OR circuit 62 is logic "0", a retest instruction signal e is generated, and when the output is logic "1", the retest instruction signal e is not generated.

The logic circuit 63 receives a retest instruction signal e and a clock signal a.
is supplied, and the output of the h output sum circuit 62 is a logic
When it is '0', an operation stop signal is generated.

The frequency divider 64 is a 1/N frequency divider configured to start frequency division when the output of the OR circuit 62 becomes logic "0", that is, when the retest instruction signal e is generated. The Noritsubu flop 65 operates according to the clock signal a.When the retest instruction signal e is supplied and the output is also supplied from the divider 64, that is, the clock signal a is supplied N+1 times. At times, a test stop signal k is output when the retest instruction signal is continuously output.

Next, using the memory circuit testing apparatus shown in FIG. 1, a procedure for measuring parameters of a memory circuit to be tested and operations of each part will be explained.

■ Set appropriate values for the parameters of the memory circuit to be tested.

■ Initialize the registers in the test pattern generator l. Also, the contents of the flip-flop 65 are set to logic "1".

■ Start the test pattern generator l.

At this time, until the first N patterns are output, the fail prohibition signal j is set to logic PI I I+ to cause the data selector 3 to select the test pattern C even if a fail occurs. After that, the fail prohibition signal j is set to logic "0°".

■ When a fail occurs, the output of the OR circuit 62 becomes logic "0", a retest instruction signal e is generated, the supply of the clock signal a of the test pattern generator L is prohibited, and the generation operation of the test pattern C is stopped. do. At the same time, shift pattern d is selected by data selector 3. Furthermore, at the same time, the branching unit 64 starts branching and outputs a pulse to the flip-flop 65 after N patterns. This pulse sets the flip-flop 65 to logic "0",
A test stop signal k is output, inhibiting the generation of the clock signal a and stopping the test.

■ Change parameter values.

■ Set the flip-flop 65 to logic "1" and start the test again. Since the shift pattern d has been selected by the data selector 3, the test is started from the N test patterns f immediately before the failure. When N patterns are tested and all the results are buses, logic "0" is set in the flip-flop 65 and the test is stopped, as in (2). In this case, return to ■. When all N patterns are buses, the output of the AND circuit 61 is logic N I I
+, the clock signal a is input to the test pattern generator 1, the test pattern generator 1 starts operating, and the generated test pattern C is selected by the data selector 3 and output as the test pattern f.

■ After that, repeat ■ until the test pattern generator completes generation.

〔Effect of the invention〕

By adding the first shift register and the second shift register, the memory circuit testing device of the present invention can perform the test from the beginning when a failure occurs.
Since the test can be retested from the previously supplied test pattern, the test time can be reduced.

In other words, when the memory circuit testing device of the present invention fails in the middle of a test pattern, the test can be restarted from the previous N patterns, thereby omitting the previous patterns, thereby reducing the test time. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...''...Test pattern generator, 2,5...
...Shift register, 3...Data selector,
4... Comparison circuit, 6... Test control circuit, 61.63... AND circuit, 62...
・OR circuit, 64... Frequency divider, 65...
··flip flop. a...Clock signal, b...Operation stop signal, C...Test pattern, d...Shift pattern, e...Retest Instruction signal, f...
...Test pattern, g...Expected value data, h...Test result, i...Judgment result,
j...Fail prohibition signal, k...Test stop signal. Agent: Susumu Uchihara, patent attorney (,,,,,f
, :l.

Claims (1)

[Claims] A test pattern generator that sequentially generates test turns when an operation stop signal is not supplied; A first shift register selects the test pattern when the retest instruction signal is not supplied, selects the shift pattern when the retest instruction signal is supplied, and selects the shift pattern from the test data and the expected value data. a data selector that outputs the test pattern, and a comparison circuit that compares the test result output in response to the test data supplied to the storage circuit to be tested with the expected value data and outputs a determination result. , a second shift register having N stages and storing the determination result for each supply of the test pattern.At least one of the N determination results supplied in parallel indicates a fail. When the retest instruction signal is generated, the operation stop signal is generated when the retest instruction signal is generated, and the memory circuit is tested when the retest instruction signal is generated N+1 times in succession. A memory circuit testing device comprising: a test control circuit that generates a test stop signal for stopping the test.