JPS59211278A - Transfer gate - Google Patents
Transfer gateInfo
- Publication number
- JPS59211278A JPS59211278A JP58086123A JP8612383A JPS59211278A JP S59211278 A JPS59211278 A JP S59211278A JP 58086123 A JP58086123 A JP 58086123A JP 8612383 A JP8612383 A JP 8612383A JP S59211278 A JPS59211278 A JP S59211278A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- transfer gate
- drain
- signal line
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 238000009736 wetting Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 241000282376 Panthera tigris Species 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体集積回路装置内で用いられるトランス
ファゲートに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a transfer gate used in a semiconductor integrated circuit device.
従来例の構成とその問題点
トランスファゲートは、ハイインピーダンス状態を有す
る信号伝達素子であシ、従来は一般にＭＯＳ）ランジス
２１個よりなっている。Conventional Structure and Problems The transfer gate is a signal transmission element having a high impedance state, and conventionally consists of 21 MOS transistors.
第１図は従来のトランスファゲートを示した図であり、
第１図ａはトランスファゲート回路図、第１図すは半導
体基体中に形成された従来のトランスファゲートの構造
断面図であり、第１図Ｃは絶縁膜上に形成された半導体
薄膜中に形成されたトランスファゲートの構造断面図で
ある。尚、１はドレイン、２はゲート、３はソースであ
り、１０は半導体基体、１１は酸化膜、１２は半導体基
体１０と反対導電形の拡散層、１３は半導体薄膜又は金
属膜によるゲートであり、１４は半導体薄膜、１６は半
導体薄膜１４中に形成されたこれと反対導電形の拡散層
、１６は半導体薄膜又は金属膜によるゲートである。FIG. 1 is a diagram showing a conventional transfer gate.
Figure 1A is a transfer gate circuit diagram, Figure 1C is a cross-sectional view of the structure of a conventional transfer gate formed in a semiconductor substrate, and Figure 1C is a transfer gate formed in a semiconductor thin film formed on an insulating film. FIG. In addition, 1 is a drain, 2 is a gate, 3 is a source, 10 is a semiconductor substrate, 11 is an oxide film, 12 is a diffusion layer of the opposite conductivity type to the semiconductor substrate 10, and 13 is a gate made of a semiconductor thin film or a metal film. , 14 is a semiconductor thin film, 16 is a diffusion layer of the opposite conductivity type formed in the semiconductor thin film 14, and 16 is a gate made of a semiconductor thin film or a metal film.
トランスファゲートは、ハイインピーダンス状態を有す
ることから同一の信号線に複数の信号を選択的に出力す
る場合などに多く用いられる。このとき、例えばメモリ
のメモリセルとビット線のように、同一の信号線に極め
て多数のトランスファゲートが接続されることになる。Since the transfer gate has a high impedance state, it is often used when a plurality of signals are selectively output to the same signal line. At this time, an extremely large number of transfer gates are connected to the same signal line, such as a memory cell and a bit line of a memory.
さて、トランスファゲートは、普通第１図すに示すよう
な半導体基体中に形成されたものが用いられる。この場
合、信号線に接続されるドレイン１の半導体基体に対す
る浮遊容量が問題となる。Now, a transfer gate formed in a semiconductor substrate as shown in FIG. 1 is usually used. In this case, stray capacitance of the drain 1 connected to the signal line with respect to the semiconductor substrate becomes a problem.
なぜなら、先にも述べたように、同一の信号線に多数ノ
ドランスファゲートが接続され、個々のトラ／スフアゲ
ートのドレイン容量が無視しうるほどには小さく女＜、
その結果、信号線の浮遊容量が極めて大きくなるからで
ある。信号線の浮遊容量が大きくなれば信号伝達に時間
がかかり、従って動作速度が低下するのである０まだ、
消費電力も大きくなるのである０
トランスファゲートのドレイン１の容量は、はとんど拡
散層１２と半導体基体との間の接合容量である。このこ
とから、接合の面積を減らせば容量が減るということに
なる。This is because, as mentioned earlier, a large number of transfer gates are connected to the same signal line, and the drain capacitance of each tiger/sphere gate is so small that it can be ignored.
This is because as a result, the stray capacitance of the signal line becomes extremely large. If the stray capacitance of the signal line increases, it takes time for signal transmission, and therefore the operation speed decreases.
Power consumption also increases.0 The capacitance of the drain 1 of the transfer gate is essentially the junction capacitance between the diffusion layer 12 and the semiconductor substrate. This means that if the area of the junction is reduced, the capacitance will be reduced.
第１図Ｃは、接合面積を減らすため、半導体基体１０上
に酸化膜１１を介し７て形成された半導体薄膜１４中に
トランスファゲートを形成したものである。In FIG. 1C, a transfer gate is formed in a semiconductor thin film 14 formed on a semiconductor substrate 10 with an oxide film 11 interposed therebetween in order to reduce the junction area.
第１図Ｃに示し、たトランスファゲートは、確かに接合
面積が小さく、ドレイン容量が小さい０しかし、半導体
薄膜１４は、例えば多結晶シリコンのようにその結晶性
が悪い０このため、ドレイン々いしソースの濡れ電流が
多く、実際上半導体集積回路装置などで使用することは
不可能である。It is true that the transfer gate shown in FIG. The wetting current of the source is large, making it practically impossible to use it in semiconductor integrated circuit devices.
即ち、第１図に示し、た従来のトランスファゲートでは
、ドレイン容量が少女り、かつ濡れ電流のないトランス
ファゲートは実現できないのであるＯ発明の目的
従って本発明の目的は、ドレイン容量が少なくかつ濡れ
電流のないトランスファゲートを提供することである。That is, with the conventional transfer gate shown in FIG. 1, a transfer gate with low drain capacitance and no wetting current cannot be realized. The object of the present invention is to provide a current-free transfer gate.
発明の構成
本発明に係るトラ／スフアゲートは、半導体基体中に形
成されたＭＯＳトランジスタと、これと直列に接続され
、半導体基体上に絶縁膜を介し、て形成された半導体薄
膜中に形成されたＭＯＳ）ランジスタからなり、これら
２つのトランジスタのゲートが共通接続されている構成
を有するＯ実施例の説明
第２図に本発明に係るトランスファゲートの実施例を示
す。尚、第１図と同じ構成要素には同じ番号を付してあ
り、２０は半導体基体１０中に形成されたＭＯＳ）ラン
ジスタであり、２１は半導体基体１０上に絶縁膜１１を
介し、て形成された半導体薄膜１４中−に形成されたＭ
ＯＳ）ランジスタ、３１はドレイン、３３はソースであ
る。Structure of the Invention The tiger/sphere gate according to the present invention includes a MOS transistor formed in a semiconductor substrate, connected in series with the MOS transistor, and formed in a semiconductor thin film formed on the semiconductor substrate with an insulating film interposed therebetween. DESCRIPTION OF EMBODIMENT OF THE INVENTION FIG. 2 shows an embodiment of a transfer gate according to the present invention. Note that the same components as in FIG. M formed in the semiconductor thin film 14
OS) transistor, 31 is a drain, 33 is a source.
さて、第２図よりわかるように、本発明に係るトランス
フアゲ−）１ｄ、２つのＭＯＳ ）ランジスタ２０．２
１が直列に接続されており、ゲートが共通接続されてい
る０そして、ドレインはＭＯＳトラ／ジスタ２１側にあ
る０同一の信号線に複数の信号を選択的に出力する場合
、ＭＯＳ）ランラスタ２１側にあるドレイン３１が、信
号線に接続されることになる。このとき、その信号線に
発生する浮遊容量は、第１図Ｃに示し、たトランスファ
ゲートを用いた場合と同じく、第１図すに示したトラン
スファゲートを用いた場合より極めて小さい。しかも本
発明に係るトランスファゲートにおいては、ソース側に
半導体基体中に形成されたＭＯＳ）ランジスタ２０があ
るために、ドレイン３１とソース３３との間に発生する
濡れ電流は、第１図すに示したトランスファゲートと同
じく皆無である。Now, as can be seen from FIG. 2, the transfer game according to the present invention includes two MOS transistors 20.2 and 1d.
1 are connected in series, the gates are commonly connected 0, and the drain is on the MOS transistor/transistor 21 side 0 When multiple signals are selectively output to the same signal line, MOS) run raster 21 The drain 31 on the side will be connected to the signal line. At this time, the stray capacitance generated in the signal line is much smaller than when the transfer gate shown in FIG. 1C is used, as is the case when the transfer gate shown in FIG. 1C is used. Moreover, in the transfer gate according to the present invention, since there is a MOS transistor 20 formed in a semiconductor substrate on the source side, the wetting current generated between the drain 31 and the source 33 is reduced as shown in FIG. Just like with the transfer gate, there are none.
即ち、本発明に係るトランスファゲートは、ドレイン容
量が極めて小さく、濡れ電流がない良好なトラ／スフア
ゲートなのである。That is, the transfer gate according to the present invention is a good tiger/sphere gate with extremely small drain capacitance and no wetting current.
発明の効果
以上述べてきたように、本発明に係るトランスファゲー
トは、ドレイン容量を小さくせし、めかつ濡れ電流がな
い従来のトランスファゲートでは実現できない有効な効
果を有するものである。Effects of the Invention As described above, the transfer gate according to the present invention has effective effects that cannot be achieved with conventional transfer gates, which have a small drain capacitance and no wetting current.
第１図ａ、ｂ、Ｃは従来のトランスファゲートを示した
回路図ならびに構造断面図、第２図ａ。
ｂは本発明に係るトランスファゲートの実施例を示した
回路図ならびに構造断面図である。
２・・−・・・ゲート、２０・・−・・・半導体基体中
に形成されたＭＯＳ）ランジスタ、２１・・・・・・半
導体基体上に絶縁膜を介し、て形成された半導体薄膜中
に形成されたＭＯＳ）ランジスタ、３１・・・・・・ド
レイン、３３・・・・・・ソース。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
？
４１０
第２図Figures 1a, b, and c are circuit diagrams and structural cross-sectional views showing a conventional transfer gate, and Figure 2a is a cross-sectional view of the structure. b is a circuit diagram and a structural sectional view showing an embodiment of a transfer gate according to the present invention. 2...Gate, 20...MOS transistor formed in the semiconductor substrate, 21...In the semiconductor thin film formed on the semiconductor substrate with an insulating film interposed therebetween. (MOS formed in) transistor, 31... drain, 33... source. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure? 410 Figure 2
Claims (1)
、前記の半導体基体上に絶縁膜を介して形成された半導
体薄膜中に形成され、前記第１のＭＯＳ）ランジスタと
直列に接続され前記第１のＭＯＳ）ランジスタのゲート
が共通接続された第２のＭＯＳ ）ランジスタとを有す
るトランスファゲート。a first MOS) transistor formed in a semiconductor substrate; and a first MOS) transistor formed in a semiconductor thin film formed on the semiconductor substrate via an insulating film and connected in series with the first MOS) transistor. A transfer gate having a second MOS transistor whose gates are commonly connected; and a second MOS transistor whose gates are connected in common.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58086123A JPS59211278A (en) | 1983-05-16 | 1983-05-16 | Transfer gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58086123A JPS59211278A (en) | 1983-05-16 | 1983-05-16 | Transfer gate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59211278A true JPS59211278A (en) | 1984-11-30 |
Family
ID=13877922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58086123A Pending JPS59211278A (en) | 1983-05-16 | 1983-05-16 | Transfer gate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59211278A (en) |
-
1983
- 1983-05-16 JP JP58086123A patent/JPS59211278A/en active Pending
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