JPS6161438A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6161438A
JPS6161438A JP59182805A JP18280584A JPS6161438A JP S6161438 A JPS6161438 A JP S6161438A JP 59182805 A JP59182805 A JP 59182805A JP 18280584 A JP18280584 A JP 18280584A JP S6161438 A JPS6161438 A JP S6161438A
Authority
JP
Japan
Prior art keywords
transistor
shaped groove
integrated circuit
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59182805A
Other languages
Japanese (ja)
Inventor
Katsuichi Mimura
三村　勝一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59182805A priority Critical patent/JPS6161438A/en
Publication of JPS6161438A publication Critical patent/JPS6161438A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology

Abstract

PURPOSE:To augment the transistor driving capability without allowing a transistor to occupy a larger area by a method wherein a V-shaped groove is provided meeting the gate electrode at a right angle and shared among all the cells. CONSTITUTION:In the channel region of the MOS transistor constituting a basic cell in an element region, a V-shaped groove is provided to meet the gate electrode at a right angle. For example, when a plane (100) of silicon is exposed to etching by the water solution of KOH a V-shaped groove is creat ed with its sides forming an angle of 54.7 deg.. By using this method, a V-shaped groove meeting the gate metal at a right angle is provided after the formation of a field region in a MOS transistor manufacturing process. The gate width of a transistor may be thus increased by a factor 1/cos54.7 deg.=1.73 times at the maximum.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はＭＯＳ型半導体集積回路装置に係わシ特にマ
スメスライス型集積回路を構成するＮｆＯＳトランジス
タの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a MOS type semiconductor integrated circuit device, and particularly to the structure of an NfOS transistor constituting a mass-slice type integrated circuit.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

マスメスライス型集積回路の基本セルは第２図に示した
如く２個のＮチャネルトランジスタと２個のＰ−チャネ
ルトランジスタを構成要素としているのが普通である。The basic cell of a mass-sliced integrated circuit typically consists of two N-channel transistors and two P-channel transistors, as shown in FIG.

なお第２図２は２個のＮチャネルトランジスタの能動領
域境界すなわちいわゆるソース、ゲート、ドレイン領域
を示している。Note that FIG. 2 shows active region boundaries of two N-channel transistors, ie, so-called source, gate, and drain regions.

３は同じくＰ−チャネルとそれである。3 is also the P-channel.

マスメスライス型の半導体集積回路装置にあっては第２
図に示した基本セルを列状に並べその列をチャネル配４
１１ｆＪｉ域をはさんで何本も配列しておき配線パター
ンを形成することによって所望の電子回路を実現する。For mass-slice type semiconductor integrated circuit devices, the second
The basic cells shown in the figure are arranged in rows and the rows are arranged in channel layout 4.
A desired electronic circuit is realized by arranging a number of wires across the 11fJi area and forming a wiring pattern.

このときに第２図中のＮチャネル及びＰチャネルトラン
ジスタは配線パターンで作られた長い配線あるいは個数
の多い次段ゲートのトランジスタという重い負荷をドラ
イブしなければならない場合がある。その念めトランジ
スタのチャネル巾（ゲート４が能動領域２又は３で切υ
取られる長さ）は十分な大きさに作っておく要があるが
、そうするとチップ全体の集積度が低下してしまうこと
だなる。At this time, the N-channel and P-channel transistors shown in FIG. 2 may have to drive a heavy load such as a long wiring formed by a wiring pattern or a large number of next-stage gate transistors. The channel width of the transistor (gate 4 is cut in active region 2 or 3 υ
It is necessary to make the chip large enough (length), but doing so will reduce the overall integration density of the chip.

〔発明の目的〕[Purpose of the invention]

この発明は上述した従来技術の欠点、すなわちトランジ
スタのドライブ能力を大とするためにチャネル巾を大き
くすると集積度が落ちてしまうという欠点を改良するた
めになされたものである。The present invention was made in order to improve the above-mentioned drawback of the prior art, that is, increasing the channel width in order to increase the drive ability of a transistor results in a decrease in the degree of integration.

〔発明の概要〕[Summary of the invention]

集積度を落とさず、すなわちトランジスタの専有面積を
大きくせずに、　　トランジスタのドライブ能力を犬と
するためにセル列方向即ちゲート電極と直交方向にＶ字
型の溝を各セル共通に作ることにヨリ実質的にトランジ
スタのチャネル巾を大きくすることである。第２図に示
す様にＶ字型の蒋を作ることによりチャネル巾を大きく
している。In order to improve the drive ability of the transistor without reducing the degree of integration, that is, without increasing the area occupied by the transistor, we decided to create a common V-shaped groove in each cell in the direction of the cell column, that is, in the direction perpendicular to the gate electrode. This essentially means increasing the channel width of the transistor. As shown in FIG. 2, the channel width is increased by creating a V-shaped channel.

第２図の例ではＰ−チャネルトランジスタにのみ深さと
表面孔中の異なる７字溝を２つ作っであるカＮ　−ｆヤ
ネルトランジスタに作ることももちろん可能であるし、
ｉた２つと限る必要はない。In the example of FIG. 2, it is also possible to create two 7-shaped grooves with different depths and surface holes only in the P-channel transistor, but it is also possible to create them in the N-f Channel transistor.
There is no need to limit it to two.

〔発明の実施例〕[Embodiments of the invention]

周知の如＜　ＫＯＨ水溶液によ、９　（１００）面シリ
コンをエツチングすると５４．７°の側面をもつ７字溝
を作ることができる。ＭＯＳ）ランジスタ製造工程のフ
ィールド領域形成後にゲートメタルと直交する７字溝を
“第２図の如くに作ると本発明の構造を持ったトランジ
スタを作ることができる。７字溝を作ることによりトラ
ンジスタのゲート巾を最大１／ＣｘＢ５４．７°＝　１
．７３倍にすることができる。As is well known, when 9 (100) silicon is etched using a KOH aqueous solution, a 7-shaped groove with side faces of 54.7° can be created. After forming the field region in the transistor manufacturing process, a transistor with the structure of the present invention can be manufactured by creating a 7-shaped groove perpendicular to the gate metal as shown in Figure 2. Maximum gate width of 1/CxB54.7° = 1
．． It can be multiplied by 73 times.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の基本セルの平面図、（ｂ）は八
−に断面図、第２図は従来の基本セルの平面図を示した
ものである０図において１は基本セルの単位境界、２及
び３は２個のＮチャネル及びＰチャネルトランジスタの
能動領域境界、４はそれぞれのＭＯＳトランジスタのゲ
ート電極、５はフィールド領域（非能動領域）の素子分
離用の厚い酸化膜。 ６．７，８．９はＶ字型の溝の壁面、１０はシリコン基
板。FIG. 1(a) is a plan view of the basic cell of the present invention, FIG. 1(b) is a cross-sectional view of the basic cell of the present invention, and FIG. 2 is a plan view of a conventional basic cell. 2 and 3 are active region boundaries of two N-channel and P-channel transistors, 4 is a gate electrode of each MOS transistor, and 5 is a thick oxide film for element isolation in a field region (inactive region). 6.7 and 8.9 are the wall surfaces of V-shaped grooves, and 10 is a silicon substrate.

Claims (1)

【特許請求の範囲】[Claims] 　ＭＯＳ素子からなる基本セルを半導体基板上に複数個
配列して素子領域を形成すると共に、この素子領域を上
記基板上に複数個配列してなり、必要に応じた配線パタ
ーンの形成により所望の回路が実現されるマスメスライ
ス方式の半導体集積回路装置において、前記素子領域上
で使用されている基本セルを構成するＭＯＳトランジス
タのチャネル領域にゲート電極と直行方向に少くとも一
つのＶ字型の溝を設けたことを特徴とする半導体集積回
路装置。A plurality of basic cells consisting of MOS elements are arranged on a semiconductor substrate to form an element region, and a plurality of these element regions are arranged on the substrate, and a desired circuit is formed by forming wiring patterns as necessary. In a mass-to-slice type semiconductor integrated circuit device in which this is realized, at least one V-shaped groove is formed in the channel region of a MOS transistor constituting a basic cell used on the element region in a direction perpendicular to the gate electrode. A semiconductor integrated circuit device characterized in that:
JP59182805A 1984-09-03 1984-09-03 Semiconductor integrated circuit device Pending JPS6161438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59182805A JPS6161438A (en) 1984-09-03 1984-09-03 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59182805A JPS6161438A (en) 1984-09-03 1984-09-03 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6161438A true JPS6161438A (en) 1986-03-29

Family

ID=16124737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59182805A Pending JPS6161438A (en) 1984-09-03 1984-09-03 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6161438A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5717239A (en) * 1995-11-15 1998-02-10 Nec Corporation MOS transistor with large gate width
JP2007040917A (en) * 2005-08-05 2007-02-15 Kawaso Electric Industrial Co Ltd Method and device for measuring temperature

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5717239A (en) * 1995-11-15 1998-02-10 Nec Corporation MOS transistor with large gate width
JP2007040917A (en) * 2005-08-05 2007-02-15 Kawaso Electric Industrial Co Ltd Method and device for measuring temperature

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