JPH07183476A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To improve the driving ability of the title device without increasing the layout area and to enable easy setting of the channel width by forming at least one or more recessed part in a direction perpendicular to a channel longitudinal direction of a gate electrode. CONSTITUTION:An N-type MOS transistor is comprised of a gate electrode 101 and source/drain regions 102, 103. A cross section structure along the X-axis therein is a gate electrode 104 and source/drain regions 105, 106. Therein, a recessed part is formed immediately below the gate electrode 104 in a direction perpendicular to a channel longitudinal direction of the gate electrode 104. The recessed part is formed in contact with the source/drain regions 105, 106 or within the source/drain regions 105, 106. Therefore, the channel length does not change and remains as is, and the channel width along increase. The increase of the channel width has an effect of improving driving ability along without increasing the integration degree.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and manufacturing method of a MOS transistor in a semiconductor integrated device, and a basic cell structure of a master slice type semiconductor integrated device.

[0002]

2. Description of the Related Art A conventional MOS transistor structure in a semiconductor integrated device is such that the surface of a well region immediately below a gate electrode has a flat structure or a V-shaped groove as shown in FIGS. there were.

The prior art shown in FIG. 5 shows a general MOS transistor structure in which the well region surface immediately below the gate electrode has a flat cross-sectional structure. FIG. 5A shows an N-type MOS transistor from above, which includes a gate electrode 501 and a source / source.
It is composed of drain regions 502 and 503. Further, the channel length direction of the MOS transistor shown in FIG. 5A is represented by the X axis, and the channel width direction is represented by the Y axis. Figure 5
5B is a cross-sectional view in the X-axis direction of FIG. 5A, in which the source / drain regions 505 and 506 are formed in the well region 507 formed on the semiconductor substrate 512. A gate electrode 504 is formed via a gate oxide film 509. FIG. 5C shows a cross-sectional view in the Y-axis direction of FIG.
A gate oxide film 516 is formed on the well region 514 formed above.
A gate electrode 513 is formed via the. This Figure 5
In the prior art MOS transistor structure shown in FIG. 3, the surface of the well region immediately below the gate electrode has a flat cross-sectional structure in both the channel length direction and the channel width direction.

MOS in the semiconductor integrated device shown in FIG.
The structure of the transistor is disclosed in Japanese Patent Application Laid-Open No. 61-6 / 1986.
1 shows the MOS transistor structure shown in 1438. FIG. 6A shows an N-type MOS transistor from above, which includes a gate electrode 601 and a source electrode.
The drain / drain regions 602 and 603,
The channel length direction is represented by the X axis and the channel width direction is represented by the Y axis. FIG. 6B is a cross-sectional view in the X-axis direction of FIG. 6A, in which the source / drain region 60 is formed in the well region 607 formed on the semiconductor substrate 612.
5, 606 exist, and the gate oxide film 609 is used to obtain the gate.
The electrode 604 is configured. FIG.
It is a cross-sectional view in the Y-axis direction of (a),
In the well region 614 formed on the semiconductor substrate 619, a V-shaped groove is provided in the direction orthogonal to the gate electrode, and the gate electrode 613 is formed via the gate oxide film 616. The conventional MOS transistor structure shown in FIG.
The portion immediately below the gate electrode in the channel length direction (X axis) has a flat structure, and the portion immediately below the gate electrode in the channel width direction (Y axis) has a V-shaped groove. The V-shaped groove formed in the direction perpendicular to the gate electrode forms a V-shaped groove having a side surface of a maximum of 54.7 degrees when (100) plane silicon is etched with a KOH aqueous solution. It was

[0005]

However, in the above-mentioned conventional technique, when the drive capability of the MOS transistor is prioritized, the layout area of the MOS transistor increases and the integration degree of the semiconductor integrated device decreases. On the contrary, when the integration degree is prioritized, the layout area of the MOS transistor is made compact, so that there is a problem that the drive capability is reduced.

In the prior art MOS transistor structure shown in FIG. 5, the surface of the well region immediately below the gate electrode is flat in both the channel length direction (X axis) and the channel width direction (Y axis). It has a cross-sectional structure.
Therefore, the only way to improve the drive capability is to narrow the channel length or widen the channel width. Since the channel length is basically determined by the minimum design rule in the process, the channel width is widened by design. However, the increase of the channel width increases the layout area of the MOS transistor, and the degree of integration is unavoidable. Further, the M shown in Japanese Patent Laid-Open No. 61-61438 shown in FIG.
The OS transistor structure has a flat structure immediately below the gate electrode in the channel length direction (X axis) and a channel width direction (Y axis).
A V-shaped groove is formed just below the gate electrode. Therefore, compared with the MOS transistor structure shown in FIG. 5, the maximum layout is 1.73 times (1 / cos 54.7).
Although it is possible to form a wide channel width, the V-shaped side surfaces formed by the surface of the semiconductor substrate have different angles, and the cross-sectional shape is V-shaped and the side surface forming angle is fixed. Therefore, there is a problem that the channel width cannot be increased further.

Therefore, the present invention solves such a problem by improving the drive capability without increasing the layout area of the MOS transistor and easily setting the channel width regardless of the surface of the semiconductor substrate. An object of the present invention is to provide a semiconductor integrated device that can be used.

[0008]

According to another aspect of the present invention, there is provided a semiconductor integrated device in which a separated second conductivity type impurity diffusion layer of the same polarity and a separated second second conductivity type impurity diffusion layer are formed in a first conductivity type well region formed in a semiconductor substrate. In a semiconductor integrated device having a gate electrode formed on the surface of a first conductivity type well region between conductivity type impurity diffusion layers via a gate oxide film, a first conductivity type immediately below the gate electrode. At least one recess is formed on the surface of the well region in a direction orthogonal to the channel length direction of the gate electrode. Further, the first conductivity type transistor and the second conductivity type transistor having a polarity different from that of the first conductivity type transistor are provided, and a plurality of matrix-shaped transistors are arranged for the purpose of forming a predetermined function by changing wiring. In a semiconductor integrated device having a basic cell group and an input / output buffer cell group arranged around the basic cell group,
At least one recess is formed in the surface of the well region immediately below the gate electrode of the first conductivity type transistor in a direction orthogonal to the channel length direction of the gate electrode, and the gate of the second conductivity type transistor is formed. It is characterized in that no recess is formed on the surface of the well region immediately below the gate electrode.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a MOS transistor of the present invention.
In particular, it shows the structure of an N-type MOS transistor. FIG. 1A shows an N-type MOS transistor from above, which is composed of a gate electrode 101 and source / drain regions 102 and 103. This Figure 1
The cross-sectional structure of the X-axis in (a) is FIG. 1 (b).
FIG. 1B shows a gate electrode 104, source / drain regions 105 and 106, a P-type well region 107, a P-type stopper region 108, a gate oxide film 109, and an element isolation region 1.
10, an interlayer insulating film 111, and a semiconductor substrate 112. In the MOS transistor of the present invention, a recess is formed immediately below the gate electrode in a direction orthogonal to the channel length direction of the gate electrode. Therefore, the channel length direction of the MOS transistor is flat as in the conventional MOS transistor. It has a cross-sectional structure. FIG. 1C shows a cross-sectional structure of the Y-axis in FIG. 1A. Since a recess is formed in the orthogonal direction with the gate electrode immediately below the gate electrode, the pitch between the recesses ( The channel width is determined by the number of recesses) and the depth. The recess is formed by contacting the source / drain region,
Alternatively, it must be formed including the source / drain region. Further, the source / drain region is formed deeper than the bottom of the recess. From the above, since the recess is formed in the direction perpendicular to the gate electrode on the surface of the well region immediately below the gate electrode, the channel length is the same as that of the conventional MOS transistor and only the channel width is increased. Therefore, the MOS transistor of the present invention can increase the channel width by the pitch (the number of recesses) and the depth between the recesses as compared with the conventional MOS transistor shown in FIG. 5, thereby improving the driving capability of the MOS transistor. You can Although the recess of the N-type MOS transistor shown in FIG. 1 is formed with a space from the end of element isolation, the recess may be formed without the space. Further, regarding the conventional MOS transistor having the V-shaped groove shown in FIG. 6, the channel width may be increased by forming a recess on the V-shaped side surface.

FIG. 2 shows the structure of a P-type MOS transistor as the MOS transistor of the present invention. FIG. 2A shows a P-type MOS transistor from above, which is composed of a gate electrode 201 and source / drain regions 202 and 203. The sectional structure of the X axis in FIG. 2A is FIG. 2B. FIG. 2B shows the gate electrode 204, the source / drain regions 205 and 206, the N-type well region 207, the P-type stopper region 208, the gate oxide film 209, the element isolation region 210, and the interlayer insulation. It is composed of a film 211 and a semiconductor substrate 212. In the MOS transistor of the present invention, a recess is formed immediately below the gate electrode and in a direction orthogonal to the gate electrode.
Like the OS transistor, it has a flat sectional structure. FIG. 2C shows a cross-sectional structure of the Y-axis in FIG. 2A. Since the recess is formed in the orthogonal direction with the gate electrode immediately below the gate electrode, the pitch between the recesses ( The channel width is determined by the number of recesses) and the depth. Further, similar to the N-type MOS transistor shown in FIG.
It must be formed in contact with the source / drain region or within the source / drain region. Also,
The depth of the drain / srain region is formed deeper than the bottom of the recess. From the above, since the recess is formed in the direction perpendicular to the gate electrode on the surface of the well region immediately below the gate electrode, the channel length is the same as that of the conventional MOS transistor and only the channel width is increased. Therefore, the MOS transistor of the present invention has a larger channel width than the conventional MOS transistor shown in FIG. In the formation of the recess of the P-type MOS transistor shown in FIG. 2, the channel width increases when the recess is formed without placing a space from the end of element isolation. This is because the P-type stopper region is not in contact with the source / drain region of the N-type well region, so that the channel region can be formed on the side surface of the recess at the end of the element isolation region. Further, regarding the conventional MOS transistor having the V-shaped groove shown in FIG. 6, the channel width may be increased by forming a recess on the V-shaped side surface.

Next, a method of manufacturing the MOS transistor of the present invention will be described below. FIG. 3 shows a manufacturing process of an N-type MOS transistor as the MOS transistor of the present invention. In FIG. 3A, boron (B +) ions are implanted into the semiconductor substrate 303, and boron (B +) is deeply diffused into the silicon substrate by well drive-in to form a P-type well 302, and then the surface oxide film is completely etched. Remove by. Then, a slit-shaped recess is formed in a direction orthogonal to the gate electrode by a photo process and an etching process for forming a recess on the surface of the P-type well. The recess is formed in contact with the source / drain region or in a region including the inside of the source / drain region. In FIG. 3B, after removing the resist, the corners of the formed recess are rounded, so that the surface of the substrate is oxidized again, and the oxide film is removed by the post-oxidation etching process. This is because if the gate oxide film is formed while leaving the corners of the recess, the electric field concentrates on the corners of the recess and the gate oxide film is destroyed. After rounding the corners of the recess, the surface is oxidized to deposit the nitride film 304. Then, the nitride film 304 covering the MOS transistor formation region is etched by a photo process. After etching, a photo process and an ion implantation process are performed to remove the resist and form a P-type stopper region 307. FIG. 3C shows about 10 after the P-type stopper region 312 is formed.
The element isolation region 313 is formed by oxidation with a steam at 00 ° C. In FIG. 3D, after the element isolation region 319 is formed, the nitride film is removed and etching is performed to clean the surface of the semiconductor substrate. After that, a gate oxide film 316 is formed, polycrystalline silicon is deposited, and a gate electrode 315 is formed by etching. Then, at a position deeper than the bottom of the recess, phosphorus (P
+) Ions are implanted to form the source / drain regions, and the interlayer insulating film 320 is deposited on the semiconductor substrate.
The manufacturing method of the P-type MOS transistor is also the same.

FIG. 4 shows a basic cell of a master slice type semiconductor integrated device of the present invention, which is composed of a P-type MOS transistor region I and an N-type MOS transistor region II as shown in FIG. Has been done. Usually P type M
Β ratio between the OS transistor and the N-type MOS transistor (β
n / βp) is about 2 or more, and the driving capability of the P-type MOS transistor is lower than that of the N-type MOS transistor. In order to increase the driving capability of this P-type MOS transistor,
It is necessary to increase the channel width of the P-type MOS transistor. However, since the increase in the channel width of the P-type MOS transistor lowers the integration degree of the semiconductor integrated device, it is often designed to be almost the same as the channel width of the N-type MOS transistor. In this way, when the logic circuit is configured with almost the same channel width, the rise time (the output changes from Low to High) is compared with the fall time (the time when the output changes from High to Low) of the logic circuit.
(time to change to h) becomes very slow. Therefore, FIG.
As shown in FIG. 4A, a recess is formed immediately below each gate electrode in the P-type MOS transistor region I in a direction orthogonal to the channel direction of the gate electrode as shown in FIG. The drive capability of the MOS transistor can be improved. As a result, the fall time (the time when the output changes from High to Low) and the rise time (the time when the output changes from Low to High) of the logic circuit can be made almost the same speed, and the high-speed operation logic circuit is configured. it can. Further, the improvement of the driving capability of the P-type MOS transistor can be easily set by the pitch (number of recesses) and the depth between the recesses. The recess may be formed in both the P-type / N-type MOS transistors.

[0013]

According to the effects of the invention described above, the MOS
By forming the recess in the channel region of the transistor, the channel width of the MOS transistor is increased, so that the driving ability is improved without increasing the integration degree. Further, since the channel width is increased by forming the concave portion in the channel portion of the MOS transistor,
Pitch between recesses (number of recesses) regardless of the surface of the semiconductor substrate
With the depth, the channel width can be easily set. In particular, in the basic cell of the master slice type semiconductor integrated device, there is an effect that the driving capability of the P-type MOS transistor is improved and a high-speed operation logic circuit can be configured.

[Brief description of drawings]

FIG. 1 is a sectional view of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a MOS transistor according to a second embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of a MOS transistor according to the present invention.

FIG. 4 is a sectional view of a MOS transistor according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view of a MOS transistor according to a first example of the related art.

FIG. 6 is a sectional view of a MOS transistor according to a second example of the related art.

[Explanation of symbols]

101, 104, 113, 201, 204, 213, 3
15, 401, 402, 406, 407, 411, 50
1, 504, 513, 601, 604, 613 ... Gate electrodes 102, 103, 105, 106, 202, 203, 2
05, 206, 403, 404, 405, 408, 40
9, 410, 502, 503, 505, 506, 60
2, 603, 605, 606 ... Source / drain regions 107, 114, 207, 214, 302, 306, 3
11, 317, 412, 507, 514, 607, 61
4 ... Well regions 108, 115, 208, 215, 307, 312, 3
18, 413, 508, 515, 608, 615
..Stopper areas 109, 116, 209, 216, 316, 414, 5
09, 516, 609, 616 ... Gate oxide film 305, 310 ... Oxide film 110, 117, 210, 217, 313, 319, 4
15, 510, 517, 610, 617 ... Element isolation 111, 118, 211, 218, 320, 416, 5
11, 518, 611, 618 ... Interlayer insulating film 112, 119, 212, 219, 303, 308, 3
14, 321, 417, 512, 519, 612, 61
9 ... Semiconductor substrate 301 ... Resist 304, 309 ... Nitride film I region ... P-type MOS transistor II region ... N-type MOS transistor

Claims (3)

[Claims] 1. A first conductivity type well region between a separated second conductivity type impurity diffusion layer of the same polarity and the separated second conductivity type impurity diffusion layer in a first conductivity type well region formed in a semiconductor substrate. In a semiconductor integrated device having a gate electrode formed on its surface via a gate oxide film, a channel length direction of the gate electrode is formed on the surface of the first conductivity type well region immediately below the gate electrode. A semiconductor integrated device characterized in that at least one or more recesses are formed in a perpendicular direction. 2. The method of manufacturing a semiconductor integrated device according to claim 1, wherein a recess is formed in the surface of the first conductivity type well region immediately below the gate electrode in a direction perpendicular to the channel length direction of the gate electrode. A method of manufacturing a semiconductor integrated device, comprising: a photo step and an etching step for forming, an oxidizing step for rounding the corners of a recess, and an etching step for removing an oxide film formed by the oxidizing step. 3. A first conductivity type transistor and a second conductivity type transistor having a polarity different from that of the first conductivity type transistor and arranged in a matrix for the purpose of constituting a predetermined function by changing wiring. In a semiconductor integrated device having a plurality of basic cell groups and an input / output buffer cell group arranged around the basic cell group, a well region surface immediately below a gate electrode of the first conductivity type transistor is provided. At least 1 in the direction orthogonal to the channel length direction of the gate electrode
A semiconductor integrated device, wherein one or more recesses are formed and no recess is formed on the surface of the well region immediately below the gate electrode of the second conductivity type transistor.