JPS59208943A - Logical circuit - Google Patents

Abstract

PURPOSE:To attain various types of logical functions with a simple element constitution for formation of an LSI by deciding a logical function in response to the logical levels of four types of control signals after combining three electric switches consisting of complementary MOS transistors of the same form. CONSTITUTION:The 1st electric switch 11 consists of an N type MOS transistor TRN1 and a P type MOSTRP1. The 2nd electric switch 12 consists of an N type MOSTRN2 and a P type MOSTRP2. The 3rd electric switch 13 consists of N type MOSTRN3 and a P type MOSTRP3 respectively. A logical inverse signal generating means 14 consists of an N type MOSTRN4 and a P type MOSTRP4. One of control signals C1-C4 is transferred to a terminal 9 by input signals A and B, and the inverse signal of the control signal is delivered to a terminal 10. When the signals applied to the signals C1-C4 are changed in terms of time, a logical function can be changed in terms of time. Thus it is possible to constitute a dynamic logical gate.

Description

[Detailed Description of the Invention] The industrial field of application is a logic device called a semiconductor integrated circuit device (hereinafter referred to as LSI).
Logic circuits that can be used to implement

Conventional configurations and their problems When converting a logic device composed of random logic into an LSI, it may be developed and designed with a TMI custom LSI such as a gate array, or it may be developed as a custom LSI, depending on the scale of the logic device. Especially when the logic device is developed and designed as a custom LSI, the scale of the logic device is quite large and mass production is required.

As a means of designing a custom LSi, 1) Each logical function (logical sum, logical product, exclusive logical sum, etc.)
We will design a cell that can realize this.

2) Determine the placement of each cell.

3) Make electrical connections between each cell.

4) Check whether the driving capacity of each cell is satisfied with respect to the load capacity of each cell.

5) Check whether the mask pattern matches the logic diagram.

6) Check whether the Ma Sufu pattern violates the design rules.

A mask pattern is formed by following these procedures.

When designing cells that can realize each logic function, if you design the cells according to the drive capacity of the load capacitance, for example, you will need to design several types of NOR gates and several types of NAND gates, which is quite a large number. cells would have to be designed, which would require a considerable amount of effort. It's reed, just in case you make a logical mistake, reirfl the cell.
In this case, even if it is found during mask pattern inspection, correction work must be performed on all layers of the mask pattern, and if something is overlooked, L.
If you notice an error only after evaluating the SI prototype, you will have to replace it with a different cell, or else you will have to make corrections to all layers of the mask, reducing the development period. The current situation is that it is impossible to shorten the time.

Purpose of the Invention It is an object of the present invention to provide a logic circuit that can be used as a cell that can realize various logic functions with a simple element configuration when converting a logic device into an LSI.

Configuration of the Invention The logic circuit of the present invention includes: a first electrical switch that transfers one of a first control signal and a second control signal in response to a first input signal; a second control signal that transfers one of the third control signal and the fourth control signal in consideration of the
an electrical switch for controlling the first electrical switch in response to a second input signal;
, a third electrical switch for transferring one of the outputs of the second electrical switch, and a generating means for outputting an electrical signal complementary to the output of the third electrical switch; , gIJ2, and the logic (level) is determined according to the logic levels of the third and fourth control signals.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will now be described with reference to FIGS. 1 to 3. Figure 1 is a block diagram showing the basic configuration.
) (2) is the terminal for the first and second input signals, (3) (4
) (5) (6) are the first to fourth control signal terminals, (
7) (8) (9) are the first to third electrical switches (
]υ@(2), a*r/'i is the output terminal of the logical inversion signal generating means 0a.

Depending on the logic level of the input signal at the terminal (1), the first electrical switch υ transfers the control signal of one of the terminals (5) and (6) to the terminal (8) and target switch @
A control signal from one of terminals (3) and (4) is transferred to terminal (7) in response to terminal (1). A third electrical switch (3) is activated depending on the logic level of the input signal at terminal (2).
) transfers the control signal of one of terminals (7) and (8) to terminal (9). The logical inversion signal generating means QO is configured to output the inverted signal of the terminal (9) and the terminal 01.

In this way, p of the control signals at terminals (3), (4), (5), and (6) is determined by the input signals at terminals (1) and (2).
Since the output is logically inverted and output to terminal (10), 16 types of two-person logical operations can be performed according to the control signals given to terminals (3), (4), (5), and (6). .

FIG. 2 shows the specific configuration of FIG. 1. The first electrical switch 0υ consists of an N-type MO5l-transistor (Nl) and a P-type MO5 transistor (p+), and the second electrical switch (6) consists of an N-type MO5l-transistor (N2).
and a P-type MO5) transistor (Pl).
electrical switch (13 is an N-type MO8l-transistor (
N3) and a P-type MO5 transistor (P8).

Further, the logical inversion signal generating means 1.14) is an N-type MO5l
- transistor (N4) (!: P-type MO5l - transistor (P4)). The gates of transistors (N1), (N2), (P, ), and (Pl) are common, and the terminal ( 1), transistor (Pl), (N1
) are connected to the respective terminals (3 (4),
The trains of transistors (Pl) (Nl) are each commonly connected to the source of transistor (P3). The source p of the transistor (Pz) (N2) is connected to the terminals (5) and (6), respectively.
The drains of the transistors (Nx) and (Nx) are connected in common to the source of the transistor (N3). The gates of the transistors (P3) and CN3) are connected to the terminal (2) in common.
) connected to 1-transistor (P3) (1'+3)
No Doshin II:! i LnK connected to transistor I
P4) Connected to 'r-to' of (N4). The drains of the transistors (P4) (N,) are connected to each other and connected to the terminal (10), and the transistor (P4) glue
- source is connected to the T3 source, and the source of the transistor (N4) is connected to ground.

Table 1 below shows @1, the second input signals are A and B, and the first
~The fourth control signal is Ca □ C4, and the output signal of the terminal q0 is O. Figure 2 and Figure 1 show the 1 ethical function in Figure 2.
The operation will be explained using a table.

- Below below - Other white - Table 1 A control signal (C,.) that determines the logical function of the arithmetic circuit.

If Ct, C3, Ca) is (H, L, L, L) and 611, and the input signal A is 11L, then the transistor (Pυ(P2
)? i conducting state, transistor (Nl) (N2
) becomes non-conductive, so terminal (7) I becomes "H" and terminal (8) L becomes "1" L. Input signal B becomes "L".
Then, the transistor (pg) becomes conductive and the transistor (N3) becomes non-conductive, so the terminal (9) becomes 1.
i(+7. Therefore, the output signal (6) becomes the inverted signal of the terminal (9) and becomes "L". Therefore, (A, B,
0)=(L, L, L). Next, input signal B is 1゜H
“If so, the transistor (ps) will be in a non-conducting state and the transistor Ns will be in a conducting state, so the terminal (9) will be “L”.
// becomes.

Therefore, the output signal (0) becomes 1"H", and (A, B, 0
)=(L, H, H). Next, input signal A is 11H”
, when the input signal B is “L”, the transistor (Nl
) (N2) (P3) becomes conductive, and the transistor (
PI) (P2) (N3) become non-conductive. Therefore,
Terminal (9) #The control signal (C2) is transferred and the
Therefore, the output signal becomes o +411n#, and (
A, B, 0)=(H, L, H). Finally, when both input signals A and B are "H", the transistor (Nl
) (N2) (m) is conductive, transistor (Pυ
(P2) (Ps) becomes non-conductive and the control signal (C
4) is transferred to terminal (9). Output signal terminal (
Since it is an inverted signal of 9), it becomes 1゜H'', and (A, B,
0)=(H, H, Hl).

From the above 1, control (No. 8 Q, C2, Cs,
C4 power ball (C1, C2, Cs, C4) ” (H,
L, L, L), the output signal 80 for the input signals A and H is as follows.

If A=ゝゝL", B-ゝゝL", then 0-ゝIL''A-
If ゝゝL", B = ゝゝH" then 0 = ゝゝH "A2ゝH", if B = ゝゞL" then 0-ゝゝH "A-ゝゝH"
, B = 9H'', then 0 = ゝゝH''. Therefore, the output signal 0 generates the logical sum of the input signals A and H.

As is clear from the above description, the input signal A.

B causes control signals Cs, Q, to be applied to terminal (9).
One of C3 and C4 is transferred and its inverted signal is output to terminal OI. Therefore, I
The logic function of the logic circuit can be determined according to the signals applied to the IJ control signals C1, C2, Cs, and Cs.

Furthermore, when the signals given to the control signals CI, C2, Cs, and C4 are changed over time, the logic function can be changed over time, and a three-way logic gate can be constructed.

FIG. 3 shows a mask pattern diagram in which the logic circuit of FIG. 2 is made into cells as a mask pattern.

aQ is a contact window connecting the E layer and F layer, (lIQ is a metal wiring, 07) I is a gate electrode wiring, (to) is a P type diffusion layer, and 01 is an N type diffusion layer. Like symbols and hatchings represent the same thing. When a logic device [t is made into a semiconductor integrated circuit using the cell shown in FIG. 3,
Since the cells shown in FIG. 3 can be applied to any place where logical operations are performed on two-manpower signals, cells to be designed can be eliminated.

If you want to make the logical operation fixed, use terminals (3) and (4).
(5) (6) with metal wiring, Vdd or VssK
Since it can be obtained by properly connecting the pieces, gold J7-A
t″I!, the logic can be changed simply by history of the line mask pattern.

As described in the detailed description of the invention, according to the logic circuit of the present invention, when a logic device is implemented as a half-quadruple integrated circuit, various logic functions can be realized with one cell. 1) 2) The logic function of a logic circuit can be changed over time.

3) When a logic function is used in a fixed manner, the logic can be changed by simply changing the mask pattern of the metal wiring.

4) The number of cells to be designed during custom LSI development can be reduced.

[Brief Description of the Drawings] Figure 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the detailed structure of FIG. 1, and the third diagram is a mask pattern diagram of FIG. 2. A: first input signal, B: second input signal, G
...First control signal, C2...Second control signal, C
3...Third control signal, C4...Fourth control signal,
0...output signal, aQ...first electrical switch, (\
...Second electrical switch, (3)...Third electrical switch, (4)...Logical inversion signal generating means Fig. 1 Fig. 2 Fig. 3

Claims (1)

[Claims] 1. A first electrical switch that transfers one of a first control signal and a second control signal in response to a first input signal; 3rd control No. 48 and 4th control
a second electrical switch that transfers one of the control signals of the first and second electrical switches; and a third electrical switch that transfers one of the outputs of the first and second electrical switches in response to a second input signal. , generating means for outputting an electrical signal complementary to the output of the third electrical switch, and a logic function is provided according to the logic levels of the first, second, eighth, and fourth control signals. A logic circuit characterized by determining. 2. Each of the first to third electrical switches is N9M.
A generating means for generating an electrical signal complementary to the output of the eighth electrical switch is configured by using an 0S transistor and a P-type MO5) transistor to have a common gate, a common drain, and an independent source terminal. , complementary MOS
2. The logic circuit according to claim 1, wherein the logic circuit is constituted by an inverter.