JPH06224739A - Gate circuit - Google Patents

Abstract

PURPOSE:To obtain the gate circuits whose characteristic such as a delay time between each input terminal and its output is arranged. CONSTITUTION:The gate circuit is provided with P-channel MOS transistors(TRs) 1, 2 connected in parallel, N-channel MOS TRs 3, 4 of series-connection connecting in series with the TRs 1, 2 connected in parallel, and N-channel MOS TRs 5, 6 of series connection connected in parallel with the TRs 3, 4 of series connection and whose gates receive different inputs A1, A2 from those of gates of the TRs 3, 4. Then a NAND gate circuit is formed by obtaining an X output from a connecting point between the parallel-connection TRs 1, 2 and the series connection TRs 3, 4 and 5, 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate circuit having a CMOS transistor structure used in digital circuits.

[0002]

2. Description of the Related Art Conventionally, a gate circuit having a CMOS transistor structure, for example, a NAND gate circuit represented by a logic symbol shown in FIG. 6A has a transistor circuit structure shown in FIG. 6B. There is. That is, the P-channel MOS transistors 1 and 2 connected in parallel, and the N-channel MOS transistors 3 and 4 connected in series to the P-channel MOS transistors 1 and 2 connected in parallel.
And the sources of the transistors 1 and 2 are the power supply,
The source of the transistor 4 is connected to the ground, the gates of the transistors 2 and 3 are connected to the input terminal 7 to which the A1 input is applied, and the gates of the transistors 1 and 4 are connected to the input terminal 8 to which the A2 input is applied. The X output is obtained at the output terminal 9 which is connected and led out from the connection portion between the parallel connection transistor group and the series connection transistor group.

The operation of the NAND gate circuit thus constructed will be briefly described below. When at least one of A1 and A2 inputs is at "L" level, the transistor 1
Or, at least one of 2 becomes ON,
At least one of the transistors 3 and 4 is OF
F Therefore, the "H" level is output from the X output. When both the A1 and A2 inputs are at "H" level, both transistors 1 and 2 are turned off and both transistors 3 and 4 are turned on, so that "L" level is output from the X output.

By the way, since the transistors 3 and 4 are connected in series, the source potential of the transistor 4 is always 0V, but the source potential of the transistor 3 is 0V when no current is flowing, but a current flows. 0 when you start
It doesn't become V. This is due to the voltage drop between the source and drain of the transistor 4. Since ON / OFF of the MSO transistor is determined by the potential difference between the source and the gate, when the transistor 4 is in the ON state, the transistor 3 changes from OFF to ON, or from ON to OFF, and The characteristics of the A1 and A2 inputs applied to the gate are different when the transistor 4 changes from OFF to ON or from ON to OFF in the ON state.

Description of gate circuits other than the NAND gate circuit is omitted, but similarly, the characteristics are different for each input terminal.

[0006]

In the conventional NAND gate circuit described above, the difference in characteristics between the A1 input and the A2 input appears as a difference in delay time. In recent years, the operating frequency of the circuit has become higher and higher, and this difference in delay time cannot be ignored. However, when actually designing a circuit, designing in consideration of this delay time further complicates the design, and the amount of data for simulation increases several times and takes time. .

The present invention has been made to solve the above problems in the conventional gate circuit, and an object of the present invention is to provide a gate circuit in which characteristics such as delay time from each input terminal to output are uniform. And

[0008]

In order to solve the above problems, the present invention provides a P or N-channel MO connected in parallel with their source electrodes connected to one power supply.
A gate circuit having a CMOS transistor structure, which has an S transistor group and an N- or P-channel MOS transistor group connected in series and having a source electrode of a transistor arranged at one end thereof connected to the other power source. , N- or P-channel MO having a structure similar to that of N- or P-channel MOS transistors connected in series
S transistor groups are connected in parallel by the number of transistors in series, and the gate connection is such that, for transistor groups connected in series with each other, different inputs are connected to each transistor, and the transistor groups connected in series are connected in parallel. Regarding the connected transistor group, different inputs are all connected to the gates of the respective transistors arranged at the end farthest from the other power source.

In the gate circuit configured as described above, since different inputs are connected to the respective transistors in the transistor groups connected in series with each other,
Operation as a gate circuit is ensured, and in a transistor group in which transistor groups connected in series are connected in parallel, all different inputs are connected to the gate of each transistor located at the end farthest from the other power supply. Since it is done, it becomes the same configuration for each input,
The characteristics of each input will be the same. Therefore, although there is an increase in the gate scale, it is effective for applications where characteristics are prioritized, and it is also useful for simplifying and speeding up simulation data.

[0010]

EXAMPLES Next, examples will be described. Figure 1 (B)
FIG. 1 is a circuit configuration diagram showing a first embodiment of a gate circuit according to the present invention. In this embodiment, the present invention is applied to a NAND gate circuit represented by a logic symbol shown in FIG. 1A, in which 1 and 2 are P-channel MOS transistors, 3, 4, and 5. 6 is an N-channel MOS transistor. The transistor 1 has a source as a power source, a drain as an output terminal 9 and transistors 2, 3, 5
Connected to each drain. Similarly transistor 2
The source of is connected to the power supply. The source of the transistor 3 is connected to the drain of the transistor 4, and the source of the transistor 4 is connected to the ground. Similarly, the source of the transistor 5 is connected to the drain of the transistor 6, and the source of the transistor 6 is connected to the ground. The gates of the transistors 1, 4 and 5 are A
It is connected to an input terminal 7 to which one input is applied, and each gate of the transistors 2, 3 and 6 is connected to an input terminal 8 to which an A2 input is applied.

Since the NAND gate circuit configured as described above is provided with the transistors 3 and 4 connected in series in parallel, the transistors 5 and 6 connected in series by changing the order of the input signals to the gates are provided. Transistors 3 and 6
Also, the transistors 4 and 5 perform ON and OFF operations in synchronism, so that the characteristics of both inputs A1 and A2 are the same. Further, the current driving capability also increases as a result of the series connection, which is a bottleneck, being parallelized.

Next, a second embodiment will be described. In this embodiment, NO represented by the logical symbol shown in FIG.
The present invention is applied to the R gate. As shown in FIG. 2B, the P-channel MOS transistors 13 and 14 are connected in series in parallel with the P-channel MOS transistors 11 and 12 connected in series. The circuit is added, and the same operation and effect as in the case of the NAND gate circuit shown in FIG. 1 are realized. In FIG. 2B, reference numerals 15 and 16 denote N-channel MOS transistors connected in parallel, and the series-connected transistors 11, 12 and 13, 14 connected in parallel.
Are connected in series to the circuit.

The present invention is not limited to the two-input gate circuit,
It is obvious that the same can be applied to the multi-input gate circuit. FIG. 3B is a diagram showing a circuit configuration when the present invention is applied to the 3-input NAND circuit represented by the logical symbol shown in FIG. In this case, in series with the N-channel MOS transistors 24, 25, 26 connected in series,
N-channel MOS transistors 27, 2 connected in series
8, 29 and N-channel MOS transistors 30, 31, 32
Insert additional. Then, to the gates of the transistors 32, 29 and 26 whose sources are connected to the ground, A
By connecting the input terminals to which the inputs A1, A2, and A3 are applied, it is possible to configure a three-input NAND circuit having uniform input characteristics. In addition, in FIG.
Reference numerals 21, 22, 23 denote P-channel MOS transistors connected in parallel, and the series-connected transistors connected in parallel.
It is connected in series to the circuit consisting of 24, 25, 26, 27, 28, 29 and 30, 31, 32.

Further, the present invention can be applied to a composite gate circuit, and as an example of the structure, the circuit structure in the case where the present invention is applied to the composite gate circuit represented by the logic symbol shown in FIG. Is shown in FIG. For reference, FIG. 5 shows a conventional circuit configuration of the composite gate circuit shown in FIG. As shown in FIG. 4B, this composite gate circuit is connected in series with the P-channel MOS transistors 41, 42, 43 connected in series, and the P-channel MO connected in series.
S-transistors 44, 45, 46 and P-channel MOS transistors 47, 48, 49 connected in series are additionally inserted. In addition, P-channel MOS transistors 51, 52 connected in series
P-channel MOS transistor connected in series in parallel with
Insert 53 and 54 additionally. Further, N-channel MOS transistors 61 and 62 connected in parallel and N-channel MOS transistors connected in parallel are connected.
N-channel MOS transistors 74, 75, 76 and 63, 64 in which only the series connection relationship is reversed in a circuit having a structure in which channel MOS transistors 71, 72, 73 are connected in series
Insert additional circuit consisting of. Then, by connecting the gates in the same manner as in the above-described embodiments as shown in the drawing, the characteristics of the A1, A2 inputs and the B1, B2, B3 inputs are made uniform, and the output drive capability is also increased. Is obtained.

As described above, in the case of many composite gate circuits, the P-channel MOS transistor side and the N-channel MOS transistor side, both having the same structure as the series connection part, are parallelized and additionally inserted to form the gate. By changing the connection, the same effect as that of each of the above embodiments can be obtained.

[0016]

As described above on the basis of the embodiments,
According to the present invention, although the circuit scale increases, it is possible to realize a gate circuit having uniform characteristics such as delay time from each input terminal to output. Therefore, the data amount of the simulation can be reduced, and more accurate simulation can be executed in a short time.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a logical symbol of a NAND gate circuit and a first embodiment of a gate circuit according to the present invention.

FIG. 2 is a logic symbol of a NOR gate circuit and a second aspect of the present invention.
It is a circuit block diagram which shows an Example.

FIG. 3 is a logic symbol and a third of a 3-input NAND gate circuit.
It is a circuit block diagram which shows an Example.

FIG. 4 is a circuit configuration diagram showing a logical symbol of a composite gate circuit and a fourth embodiment.

5 is a diagram showing a conventional circuit configuration example of the composite gate circuit shown in FIG.

FIG. 6 shows a logical symbol of a NAND gate circuit and a conventional NA.
It is a circuit block diagram which shows the structural example of an ND gate circuit.

[Explanation of symbols]

 1, 2 P-channel MOS transistor 3, 4, 5, 6 N-channel MOS transistor 7, 8 Input terminal 9 Output terminal

Claims (2)

[Claims] 1. A source electrode of a transistor which is connected in parallel with a P or N-channel MOS transistor group in which their source electrodes are connected to one power source and which is arranged in series at one end thereof. And a N- or P-channel MOS transistor group in which is connected to the other power source,
N or P-channel MOS transistor groups having the same structure as the N- or P-channel MOS transistor groups connected in series are connected in parallel by the number of series of the transistors, and the gate connections are connected in series. For the transistor group, connect different inputs to each transistor, and connect the transistor groups connected in series in parallel to the gate of each transistor located at the end farthest from the other power supply. A gate circuit characterized by being configured so that all different inputs are connected. 2. A group of P or N-channel MOS transistors connected in parallel and series with one end connected to one power source, and an N or P-channel connected in series and parallel with one end connected to the other power source. In a composite gate circuit having a CMOS transistor configuration having a MOS transistor group, the transistor groups connected in parallel are fixed blocks, and the serial connection groups having the same structure as the series connection group of the blocks are provided by the number of series of blocks. Connect in parallel, gate connections connect all different inputs for blocks that are connected in series with each other, and for parallel connections,
A composite gate circuit characterized in that all different inputs are connected to a block arranged at an end farthest from the other power supply.