JPS615623A - Multivalued logical circuit - Google Patents

Abstract

PURPOSE:To form an inverter logical circuit, NAND circuit, NOR circuit, etc., by combining a depletion type MOSFET and plural enhancement type MOSFETs having a different threshold voltages. CONSTITUTION:When an input terminal (x) is logical value 0, FETs Q33-Q35 are off, so an output of logical value 3 appears at an output terminal U. Then, when the terminal (x) rises in logical value 1, the FET Q33 which operates with the 1st threshold value turns on and a current flows from an FET Q11 through an FET Q31, so an output of logical value 2 is obtained. Further, when logical value 2 is obtained at the terminal (x), the FET Q34 which operates with the 2nd threshold value turns on as well and a current flows from the FET Q11 through an FET Q32, so the logical value 1 is obtained. Furtermore, when logical value 3 is obtained at the terminal (x), the FET Q35 also turns on and the logical value 0 is obtained. Thus, a four-valued inverter logical circuit is formed. This is used as a basic circuit to form a NAND circuit, NOR circuit, etc., similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is directed to NMOS (N-Channel MOS).
S) is used to create n-value inverter logic circuits, NAND circuits, and N.

The present invention relates to a multivalued logic circuit comprising an 8-circuit, a stable circuit, a delta literal circuit, a unary function circuit, and the like.

(Prior art) In LSIs, the integration density is becoming higher and higher due to the development of circuit technology and semiconductor manufacturing technology.As this higher integration progresses and the number of elements inside the LSI increases,
Wiring within a chip becomes more complex, and the area occupied by the wiring also increases. Incidentally, it is said that the wiring area of current LSIs accounts for as much as 70%, and this ratio is expected to further increase in the future as LSIs become more highly integrated.

Therefore, as a solution to this problem, research into multivalued logic circuits has become active in recent years.

In contrast to binary logic, which is the mainstream of current logic circuits,
Multivalued logic uses three or more logical values.

For example, in R-value logic, II Q II, II I
N. Old...

A logical value ``R-1'' exists. Compared to binary logic circuits, multi-level logic circuits: ■ have a larger amount of information per signal line, so the number of wires can be reduced, and ■ can increase the integration density of elements within a chip. There are two major advantages: In order to realize multivalued logic with such great advantages, CCD
(Charged Coupie Device)
, CM OS (eoIllplementary M
OS Device), ECL (Emitter)
Couple Logic), I”L (Integra
Applications of various devices such as ted injection logi'c) are being considered.

[Problem that the invention seeks to solve]

In conventional multivalued logic circuits, the number of elements increases and the pattern structure becomes complicated, which makes it difficult to correspond between the pattern and the circuit configuration, and also has problems such as increased power consumption. Furthermore, there was also a problem with reliability because levels indicating logical values were not propagated accurately. The present invention is based on the above considerations, and aims to provide a multivalued logic circuit with a reduced number of elements and a simplified pattern structure.

[Means for solving problems]

For this reason, uninvented multi-level logic circuits are basically circuits that combine one type of depression type MOS transistor and multiple types of enhancement type MOS transistors with different threshold values, and are used as inverter logic circuits or NAN.
D circuit, NOR circuit, stability circuit, delta literal circuit,
It is characterized by configuring a unary function circuit or the like. The depression type MOS transistor has multiple types of enhancement type MOS transistors in which a power source is connected to the drain electrode, and the gate electrode and source electrode have different thresholds.
Commonly connected to the S transistor and the output terminal. The enhancement type MO5I-transistor has a gate electrode connected to an input terminal to determine the logical value of an input signal and is used as a switching element, and a drain electrode connected to the gate electrode and to the output terminal side, and a source electrode. is connected to the ground potential side to obtain an output voltage corresponding to a desired logical value. The enhancement type MOS transistor has a threshold value intermediate between each logic value level. For example, in four-valued logic,
The voltages corresponding to the logical values rOJ, rlJ, r2J, and "3" are respectively 0. 1. 2. 3 (V
i], then 0.5.1.5.
It has a threshold of 2.5 (V).

[Effect]

In an enhancement type MOS transistor for determining and switching the logical value of an input signal, for example, when a voltage with a logical value of "2" is applied to the gate electrode, the threshold value changes between 0.5 (V) and 1.5 (V). The elements with a threshold voltage of 2.5 (V) remain non-conductive. Furthermore, in an enhancement type MOS transistor for obtaining an output voltage corresponding to a desired logical value, the threshold value is, for example, 1.
5 (V), in a series circuit with a depression type MOS transistor connected to the power supply side, as will be explained later with reference to FIG.
The power supply voltage is divided by the transistor and the enhancement type MOS transistor, and a stable state is reached at an output voltage of approximately 2 [■], which is higher than the threshold value of 1.5 (V), and a logical value of "2" is output.

However, when multiple enhancement type MOS transistors with different threshold values are connected in parallel, priority is given to the enhancement type MOS transistor with the lowest threshold value.
The output voltage is determined by the transistor. That is, the logical value "1" becomes the output voltage. At this time. The enhancement type MO3l- transistor with a high threshold becomes non-conductive because the voltage becomes below the threshold. That is, when a plurality of enhancement type MOS transistors having different threshold values are connected in parallel to a depression type MOS transistor, priority is given.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention regarding an inverter logic circuit, FIG. 2 is a diagram explaining the operation of the inverter logic circuit shown in FIG. FIG. 4 is a diagram showing the configuration of one embodiment of the present invention regarding a NOR circuit, FIG. 5 is a diagram showing the configuration of one embodiment of the present invention regarding a stabilizing circuit, and FIG. 1 is a diagram showing the configuration of an embodiment of the present invention regarding a delta literal circuit and a unary function circuit; FIG.

In the figure, Q, 1 to Q are depressosidine type M
The OS transistors Q1 to Q1 are enhancement type MOS transistors, Sl to S3 are switches, and 1 to 4 are inserted portions of output circuits, respectively.

In FIG. 1, a power supply V0 is supplied to the drain electrode of a depletion type MOS transistor Q11, a gate electrode and a source electrode of the depletion type MOS transistor Q11 are connected to an output terminal U (X), and an enhancement type MOS transistor Q3 is connected to an output terminal U (X). Q, 2
Each drain electrode, gate electrode and enhancement type MOS transistor Q8. connected to the drain electrode of In addition, enhancement type MOS transistor Q38
, Q3□ each source electrode is an enhancement type MOS
Transistors Q, 3, Q3. are connected to each drain electrode.

and enhancement type MOS transistors Q3 to Q3. , each source electrode is connected to ground potential,
Each gate electrode is connected to input terminal X.

These connections result in logical values rOJ, rlJ, r2J,
When the r3J signal is applied to the input terminal X, the corresponding logical values r3J, r2J, rlJ, respectively.

A signal of "0" is obtained at the output terminal U(x). That is, 4
It constitutes a value inverter logic circuit.

Next, the operation will be explained. In order to operate as a four-value inverter logic circuit as described above, an enhancement type MO
S transistors Q3z and Q3. is an element that operates according to the second threshold value, and an enhancement type MOS transistor Q, and lI and Qff4 are elements that operate according to the second threshold value, and enhancement type MOS transistors Q and l.
, an element that operates according to the third threshold value is used. Here, the second threshold is an intermediate level between logical values "0" and "1", and the second threshold is an intermediate level between logical values "1" and "2". , the third threshold is at a level intermediate between logical values "2" and "3". Therefore, enhancement type MOS transistors Q141 to Q3
5 are logical values rlJ and r2J, respectively.

It switches in response to the input of "3",
This can be replaced with switches S1 to S3 as shown in Figure 2 (a).
) can be expressed as follows. Enhancement type MOS
Transistors Q34 and Q32 are for obtaining a desired output voltage, and depletion type MOS transistors Q1. and enhancement type MOS transistor Q3
Figure 2 (kll) shows the operation transition of 1 and Ql. Figure 2 (b1) shows the voltage of the power supply ■.
■], level of logical value “2” is 2CV), logical value “1”
Assuming that the level of is 1 [V] and the third and second thresholds are respectively 2.5.1 and 0.0°5 [V], the switch S
When all of I to S are off, the voltage at point A is 3 [V]
, when only switch Sl is on, point B 2
(V), when switches S1 and 82 are on, the stable point is 0 point 1 [■], and when all switches S1 to S3 are on, the stable point is near O(V) of point D, respectively. voltage level is obtained at the output terminal IJ(x). Note that the third and second thresholds are not necessarily 2.
5.1°0.0.5CV), but 3 to 2.
2-1.1-OCV).

Therefore, when the input terminal X has the logical value rOJ, all of the enhancement type MOS transistors Q, 3 to Q, S are non-conductive, so the output terminal 11(x) is supplied with the power supply V. The voltage remains unchanged, that is, an output with a logical value of "3" is obtained. Next, when the input terminal X becomes a logical value "1", the enhancement type MOS transistors Q and 3, which operate at the second threshold, become conductive. In this case, only the switch SL is turned on in FIG. 2 (al). In this state, the depletion type MOS transistor Q
Since the current of the power supply V0 flows from the power source V0 through the enhancement type MOS transistor Q3I that operates at the second threshold value, an output of logic value "2" is obtained at the output terminal U (x). Furthermore, when the input terminal X becomes a logical value "2", the enhancement type MOS operates at the second threshold
Transistor Qff4 also becomes conductive. In this case, the second
In the figure (al), the switches S1 and 32 are turned on. In this state, the depletion type MOS transistor Q11 is changed to the enhancement type MOS transistor Q3□ which operates at a second threshold value smaller than the second threshold value. Since the current of the power supply ■ flows through the output terminal υ(×), an output with a logic value of "1" is obtained.When the input terminal X becomes a logic value of "3", it operates at the third threshold. Enhancement type MOS transistor Ch
s is also conductive. In this case, all of the switches SI to S3 are turned on in FIG. 2fa). In this state, the output terminal U(x) and the ground potential are short-circuited by the switch S3, so that an output with a logical value of "0" is obtained. A truth table showing the correspondence between inputs and outputs as described above is shown in FIG.

NAND based on the above inverter logic circuit configuration
FIG. 3 shows an example of the circuit. In Figure 3, enhancement type Mo5) transistors Q311 and Q4I
A series circuit with the enhancement type MOS transistors Qa and Q corresponds to the switch Sl shown in FIG.

A series circuit with the enhancement type MOS transistors Q4° and
．． The series circuit in FIG. 2 (a1 corresponds to the switch S3 shown in FIG. For example, if the input terminal X has a logical value of "3" and the input terminal y has a logical value of "1",
Enhancement type MO controlled by input terminal
S transistors Q311 to Q,. are all conductive because the logic value is "3", but the enhancement type MOS transistors Q4. only becomes conductive. Therefore, in this case, it is the same as if only the switch S1 shown in FIG. 2 ia1 is turned on, and an output of logical value "2" is obtained at the output terminal 11(x). FIG. 3 fbl shows the correspondence between the logical values of the input terminals X and y and the logical value obtained from the output terminal υ(X).

Similarly, N
FIG. 4 shows an example of an OR circuit.

In FIG. 4, enhancement type MOS transistors Q46 and Q4. The parallel circuit with
.

Corresponding to each inch, enhancement type MOS transistor Q4. and Q4. The parallel circuit with +a1 corresponds to the switch S2 shown in FIG. 2, and is an enhancement type MOS transistor Q. and Q5. The parallel circuit corresponds to the switch shown in Figure 2 (a1).As is clear from the circuit configuration shown, the parallel circuit that conducts is connected to the higher level of the input terminals X and y. It is determined. For example, input terminal
2'', the enhancement type MOS transistors Q, 6 and Q4 . and Q6. have a logical value of "0" and therefore remain non-conductive, but the enhancement type MOS transistor Q a ? controlled by the input terminal y? Since 049 and Q5I have a logical value of "2", enhancement type MOS transistor Q4. and Q49 are electrically connected. Therefore, in this case, the situation is the same as that in FIG. 2 (a1 shown switches S1 and 82 are turned on, and the output terminal U(
1" output is obtained. FIG. 4 (bl) shows the correspondence between the logical values of the input terminals X and y and the logical value obtained from the output terminal U(χ).

FIG. 5 shows an example of a four-value stable circuit using two of the above NOR circuits. In FIG. 5, the respective circuits divided from the center to the left and right are the same as the circuits shown in FIG. 4. The input terminals y in the circuit shown in FIG. 4 are used as set terminals (S) and reset terminals (R) of this stabilizing circuit, and the input terminals X are alternately connected to the output terminals of the other party. Therefore, for example, if the set terminal S is set to the logical value "2" in FIG. The output is controlled to a logical value of "1", and this output value is supplied as an input to the circuit on the right side of the figure.

On the other hand, in the circuit on the right side of the diagram, the enhancement type MOS transistor Q63 becomes conductive due to the input of the logic value "1", and the output is controlled to the logic value "2" by the threshold of the enhancement type MOS transistor Qs4. is returned as input to .

In this way, the t output cursors Q and d are held at logical values of "2" and "1", respectively. The logical value output corresponding to the logical value of the terminal s1R is shown in FIG. As is clear from the above description, such a stable circuit can of course be similarly realized using the NAND circuit shown in FIG.

Further, FIG. 6 shows an example of a delta literal circuit and a unary function circuit realized using the above-mentioned circuit similarly constituted by a depletion type MOS transistor and an enhancement type MOS transistor. In FIG. 6, the circuits within the broken line frame have input voltages of 0 to 1, respectively.
1~2.2~3.When 3~4, the output voltage is logic "n"
(Power supply voltage V Dll> value, and in cases other than the above, the output voltage becomes logic "0"
This is a multivalued logic circuit equipped with a four-valued delta literal circuit having four output terminals, in which each gate electrode is commonly connected to the input terminal X, and each drain electrode is connected to the 0th to 2nd output terminals. Each source electrode is connected to ground potential
Three first enhancement type M'OS +- transistor group Q, t% Q, 4, Q77, ■1-2.2 with threshold voltage within the range of 1.1-2.2-3 The two first enhancement type MOS transistors Q? having threshold voltages within the range of ~3? 4. Two second electrodes connected in parallel to each drain electrode and each source electrode of Q7□
Enhancement type MOS transistor group Q73
,Q? b, ■ A third enhancement type MOS transistor Q7 whose drain electrode is connected to the third output terminal and whose source electrode is connected to ground potential! , ■ and each day 4
two fourth enhancement type MOS transistor groups ct7s whose electrodes are commonly connected to the input terminal - a drain electrode and a source electrode of an element (C; 1+5) each having a threshold voltage within the range of v, -2 to v, -1 among the fourth enhancement type MOS transistor group; ,V
A second enhancement type MOS transistor group (Q??) connected in parallel to the drain electrode and source electrode of the first enhancement type MOS transistor group (Q??) having a threshold voltage within the range of i-1 to V, Q76) is connected to the gate electrode and source electrode of the element Q711, which has a threshold voltage within the range of 2 to 3 of the fourth enhancement type MOS transistor group, and is connected to the third enhancement type MOS transistor group. connected to the gate electrode and source electrode of the type MOS transistor Qff9, and connected to the first
Of the enhancement type MOS transistor group, O~
The drain electrode and source electrode of the element Q q z having a threshold voltage within the range of 1 to 2 are connected to the train electrode and source of element Q74 of the enhancement type MOS transistor group having a threshold voltage within the range of 1 to 2. The gate electrode and the source electrode of the element Q7s of the second enhancement type MOS transistor group are connected in parallel to the
Enhancement type MOS transistor group Q? 2.Q
7 Q? 7 and the third enhancement type MOS transistor Q? 9 and the fourth enhancement type MOS described above.
Transistor group Q 7 S, Q,.

In the delta literal circuit, the input terminal
enhancement type MOS transistors Q6B to Q depending on whether the logical value is "0" to "3".
One of z is selectively made conductive. That is, when the input terminal X has a logical value of "0", the enhancement type MOS transistors Q7
Both Q and 8 are not conductive and are enhancement type MOS.
Transistors Q1, 3 and Q? & and Qt'+ become conductive.

Therefore, enhancement type MOS transistor Q6.
and Q. and Q7. is not conductive, but enhancement type MOS transistor Q611 is conductive. Next, when the input terminal X becomes 16 logical value "]", the enhancement type MO
S transistor Q, 2 conducts and becomes enhancement type M
Since OS transistor Ql becomes non-conductive, enhancement type MOS transistor Q6. becomes conductive and the enhancement type MOS transistor Q hs becomes non-conductive. Thereafter, the logic value of the input terminal
1. When Q1 and Q1 become conductive, the enhancement type MOS
Transistor Q. The conductive element changes from to Q□. For circuits with five or more values, use the depletion type MO shown in the figure.
S transistor Q19, Qt. , and enhancement type MOS transistors Q, 5 to Ql, the drain electrodes of enhancement type MOS transistors Q68 to Ql correspond to desired output potentials as output circuits 1 to 4. The unary function can be realized by connecting circuits that In other words, as shown in Figure 6 (b1), when obtaining an output potential of logic value "0", a short circuit is used; when obtaining an output potential of logic value "1", the drain electrode and gate electrode are connected in common. Connected 0-1
Enhancement type M with a threshold between (V)
When using an OS transistor circuit and obtaining an output potential with a logic value of "2", an enhancement type MOS transistor circuit with a threshold value between 1 and 2 [Y] with the drain electrode and gate electrode commonly connected is used. When an output potential of value "3" is obtained, it is released. In this case,
All circuitry associated with this (including delta literals) is no longer needed. With this configuration, the logic value of the output terminal can be arbitrarily set between "0" and "3" in 44 combinations for the logic value "0" to "3" of the input terminal X. be able to. Therefore, the output circuits 1 to 4 have, for example, logical values r3J, r2J.

A four-value inverter logic circuit can be created by using a circuit that obtains the output voltages of rlJ and rOJ. However, in the case of the inverter logic circuit, according to the present invention, the structure shown in FIG. 1 can be simplified rather than using a unary function circuit.

Note that in the explanations above, an example of a four-value logic circuit was shown, but
Of course, it goes without saying that all of these can be applied to any number of multivalued logic circuits, not just four.

[Effects of the Invention] As is clear from the above explanation, according to the present invention, a depletion type MOS transistor is connected to the power supply side,
By combining this with an enhancement-type MOS transistor that switches with a threshold value that matches the desired level of multi-value logic, and an enhancement-type MOS transistor that outputs a logic value at the desired level, priority is assigned and the output voltage is In order to make it possible to arbitrarily take out the data according to the priority order, a multivalued logic circuit can be constructed with a simple connection configuration and a small number of transistors. Therefore, it is possible to construct high-density, high-speed multi-value logic circuits, reduce power consumption in multi-value logic circuits, simplify pattern structures, and improve correspondence between patterns and circuit diagrams. It becomes easier.

In addition, by using diversion type MOS transistors and enhancement type MOS transistors, it becomes possible to accurately propagate levels (each voltage of n value), which improves reliability in multivalued logic circuits. In addition to improving the manufacturing technology, it is also possible to improve the
Since it is the same as a logic LSI, it is possible to coexist with binary logic circuits and develop and develop logic circuits based on the same ideas as binary logic circuits (a wide range of n-value logic circuits can be constructed). Further, according to the present invention, the systemization of multi-valued logic circuits has been developed, so it is possible to realize a system of multi-valued logic circuits.

[Brief explanation of the drawing]

1 is a diagram showing the configuration of one embodiment of the present invention regarding an inverter logic circuit, FIG. 2 is a diagram explaining the operation of the inverter logic circuit shown in FIG. 1, and FIG. 3 is a diagram showing the present invention regarding a NAND circuit. Figure 4 shows the configuration of one embodiment of NOR.
A diagram showing the configuration of an embodiment of the present invention regarding a circuit, FIG. 5 is a diagram showing the configuration of an embodiment of the present invention regarding a stabilizing circuit,
FIG. 6 is a diagram showing the configuration of one embodiment of the present invention regarding a delta literal circuit and a unary function circuit. Q or Q2□...depression type MOS transistor, Q3. or Ql, . . . enhancement type MOS transistor, SI or S, . . . switch, 1 to 4 . . . insertion part of output circuit. ) f11! l! dvd pu 4 tuto

Claims (6)

[Claims] (1) A depletion type MOS transistor whose drain electrode is connected to a power supply, each of which has a unique threshold voltage corresponding to a desired output voltage.
A group of (n-2) first enhancement type MOS transistors in which each drain electrode and each gate electrode are commonly connected to the gate electrode and source electrode of the OS transistor, and each gate electrode is connected to the output terminal, and each gate electrode is connected to the input terminal. V_1, V connected in common and each source electrode connected to ground potential
_2, ..., V_n_-_1 (|V_1|<|V_2|
<...<|V_n_-_1|) with a threshold voltage of (
n-1) second enhancement type MOS transistor group, and among the second enhancement type MOS transistor group, V_1, V_2, . . .
Each drain electrode of each enhancement type MOS transistor having a threshold voltage of V_n_-_2 is connected to each source electrode of the first enhancement type MOS transistor group, and the enhancement type MOS transistor having a threshold voltage of V_n_-_1 A multi-value logic circuit characterized in that the drain electrode of the transistor is connected to a common connection point between each drain electrode and each gate electrode of the first enhancement type MOS transistor group to constitute an n-value inverter logic circuit. (2) A depletion type MOS transistor whose drain electrode is connected to a power supply, each of which has a unique threshold voltage corresponding to a desired output voltage.
A group of (n-2) first enhancement type MOS transistors in which each drain electrode and each gate electrode are commonly connected to the gate electrode and source electrode of the OS transistor, and each gate electrode is connected to the output terminal, and each gate electrode is connected to the input terminal. Commonly connected V_1, V_2, ..., V_n_-_1 (|V_
(n-1) enhancement-type MOs having a threshold voltage of 1|<|V_2|<...<|V_n_-_1|)
It is constituted by a second enhancement type MOS transistor group in which m sets of S transistor groups are connected in series, and among the second enhancement type MOS transistor group,
Each drain electrode side of the series circuit of each enhancement type MOS transistor having a threshold voltage of V_1, V_2, ..., V_n_-_2 is connected to each source electrode of the first enhancement type MOS transistor group, and V_
Enhancement type M with a threshold voltage of n_-_1
The drain electrode side of the series circuit of OS transistors is connected to the common connection point between each drain electrode and each gate electrode of the first enhancement type MOS transistor group, and each source electrode side is connected to the ground potential, and the m input n value NAND
A multivalued logic circuit characterized by having a circuit configuration. (3) A depletion type MOS transistor whose drain electrode is connected to a power supply, each of which has a unique threshold voltage corresponding to a desired output voltage.
A group of (n-2) first enhancement type MOS transistors in which each drain electrode and each gate electrode are commonly connected to the gate electrode and source electrode of the OS transistor, and each gate electrode is connected to the output terminal, and each gate electrode is connected to the input terminal. Commonly connected V_1, V_2, ..., V_n_-_1 (|V_
(n-1) enhancement-type MOs having a threshold voltage of 1|<|V_2|<...<|V_n_-_1|)
It is constituted by a second enhancement type MOS transistor group in which m sets of S transistor groups are connected in parallel, and among the second enhancement type MOS transistor group,
Each drain electrode side of the parallel connection circuit of each enhancement type MOS transistor having a threshold voltage of V_1, V_2, ..., V_n_-_2 is connected to each source electrode of the first enhancement type MOS transistor group,
The drain electrode side of the parallel connection circuit of enhancement type MOS transistors having a threshold voltage of V_n_-_1 is connected to the common connection point of each drain electrode and each gate electrode of the first enhancement type MOS transistor group, and each A multi-value logic circuit characterized in that a source electrode side is connected to ground potential to form an m-input n-value NOR circuit. (4) A depletion type MOS transistor whose drain electrode is connected to a power supply, each of which has a unique threshold voltage corresponding to a desired output voltage.
A group of (n-2) first enhancement type MOS transistors in which each drain electrode and each gate electrode are commonly connected to the gate electrode and source electrode of the OS transistor, and each gate electrode is connected to the output terminal, and each gate electrode is connected to the input terminal. Commonly connected V_1, V_2, ..., V_n_-_1 (|V_
(n-1) enhancement-type MOs having a threshold voltage of 1|<|V_2|<...<|V_n_-_1|)
It is constituted by a second enhancement type MOS transistor group in which m sets of S transistor groups are connected in series or in parallel, and the threshold voltage of V_1, V_2, ..., V_n_-_2 of the second enhancement type MOS transistor group is Each drain electrode side of a series or parallel connection circuit of each enhancement type MOS transistor having The drain electrode side of the series or parallel connection circuit is connected to the common connection point of each drain electrode and each gate electrode of the first enhancement type MOS transistor group, and the source electrode side of the circuit is connected to ground potential. In addition to providing a circuit, the input and output of each of the two circuits are connected alternately, and each of the remaining circuits is connected alternately.
A multi-value logic circuit characterized in that an n-value stabilizing circuit is constructed by using input terminals as set (S) and reset (R) terminals. (5) Input voltage is 0 to V_1, V_1 to V_2, V respectively
_2~V_3,..., V_i_-_1~V_i,...
When V_n_-_1 to V_n, the output voltage is logic "n"
n having n output terminals from 0th to
A multivalued logic circuit comprising a value delta literal circuit,
Each gate electrode is commonly connected to the input terminal, each drain electrode is connected to the 0th to (n-2)th output terminal, and each source electrode is connected to the ground potential.
V_2, V_2~V_3, ..., V_i_-_1~V_
i, ..., a group of (n-1) first enhancement type MOS transistors having threshold voltages within the range of V_n_-_2 to V_n_-_1, V_1 to V_2, V_2
~V_3,...,V_i_-_1~V_i,...,V_
(n-2) first enhancement type MOs having threshold voltages within a range of n_-_2 to V_n_-_1;
A second enhancement type MOS transistor group of (n-2) pieces connected in parallel to each drain electrode and each source electrode of the S transistor group, the drain electrode being the (n-1)th
A third enhancement type MOS transistor is connected to the output terminal of the transistor and has its source electrode connected to ground potential, and each gate electrode is commonly connected to the input terminal and each source electrode is connected to ground potential, V_1 to V_2, V_2.
~V_3,...,V_i_-_1~V_i,...,V_
It includes (n-2) fourth enhancement type MOS transistor groups having threshold voltages within the range of n_-_2 to V_n_-_1, and each of the fourth enhancement type MOS transistor groups has V_i_-. ＿２
The drain electrode and source electrode of an element having a threshold voltage within the range of ~V_i_-_1 are set to V_i_-_1 ~V_i
a second enhancement-type MOS transistor connected in parallel to the drain electrode and source electrode of the elements of the first enhancement-type MOS transistor group having a threshold voltage within the range of
Drain electrodes and source electrodes of elements connected to the gate electrodes and source electrodes of the elements of the S transistor group and having threshold voltages within the range of V_n_-_2 to V_n_-_1 among the fourth enhancement type MOS transistor group; are connected to the gate electrode and source electrode of the third enhancement type MOS transistor, and the drain electrode and source electrode of the element having a threshold value within the range of 0 to V_1 among the first enhancement type MOS transistor group are connected to the gate electrode and source electrode of the third enhancement type MOS transistor. ,
The gate electrode and the source of the element of the second enhancement type MOS transistor group are connected in parallel to the drain electrode and source electrode of the element of the first enhancement type MOS transistor group having a threshold voltage within the range of V_1 to V_2. connected to the electrode, the first enhancement type M
OS transistor group and the third enhancement type M
OS transistor and the fourth enhancement type MO
A multivalued logic circuit characterized in that a delta literal circuit is configured by connecting a power source to each drain electrode of an S transistor group via a depletion type MOS transistor. (6) Connecting each of the 0th to (n-1)th output terminals of the delta literal circuit to each gate electrode of a group of (n-1) enhancement type MOS transistors whose source electrodes are connected to the ground electrode, and The enhancement type M
A unique threshold corresponding to a desired output voltage is connected between each drain electrode of the OS transistor group and the output terminal connected to the gate electrode and source electrode of a common depletion type MOS transistor whose drain electrode is connected to a power source. Claim No. 5, characterized in that a unary function circuit is constructed by connecting or disconnecting an enhancement type MOS transistor circuit or a short circuit having a value voltage.
) The multivalued logic circuit described in section 2.