JPH07177022A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the required number of wiring for every different potential by setting the threshold voltage of a differential pair of transistors on a high potential side lower than the threshold voltage of a differential pair of transistors on a low potential side. CONSTITUTION:Since this circuit is a two-input AND/NAND circuit, a signal A and a signal, the inverse of A are inputted to a differential pair S1, and a signal B and a signal, the inverse of B to a differential pair S2. In such a case, since the threshold voltage VTH1 is set smaller by a value equivalent to VDS (voltage between drain and source) required for FETs 7, 8 which form the differential pair S2 compared with the threshold voltage VTH2, no potential difference for the potential of the signals A, B (or the signals, the inverse of A, B) is required, and the input signal of same potential can be inputted. Consequently, when plural logic circuits are connected, it is not required to output signals with two kinds of potential as an output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a vertically stacked logic gate capable of high speed operation.

[0002] In recent years, as semiconductor fabrication technology has advanced and the degree of integration has improved, compound semiconductors having significantly higher speed and lower power consumption than conventional Si-ICs have been receiving attention. Then, a field-effect transistor (hereinafter referred to as FET (Field-Effect Transistor) manufactured by using this compound semiconductor.
nsistor). ) Has been developed in many integrated circuits.

[0003]

2. Description of the Related Art One of basic circuits used in integrated circuits composed of compound semiconductor FETs is SCFL (Source Coupling).
led FET Logic) circuit.

The SCFL circuit is an ECL which is a typical circuit among logic circuits using Si bipolar transistors.
(Emmiter Coupled Logic) This is a logic circuit with the same configuration as the circuit, and is a current switching type circuit.

The characteristic of the SCFL circuit is that it has a large number of elements and the number of elements per unit gate, resulting in a large power consumption, but on the other hand, it has a high speed.
Since complementary outputs such as OR-NOR are obtained, the flexibility of the logic circuit is increased. Further, when a flip-flop circuit is configured, it has a feature that its operating frequency is high, and after taking measures for lowering power consumption, small and medium-sized ICs (especially high speed) are required. For example, it is widely used in prescalers, multiplexers, demultiplexers, etc.).

Further, as another feature of the SCFL circuit,
It is possible to construct a vertically stacked logic gate, which makes it possible to construct various logic circuits. As an example of a logic circuit using a vertically stacked logic gate, a two-input AND configured by a conventional SCFL circuit using two stages of vertically stacked logic gates is shown in FIG.
/ NAND circuit is shown.

SCFL 2-input AND / N shown in FIG.
The AND circuit shifts the level of the output signal from the differential pair section 40 that generates a logical signal according to the input signal by the two differential pairs and the potential required for the output signal. It is composed of a level shift unit 50 for giving.

The differential pair section 40 prevents the logic high level signal (hereinafter referred to as H signal) output from the differential pair section 40 from being attenuated in the FET 51 or 52 in the level shift section 50. The diode 41, the load resistors 42 and 43 for determining the amplitudes of the H signal and the logical low level signal (hereinafter referred to as the L signal) output from the differential pair section 40, and the FET 44 forming the differential pair S3. And 45 and FETs 46 and 47 forming a differential pair S4,
It comprises a constant current source FET 48 constituting a constant current source and a feedback resistor 49 for stabilizing the output current value of the constant current source.

Here, the FETs 44, 45, 46 and 47
Are all FETs having the same threshold voltage (hereinafter referred to as V _TH ). The level shift unit 50
FETs 51 and 52 for amplifying the currents of the H signal and the L signal output from the differential pair section 40 and providing load driving capability
And diodes 53, 54, 55 for shifting the levels of the H and L signals output from the differential pair section 40.
And 56, and a constant current source FET 57 that constitutes a constant current source
And 59, and feedback resistors 58 and 60 for stabilizing the output current value of the constant current source.

Next, the operation will be described with reference to FIG. Since this circuit is a 2-input AND / NAND circuit, as shown in FIG. 3A, the A signal and the / A signal are input to the differential pair S3, and the B signal and the / B signal are input as input signals. It is input to the differential pair S4. Further, as the output signals, the X signal and the / X signal, and the Y signal and the / Y signal having a potential different from that of the X signal or the / X signal are output.

This output signal is output in the next-stage logic circuit when a plurality of logic circuits shown in FIG. 3A are connected.
Since input signals having different potentials are required, two kinds of output signals having different potentials are required.

V _DD and V _EE are previously applied as power supply voltages to the logic circuit shown in FIG. First, as an example, among the input signals shown in the truth table of FIG.
The operation when the H signal is input as both the A signal and the B signal will be described. Since the H signal is input as both the A signal and the B signal, the / A and / B signals are L
Signals are input together.

In the above case, since the H signal is inputted as the A signal, the FET 44 is brought into a conducting state (hereinafter referred to as an on state), and the H signal is inputted as the B signal, so that the FET 46 is also brought into the on state. Further, since the L signal is input as the / A signal, the FET 45 is in a cutoff state (hereinafter, referred to as an off state), and similarly, the FET 47 is also in an off state.

Therefore, the currents flowing through the differential pair S3 and the differential pair S4 are the diode 41, the load resistor 42 and the FET.
44, the FET 46 and the feedback resistor 49. Therefore, the potential at point c in FIG. 3 is lower than the potential at point d in FIG. 3 by the amount of the voltage drop in the load resistor 42. That is, as the output from the differential pair section 40 to the level shift section 50, the L signal is output to the gate terminal of the FET 51 in the level shift section 50, and the H signal is output to the gate terminal of the FET 52.

When the input potential of the gate terminal of the FET 52 shifts in the positive direction, the FET 59 for the constant current source and the feedback resistor 60.
FET5 to keep the current of the constant current source composed of
2, diode 55, diode 56, FE for constant current source
The potential at each connection point of the path including the T59 and the feedback resistor 60 also transits, and two types of H signals having different potentials are output as the X signal and the Y signal by shifting the level of one diode.

On the other hand, in the FET 51, on the contrary, since the input potential of the gate terminal makes a negative transition, the FET 51, the diode 53, the diode 54, and the FET 57 for the constant current source.
The potential of each connection point of the path including the feedback resistor 58 also transits in the negative direction, and two types of L signals having different potentials are output as the / X signal and the / Y signal by shifting the level of one diode. .

Even when another signal shown in the truth table of FIG. 3B is inputted as an input, the output signal shown in the truth table of FIG. 3B is obtained by the same operation as in the above example. Obtained,
This circuit operates as a 2-input AND / NAND logic circuit.

In addition to the 2-input AND / NAND logic circuit shown in this example, various logic circuits can be constructed by using vertically stacked logic gates, and a large scale can be obtained by combining these logic circuits. The integrated circuit can be speeded up. Further, since higher integration is required in the future, higher speed and lower power consumption than the present are desired.

[0019]

However, when a plurality of vertically stacked logic gates as described above are connected, an input signal having a different potential is required for each differential pair, so that the same timing is required. Even input signals that change from the H signal to the L signal (or vice versa) must be input at different potentials. Therefore, it is necessary to form a separate wiring for each input signal, and there is a problem that the wiring load increases and the delay time increases due to the increase in the wiring capacitance due to the increase in the wiring length.

This will be described with reference to FIGS. 3 and 4.
To do. That is, the 2-input AND / NAND of FIG.
In the logic circuit, saturate the FETs that make up each differential pair.
Stable operation in the range, and the current required for the differential pair section 40
In order to make it flow, the drain which is sufficient for the FETs forming each differential pair
Source-source voltage (hereinafter V_DSExpress. ) Need to give
There is. Therefore, the FET 44 forming the differential pair S3
The source potentials of 45 and 45 are the FETs forming the differential pair S4.
V more than the source potential of 46 and 47_DSTo a higher potential
There will be. Therefore, V of each FET _THAre all the same
Therefore, the potential of the input signal input to the differential pair S3 is
(Gate potential) is the voltage of the input signal input to the differential pair S4.
V from rank_DSShould only be high.

Therefore, in order to keep the potential of the input signal input to the differential pair S3 higher than the potential of the input signal input to the differential pair S4, the H signal changes to the L signal at the same timing ( Or even vice versa), separate wiring must be used. Then, when a plurality of logic circuits shown in FIG. 3 are connected, as shown in FIG. 4, it is necessary to lay an individual wiring for each differential pair in order to input an input signal to each differential pair. .

Therefore, since the total wiring length becomes long, the wiring capacitance increases, and the wiring load and the delay time increase. Here, as a method of shortening the entire wiring length, there is a method of using a level shift circuit. That is, when a plurality of logic circuits are connected and an input signal having a plurality of different potentials for one logic circuit is required, one output signal wiring of another logic circuit is branched from the middle. In this method, a level shift circuit is provided before the input signals having the different potentials are input to a necessary logic circuit to convert the potentials and then the potentials are input to the logic circuit. However, according to this method, an output signal having a plurality of types of potentials can be obtained from one type of output signal, but on the other hand, level shift circuits are required for the number of types of required potentials. There is a problem that the number increases and power consumption increases.

Therefore, an object of the present invention is to shorten the overall wiring length and increase the wiring load and delay without increasing the number of elements and the number of elements when a plurality of logic circuits having vertically stacked logic gates are connected. It is to provide a logic circuit which has reduced time and increased speed.

[0024]

In order to solve the above problems, the present invention provides a plurality of transistor differential pairs between a high potential side power supply (V _DD ) and a low potential side power supply (V _EE ). In a semiconductor integrated circuit device having a plurality of stages of vertically stacked logic gates formed by connecting in series, the threshold voltage (V _TH1 ) of the transistor differential pair (5, 6) on the high potential side is low. It is characterized in that it is set lower than the threshold voltage (V _TH2 ) of the transistor differential pair (7, 8) on the potential side (V _TH <V _TH2 ).

[0025]

In the present invention, the threshold voltage (V _TH1 ) of the high potential side transistor differential pair (5, 6) is the threshold voltage of the low potential side transistor differential pair (7, 8). (V _TH
2 ) is set lower (V _TH1 <V _TH2 ), the transistor differential pair (5, 6) on the high potential side can conduct at a lower gate potential, and therefore the potential of the input signal is low. Even if the potential is the same as that of the transistor differential pair (7, 8) on the side, each transistor can operate normally and exhibit a logical operation function.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to FIGS. FIG. 1 shows an example in which the vertically stacked logic gate of the present invention is applied to a SCFL 2-input AND / NAND circuit.

As shown in FIG. 1, in this embodiment, a differential pair section 1 for generating a logic signal according to an input signal by two differential pairs, and a level of an output signal from the differential pair section 1. And a level shift unit 20 for applying a necessary potential to the output signal.

The differential pair section 1 includes a diode 2 for preventing the H signal output from the differential pair section 1 from being attenuated in the FET 21 or 22 in the level shift section 20,
Load resistors 3 and 4 for determining the amplitudes of the H signal and the L signal output from the differential pair section 1, depletion type FETs 5 and 6 forming the differential pair S1, and enhancement forming the differential pair S2. Type FETs 7 and 8, a constant current source FET 9 forming a constant current source, and a feedback resistor 10 for stabilizing the output current value of the constant current source.

Here, V _TH (hereinafter, referred to as V _TH1 ) of the FETs 5 and 6 forming the differential pair S1 is V _TH (hereinafter, referred to as V _TH2 ) of the FETs 7 and 8 forming the differential pair S2. FETs 7 and 8 forming a differential pair S2, as compared with
Is set lower by a magnitude corresponding to V _DS required for the.

The level shift section 20 includes FETs 21 and 22 for providing load driving capability when the H signal and the L signal output from the differential pair section 1 change, and the H output from the differential pair section 1. Diodes 23, 24, 25 and 26 for shifting the levels of the signal and the L signal, constant current source FETs 27 and 29 forming a constant current source, and feedback for stabilizing the output current value of the constant current source. Resistors 28 and 30
It consists of and.

Next, the operation will be described with reference to FIG. Figure 1
The logic circuit shown in, as the power supply voltage, previously V _DD and V
It is assumed that _EE is applied.

Since this circuit is a 2-input AND / NAND circuit, as shown in FIG. 1, the A signal and the / A signal are input to the differential pair S1 as the input signals, and the B signal and the / B signal are input.
The signal is input to the differential pair S2.

Since V _TH1 is set lower than V _TH2 by a magnitude corresponding to V _DS required for the FETs 7 and 8 forming the differential pair S2, the A signal and the B signal (or The potentials of the / A signal and the / B signal do not need to have a potential difference as in the prior art, and an input signal having the same potential can be input. This is the FET
In general, the gate potential (hereinafter referred to as V _G ) required to flow a constant current changes depending on V _TH of the FET, and, for example, the lower V _TH is, the lower V _G is. Therefore, if the potential difference between V _TH1 and V _TH2 is set to a value equivalent to V _DS required for the FETs 7 and 8 forming the differential pair S2, and V _TH1 is set lower than V _TH2 , the differential voltage is set. FETs 5 and 6 required to flow a constant current through the pair S1
V _G in FIG. 2 may be as low as a potential corresponding to the V _DS required for FETs 7 and 8. Therefore, when V _TH1 and V _TH2 have the same value as in the conventional case, a potential difference corresponding to V _DS required for the FETs 7 and 8 is required for the A signal and the B signal (or / A signal and / B signal). However, according to the present embodiment, it is possible to input at the same potential.

As a result, when a plurality of logic circuits shown in this embodiment are connected, it is not necessary to output a signal having two kinds of potentials as an output signal, and an output signal having one kind of potential is branched on the way. Then, each of them may be input as the A signal and the B signal (or the / A signal and the / B signal) of the next logic circuit. Therefore, in the circuit shown in this embodiment, the X signal and / X signal as in the conventional example are unnecessary as output signals, and only the Y signal and / Y signal are output.

The reason why the Y signal and / Y signal are selected instead of the X signal and / X signal is that in the present embodiment, the V required for the FETs 5 and 6 is required for the differential pair S1 to function normally. _This is because it is necessary to give _DS .

Now, as an example, the operation when the H signals having the same potential are input as the A signal and the B signal among the input signals shown in the truth table of FIG. 1B will be described. Since the H signal is input as both the A signal and the B signal, the L signal having the same potential is also input as the / A and / B signals.

In the above case, the FET 5 is turned on because the H signal is input as the A signal, and the FET 7 is also turned on because the H signal is input as the B signal. Also, since the L signal is input as the / A signal, F
The ET6 is turned off, and the FET8 is also turned off.

Therefore, the paths of the currents flowing through the differential pair S1 and the differential pair S2 are the diode 2, the load resistor 3 and the FE.
The current flows through T5 and the FET 7 to the constant current source FET 9 and the feedback resistor 10. Therefore, the potential at point A in FIG. 1 is lower than the potential at point A in FIG. 1 by the amount of the voltage drop in the load resistor 3. That is, as the output from the differential pair section 1 to the level shift section 20, the L signal is output to the gate terminal of the FET 21 in the level shift section 20, and H signal is output.
The signal is output to the gate terminal of the FET 22.

When the input potential of only the FET 22 shifts in the positive direction, the FET 22, the diode 25, the diode 26,
The voltage is level-shifted in the circuit including the constant current source FET 29 and the feedback resistor 30, and the H signal is output as the Y signal.

On the other hand, since the gate input of the FET 21 makes a negative transition, the FET 21, the diode 23,
The level is shifted by a circuit including the diode 24, the constant current source 27, and the load resistor 28, and the L signal is output as the / Y signal.

Further, even when another signal shown in the truth table of FIG. 1B is inputted as an input, the output shown in the truth table of FIG. 1B is obtained by the same operation as in the above example. A signal is obtained and the circuit operates as a 2-input AND / NAND logic circuit.

When a plurality of 2-input AND / NAND logic circuits shown in this embodiment are connected, the output signal is Y.
Since there are only signals and / Y signals, as shown in FIG.
Since the wiring length is about half that of the conventional logic circuit, the wiring load and delay time can be reduced and the entire logic circuit can be sped up.

In this embodiment, the logic circuit using the vertically stacked logic gate having two transistor differential pairs has been described, but the same applies to the case where the transistor differential pair has three or more stages. is there.

That is, for example, the transistor differential pair is 3
In the case of the stage, the threshold voltage of the transistor differential pair on the highest potential side is V _TH3 , the threshold voltage of the transistor differential pair on the next highest potential side is V _TH4, and the threshold voltage is set to the lowest potential side. The threshold voltage of a certain transistor differential pair is set to V _TH5
Then, V _TH3 <V _TH4 <V _TH5 or V _TH3 = V _{TH 4}
By setting <V _TH5 or V _TH3 <V _TH4 = V _TH5 , one type or two types can be used for the potential of the input signal given to each transistor differential pair. The load and delay time can be reduced, and the entire logic circuit can be speeded up.

[0045]

As described above, according to the present invention,
Semiconductor integrated circuit device having vertically stacked logic gates
The threshold of the transistor differential pair on the high potential side
Voltage V _TH1However, the threshold of the transistor differential pair on the low potential side
Value voltage V_TH2Lower than (V_{TH 1}<V_TH2) Set
Therefore, each transistor differential pair of the vertically stacked logic gate is
The potential of the input signal applied to
Therefore, the number of wires required for each different potential
Can be reduced.

As a result, since the wiring length between the logic circuits can be shortened, the wiring load and delay time can be reduced and the speed of the entire circuit can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a logic circuit to which the present invention is applied.

FIG. 2 is a diagram showing a difference in wiring length between logic circuits according to a conventional technique and wiring length between logic circuits to which the present invention is applied.

FIG. 3 is a diagram showing a logic circuit according to a conventional technique.

FIG. 4 is a diagram showing a wiring configuration when a plurality of conventional logic circuits are connected.

[Explanation of symbols]

 1 ... Differential pair part 2 ... Diode 3,4 ... Load resistance 5,6 ... FET 7,8 ... FET 9 ... Constant current source FET 10 ... Feedback resistance 20 ... Level shift part 21,22 ... FET 23-26 ... Level shift diodes 27, 29 ... Constant current source FETs 28, 30 ... Feedback resistors 31-34 ... Conventional logic circuits 35-38 ... Logic circuit using the present invention 40 ... Differential pair section 41 ... Diodes 42, 43 ... Load resistance 44-47 ... FET 48 ... Constant current source FET 49 ... Feedback resistance 50 ... Level shift section 51, 52 ... FET 53-56 ... Level shift diode 57, 59 ... Constant current source FET 58 , 60 ... Feedback resistors 61-64 ... Logic circuits using conventional technology

Claims (1)

[Claims] 1. A high potential side power source (V_DD) And low-potential side power supply
(V_EE) And multiple transistor differential pairs in series
Has a vertically stacked logic gate that is connected and formed
In the semiconductor integrated circuit device, the threshold voltage of the transistor differential pair (5, 6) on the high potential side is
Pressure (V_TH1) Is a transistor differential pair (7,
8) threshold voltage (V_TH2Lower than (V _TH1<V
_TH2) A semiconductor integrated circuit characterized by being set
apparatus.