JPH042011B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention uses NMOS (N-Channel MOS) to create n-value inverter logic circuits, NAND circuits,
It relates to multivalued logic circuits that constitute NOR circuits, stability circuits, delta literal circuits, Sunary function circuits, etc.

[Conventional technology]

In LSI, the integration density is becoming higher and higher due to the development of circuit technology and semiconductor manufacturing technology. As this trend toward higher integration progresses and the number of elements inside an LSI increases, the wiring inside the chip becomes more complex.
The area occupied by the wiring also increases. By the way, the current LSI
It is said that as much as 70% of the area is occupied by wiring, and this proportion is expected to increase further in the future as LSIs become more highly integrated. Therefore, as a solution to this problem, research into multivalued logic circuits has become active in recent years.

In contrast to binary logic, which is the mainstream of current logic circuits, multi-value logic uses three or more logical values. For example, in R-value logic, "0", "1",...
A logical value "R-1" exists. Compared to binary logic circuits, multi-level logic circuits have a larger amount of information per signal line, so they can use fewer wires, and can also increase the integration density of elements within a chip. There are two major advantages: In order to realize multivalued logic with such great advantages, CCD (Charged
Couple Device), CMOS (Complementary
MOS Device), ECL (Emitter Couple Logic),
Applications of various devices such as I ² L (Integrated Injection Logic) are being considered.

[Problems to be solved by the invention] In conventional multivalued logic circuits, the number of elements increases and the pattern structure becomes complex, making it difficult to correspond between the pattern and the circuit configuration. There were problems such as the size of the image becoming larger. Furthermore, there was also a problem with reliability because levels indicating logical values were not propagated accurately. The present invention is based on the above considerations, and aims to provide a multivalued logic circuit with a reduced number of elements and a simplified pattern structure.

[Means for solving problems]

To this end, the multivalued logic circuit of the present invention uses one type of tapered MOS transistor and multiple types of enhancement type MOS transistors with different threshold values.
Based on circuits that combine transistors, inverter logic circuits, NAND circuits, NOR circuits,
It is characterized by configuring a stable circuit, a delta literal circuit, a unary function circuit, etc. In the tape compression type MOS transistor, a power supply is connected to a drain electrode, and a gate electrode and a source electrode are commonly connected to a plurality of types of enhancement type MOS transistors having different threshold values and an output terminal. An enhancement type MOS transistor consists of an element whose gate electrode is connected to an input terminal for determining the logical value of an input signal and for switching, and an element whose drain electrode is connected to the gate electrode and to the output terminal side, and whose source electrode is connected to the output terminal side. and an element connected to the ground potential side to obtain an output voltage corresponding to a desired logical value. The enhancement type MOS transistor has a threshold value intermediate between each logic value level. For example 4
In value logic, logical values "0", "1", "2",
The voltages corresponding to "3" are respectively 0, 1, 2, 3 [V]
Assuming that, the threshold values are approximately in between 0.5, 1.5, and 2.5 [V].

[Effect]

Enhancement type MOS transistors are used to determine and switch the logical value of input signals.
For example, when a voltage with a logical value of "2" is applied to the gate electrode, the elements with threshold values of 0.5 [V] and 1.5 [V] are conductive, and the element with threshold value of 2.5 [V] is non-conductive. It will remain as it is. In addition, in an enhancement type MOS transistor for obtaining an output voltage corresponding to a desired logical value, for example, when the threshold value is 1.5 [V], a second As explained later with reference to the figure, the tape compression type MOS
The power supply voltage is divided by transistors and enhancement type MOS transistors, and the threshold value is 1.5.
A stable state is reached at an output voltage of approximately 2 [V], which is higher than [V], and a logical value of "2" is output. However, enhancement type MOS with different thresholds
When multiple transistors are connected in parallel,
The output voltage is determined by the enhancement type MOS transistor with priority and the lowest threshold value. That is, the logical value "1" becomes the output voltage. At this time, the enhancement type MOS transistor with a high threshold becomes non-conductive because the voltage becomes below the threshold. That is, when a plurality of enhancement type MOS transistors having different threshold values are connected in parallel to a tapering type MOS transistor, priority is given to each enhancement type MOS transistor.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention regarding an inverter logic circuit, FIG. 2 is a diagram explaining the operation of the inverter logic circuit shown in FIG. FIG. 4 is a diagram showing the configuration of one embodiment of the present invention for a NOR circuit, FIG. 5 is a diagram showing the configuration of one embodiment of the present invention for a stabilizing circuit, and FIG. 1 is a diagram showing the configuration of an embodiment of the present invention regarding a delta literal circuit and a unary function circuit; FIG.
In the figure, _Q11 to _Q22 are depletion type MOS transistors, _Q31 to _Q79 are enhancement type MOS transistors, _S1 to _S3 are switches, and 1 to 4 are inserted parts of the output circuit, respectively.

In FIG. 1, a power supply V _DD is supplied to the drain electrode of the depletion type MOS transistor _Q11 , and the depletion type MOS transistor Q11
The gate electrode and source electrode of Q ₁₁ are the force terminal U(x)
and the respective drain electrodes and gate electrodes of the enhancement type MOS transistors Q ₃₁ and Q ₃₂ and the enhancement type MOS transistors
Connected to the drain electrode of _Q35 . Further, each source electrode of enhancement type MOS transistors Q ₃₁ and Q ₃₂ is connected to each drain electrode of enhancement type MOS transistors Q ₃₃ and Q ₃₄ .
and enhancement type MOS transistor Q ₃₃
In _Q35 , each source electrode is connected to the ground potential, and each gate electrode is connected to the input terminal x.
These connections allow logical values “0”, “1”, “2”,
When a signal of "3" is applied to the input terminal x, signals of logical values "3", "2", "1", and "0" are obtained at the output terminal U(x), respectively. That is, four inverter logic circuits are configured.

Next, the operation will be explained. In order to operate as a four-value inverter logic circuit as described above, enhancement type MOS transistors Q ₃₂ and Q ₃₃ have a first
Enhancement type MOS transistors Q ₃₁ and Q ₃₄ have elements that operate according to the second threshold, enhancement type MOS transistors Q 31 and Q 34
For the MOS transistor _Q35 , an element that operates based on the third threshold is used. Here, the first threshold is an intermediate level between logical values "0" and "1", and the second threshold is an intermediate level between logical values "1" and "2". , the third threshold is at a level intermediate between logical values "2" and "3". Therefore, the enhancement type MOS transistor Q ₃₃ or
Q ₃₅ switches in response to the input of logical values ``1'', ``2'', and ``3'', respectively, and can be replaced with switches S ₁ to S as shown in Figure 2 a. . Enhancement type MOS
The transistors Q ₃₁ and Q ₃₂ are used to obtain a desired output voltage, and FIG. 2b shows the operation transition of the depletion type MOS transistor Q ₁₁ and the enhancement type MOS transistor Q ₃₁ and Q ₃₂ . As shown in Figure 2b, the voltage of the power supply V _DD is 3 [V], the level of logic value "2" is 2 [V], the level of logic value "1" is 1 [V], and the third to first Assuming that the threshold values are respectively 2.5, 1.0, and 0.5 [V], when all switches S ₁ to S ₃ are off, 3 at point A
[V], B when only switch S ₁ is on
2 [V] at point C, 1 [V] at point C when switches S ₁ and S ₂ are on, 0 [V] at point D when all switches S ₁ to S ₃ are on. The vicinity becomes a stable point, and each voltage level is output terminal U.
Obtained in (x). Note that the third to first threshold values do not necessarily have to be 2.5, 1.0, or 0.5 [V], but are selected from 3 to 2, 2 to 1, and 1 to 0 [V].

Therefore, when the input terminal x has a logic value of "0", the enhancement type MOS transistor _Q33 or
Since all of Q ₃₅ are non-conducting, the output terminal U(x)
In this case, the voltage of the power supply V _DD remains unchanged, that is, an output with a logical value of "3" is obtained. Next, when the input terminal x becomes a logical value "1", the enhancement type MOS transistor _Q33 , which operates at the first threshold value, becomes conductive. In this case, in FIG. 2a, switch S ₁
only is turned on. In this state,
Enhancement type operating at second threshold from depletion type MOS transistor _Q11
Since the current of the power supply _VDD flows through the MOS transistor _Q31 , the output terminal U(x) has a logic value of "2".
The output is obtained. Furthermore, when the input terminal x becomes a logic value "2", the enhancement type MOS transistor _Q34 , which operates at the second threshold value, also becomes conductive. In this case, in FIG. 2a, switch S ₁
and _S2 is turned on. In this state,
Since the current of the power supply V _DD flows from the depletion type MOS transistor Q ₁₁ through the enhancement type MOS transistor Q ₃₂ which operates at the first threshold value smaller than the second threshold value, the output terminal U
An output of logical value "1" is obtained for (x). Then, when the input terminal x becomes the logical value "3", the enhancement type MOS transistor _Q35 , which operates at the third threshold value, also becomes conductive. In this case, all switches _S1 to _S3 are turned on in FIG. 2a. In this state, the output terminal U(x)
and ground potential are short-circuited by switch _S3 , resulting in an output of logical value "0". The truth table showing the correspondence between input and output as described above is shown in Figure 2c.
It is.

Based on the configuration of the inverter logic circuit described above.
FIG. 3 shows an example of a NAND circuit. In FIG. 3, a series circuit of enhancement type MOS transistors Q ₃₈ and Q ₄₁ corresponds to the switch S ₁ shown in FIG. 2a, and a series circuit of enhancement type MOS transistors Q ₃₉ and Q ₄₂ corresponds to the switch S 1 shown in FIG. Compatible with Switch S ₂ , enhancement type
The series circuit of MOS transistors Q ₄₀ and Q ₄₃ is the second
This corresponds to the switch _S3 shown in Figure a. As is clear from the circuit configuration shown in FIG. 3a, the conductive series circuit is determined by the level of the lower of the input terminals x and y. For example, when the input terminal x has a logic value of "3" and the input terminal y has a logic value of "1", the enhancement type MOS transistors Q ₃₈ to Q ₄₀ controlled by the input terminal x have a logic value of "3". '', all of them are conductive, but since the enhancement type MOS transistors Q41 to _Q43 controlled by the input terminal y have a logical value of "1", only the enhancement _{type MOS transistor Q41 is} conductive. Therefore, in this case, it is the same as if only the switch _S1 shown in FIG. 2a was turned on, and an output of logical value "2" is obtained at the output terminal U(x). FIG. 3b shows the correspondence between the logical values of the input terminals x and y and the logical value obtained from the output terminal U(x).

Similarly, FIG. 4 shows an example of a NOR circuit based on the configuration of the above-described inverter logic circuit.
In FIG. 4, the parallel circuit of enhancement type MOS transistors Q ₄₆ and Q ₄₇ corresponds to the switch S ₁ shown in FIG.
The parallel circuit with transistor Q ₄₈ and Q ₄₉ is shown in Figure 2a.
Compatible with the illustrated switch S ₂ , enhancement type
The MOS transistors Q ₅₀ and Q ₅₁ and the parallel circuit correspond to the switch S ₃ shown in FIG. 2a. As is clear from the circuit configuration shown in FIG. 4a, the conductive parallel circuit is determined by the higher level of the input terminals x and y. For example, if the input terminal x has a logical value of "0",
If the input terminal y has a logical value "2", the enhancement type controlled by the input terminal x
MOS transistors Q ₄₆ , Q ₄₈ and Q ₅₀ have logical value “0”
Therefore, all remain non-conducting, but the enhancement type MOS controlled by the input terminal y
Transistors Q ₄₇ , Q ₄₉ , and Q ₅₁ have a logic value of "2", so enhancement type MOS transistor Q ₄₇
and Q ₄₉ conduct. Therefore, in this case, it is the same as when the switches _S1 and _S2 shown in FIG. 2A are turned on, and an output of logic value "1" is obtained at the output terminal U(x). FIG. 4b shows the correspondence between the logical values of the input terminals x and y and the logical value obtained from the output terminal U(x).

FIG. 5 shows an example of a four-level stable circuit using two of the above NOR circuits. In Figure 5,
The respective circuits divided to the left and right from the center of the drawing are the same as the circuit shown in FIG. And the fourth
The input terminal y in the illustrated circuit is used as the set terminal (S) and reset terminal (R) of this stabilizing circuit, and the input terminals x are alternately connected to the output terminals of the other side. Therefore, for example, if the set terminal S _is set to the logic value " ₂ " in FIG.
The output of the enhancement type MOS transistor _Q52 is controlled to a logical value of "1" by the threshold value, and this output value is supplied as an input to the circuit on the right side of the figure. On the other hand, in the circuit on the right side of the figure, the enhancement type MOS transistor Q ₆₃ becomes conductive due to the input of the logical value "1", and the output becomes the logical value "2" due to the threshold of the enhancement type MOS transistor Q ₅₄ .
is controlled and returned as an input to the circuit on the left side of the diagram. In this way, the output terminals Q and are held at logical values of "2" and "1", respectively. FIG. 5b shows logical values output corresponding to the logical values of terminals S and R. Furthermore, as is clear from the above explanation, such a stabilizing circuit is, of course, a third stabilizing circuit.
It is also possible to implement the same method using the NAND circuit shown in the figure.

Further, by using the above-mentioned multivalued logic circuit, a delta literal circuit or a unary function circuit can be constructed.

A delta literal circuit has multi-value inputs and respective logical outputs corresponding to the multi-values. For example, for a four-value input x (0, 1, 2, 3), four outputs U(x ₀ ), U(x ₁ ), U(x ₂ ), U(x ₃
)
When input x is "0", only U(x ₀ ) is "3", when input x is "1", only U(x ₁ ) is "3", and when input x is "2", U is "3". Only (x ₂ ) is set to "3", and when the input x is "3", only U(x ₃ ) is set to "3".

Further, the unary function circuit has multi-value inputs and multi-value outputs, and each multi-value input corresponds to a multi-value output in accordance with the logic of the circuit.
Therefore, for example, for a four-value input (0, 1, 2, 3), the output U(x) is "0", "1", "2", "3".
”
You can choose either one.

Fig. 6 shows an example of a delta literal circuit within the dashed line frame, and further adds depletion type MOS transistor _Q16 , enhancement type MOS transistors _Q68 to _Q71 , and output circuits 1 to 4 to this delta literal circuit to form a unary circuit. This shows an example of a functional circuit. The delta literal circuit and unary function circuit shown in FIG. 6 will be explained below.

The delta literal circuit utilizes the basic circuit configuration of the inverter logic circuit shown in FIG. 1 and the NOR circuit shown in FIG. 4, as shown within the dashed line frame in FIG. In other words, in this circuit, when the input voltages are 0 to 1, 1 to 2, 2 to 3, and 3 to 4, the output voltage becomes the value of logic "n" (power supply voltage V _DD ), and in other cases is a multi-value logic circuit equipped with a four-value delta literal circuit having four output terminals, 0th to 3rd, whose output voltage is a logic "0" value,
Each gate electrode is commonly connected to the input terminal x, each drain electrode is connected to the 0th to 2nd output terminal, and each source electrode is connected to the ground potential, 0 to
Three first enhancement type MOS transistor groups Q ₇₂ , Q ₇₄ , Q ₇₇ having threshold voltages within the range of 1, 1 to 2, and 2 to 3; two second enhancement type MOS transistor groups Q ₇₃ connected in parallel to each drain electrode and each source electrode of the two first enhancement type MOS transistor groups _Q 74 and Q ₇₇ having threshold voltages; , Q ₇₆ , a third enhancement type MOS transistor Q ₇₉ whose drain electrode is connected to the third output terminal and whose source electrode is connected to ground potential, and whose respective gate electrodes are connected to the input terminal x
and two fourth enhancement type MOS transistor groups Q ₇₅ and Q ₇₈ which are commonly connected to the ground potential, each source electrode of which is connected to the ground potential, and which have threshold voltages within the range of 1 to 2 and 2 to 3. , the fourth above
The drain and source electrodes of the elements (Q ₇₅ ) each having a threshold voltage within the range of V _i-2 to _{V i-1} among the group of enhancement-type MOS transistors are
A second enhancement type MOS transistor group Q ₇₆ is connected in parallel to the drain electrode and source electrode of the first enhancement type MOS transistor group Q ₇₇ having a threshold voltage within the range of V _i-2 to _Vi . Two to two of the fourth enhancement type MOS transistor group are connected to the gate electrode and the source electrode.
The drain electrode and source electrode of the element Q ₇₈ having a threshold voltage within the range of No. 3 are connected to the gate electrode and source electrode of the third enhancement type MOS transistor Q ₇₉ .
Among the MOS transistors, the drain electrode and source electrode of the element _Q72 having a threshold voltage within the range of 0 to 1 are connected to the first element Q72 having a threshold voltage within the range of 1 to 2.
Element Q ₇₄ of the enhancement type MOS transistor group is connected in parallel to the drain electrode and source electrode of element Q ₇₃ of the second enhancement type MOS transistor group, and connected to the gate electrode and source electrode of element Q 73 of the first enhancement type MOS transistor group. Depletion type MOS transistors _Q17 to Q22 are connected to the respective drain electrodes of the transistor groups Q72, _Q74 , _Q77 , the third enhancement _type MOS transistor _L79 , and the fourth enhancement type MOS transistor group _Q75 , _{Q78 .} Connect the power via.

With the above connection configuration, in the delta literal circuit, the enhancement type
One of the MOS transistors _Q68 to _Q71 is selectively made conductive. That is, when the input terminal x has a logical value of "0", the enhancement type MOS
None of the transistors Q ₇₂ , Q ₇₄ , Q ₇₅ , Q ₇₇ , and Q ₇₈ conducts, and enhancement type MOS transistors Q ₇₃ , Q _{76 ,} and Q ₇₉ conduct. Therefore, enhancement type MOS transistors Q ₆₉ and Q ₇₀ do not conduct, but enhancement type MOS transistors Q 69 and Q 70 do not conduct.
Q ₆₈ conducts. Next, input terminal x has logical value “1”
When this happens, enhancement type MOS transistor Q ₇₂ becomes conductive and enhancement type MOS transistor Q ₇₃ becomes non-conductive, so enhancement type MOS transistor Q ₆₉ becomes conductive and enhancement type MOS transistor Q ₆₈ becomes non-conductive. Thereafter, the logic value of the input terminal x increases successively, and enhancement type MOS transistors Q ₇ and Q ₇₅ become conductive, and then enhancement _type MOS transistors Q ₇₇ and Q ₇₈ become _conductive . The conduction element changes. Note that in a circuit with five or more values, a configuration similar to the illustrated circuit consisting of depletion type MOS transistors Q ₁₉ and Q ₂₀ and enhancement type MOS transistors Q ₇₅ to Q ₇₇ is added.

Therefore, by connecting circuits corresponding to desired output potentials as output circuits 1 to 4 to the drain electrodes of enhancement type MOS transistors Q ₆₈ to Q ₇₁ , the unary function can be realized. That is, as shown in FIG. 6b, when obtaining an output potential of logical value "0", a short circuit is used.
In order to obtain an output potential with a logical value of "1", the drain electrode and gate electrode are commonly connected and the voltage is 0 to 1 [V].
Enhancement type MOS with threshold between
A transistor circuit is used, and when obtaining an output potential of logical value "2", an enhancement type MOS transistor circuit with a threshold voltage between 1 and 2 [V] with the drain electrode and gate electrode commonly connected,
When an output potential of logical value "3" is obtained, it is released. Note that in this case, all circuits related to this (including delta literals) are unnecessary. With this configuration, the logical value of the output terminal can be arbitrarily set between ``0'' and ``3'' in ⁴ different combinations for the logical value ``0'' to ``3'' of the input terminal x. can do. Therefore, the output circuits 1 to 4 are given, for example, logical values "3", "2", "1",
If a circuit that obtains an output voltage of "0" is used, a four-value inverter logic circuit can be created. However, in the case of the inverter logic circuit, according to the present invention, the structure shown in FIG. 1 can be simplified rather than using a unary function circuit.

In the above explanation, an example of a four-valued logic circuit has been shown, but it goes without saying that these are not limited to four-valued logic circuits, but can also be applied to any number of multi-valued logic circuits.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, a depletion type MOS transistor is connected to the power supply side, and an enhancement type MOS transistor is connected to the depletion type MOS transistor for switching with a threshold value matching the desired level of the multi-valued logic. and an enhancement type that outputs a logical value of the desired level.
By combining and configuring MOS transistors, we can prioritize and take out the output potential arbitrarily according to the priority, so we can configure a multi-value logic circuit with a simple connection configuration and a small number of transistors. can do. Therefore, it is possible to construct a high-density, high-speed multivalued logic circuit, reduce power consumption in the multivalued logic circuit, simplify the pattern structure, and improve the correspondence between the pattern and the circuit diagram. It becomes easier to take. In addition, by using depletion type MOS transistors and enhancement type MOS transistors, it becomes possible to accurately propagate the levels (each voltage of n value), and it is possible to improve the reliability of multivalued logic circuits. , since the manufacturing technology is the same as that of binary (0, 1) logic LSI, it is possible to coexist with binary logic circuits, develop and develop logic circuits based on the same concept as binary logic circuits, and has a wide range of applications. It is possible to construct a circuit with n-value logic. Further, according to the present invention, the systemization of multi-valued logic circuits has been developed, so it is possible to realize a system of multi-valued logic circuits.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention regarding an inverter logic circuit, FIG. 2 is a diagram explaining the operation of the inverter logic circuit shown in FIG. FIG. 4 is a diagram showing the configuration of one embodiment of the present invention for a NOR circuit, FIG. 5 is a diagram showing the configuration of one embodiment of the present invention for a stabilizing circuit, and FIG. 1 is a diagram showing the configuration of an embodiment of the present invention regarding a delta literal circuit and a unary function circuit; FIG. Q ₁₁ to Q ₂₂ ... depletion type MOS transistor, Q ₃₁ to Q ₇₉ ... enhancement type MOS transistor, S ₁ to S ₃ ... switch, 1 to 4 ... insertion part of output circuit.

Claims (1)

[Scope of Claims] 1. A depletion type MOS transistor whose drain electrode is connected to a power source, each having a unique threshold voltage corresponding to a desired output voltage, and a gate electrode, a source electrode, and an output terminal of the depletion type MOS transistor. a group of (n-2) first enhancement type MOS transistors, each of which has its drain electrode and each gate electrode connected in common;
and V ₁ , V ₂ , with each gate electrode commonly connected to the input terminal and each source electrode connected to ground potential,
……, V _o-1 (｜V ₁ ｜＜｜V ₂ ｜＜…＜｜V _o-1 ｜)
It is composed of (n-1) second enhancement type MOS transistors having a threshold voltage of V ₁ , V ₂ , . . . , V _o- Each drain electrode of each enhancement type MOS transistor having a threshold voltage of ₂ is connected to each source electrode of the first enhancement type MOS transistor group, and the enhancement type MOS transistor having a threshold voltage of V _o-1 A multi-valued logic circuit characterized in that the drain electrode of is connected to a common connection point between each drain electrode and each gate electrode of the first enhancement type MOS transistor group to constitute an n-value inverter logic circuit. 2 depletion type MOS transistors whose drain electrodes are connected to a power source, each having a unique threshold voltage corresponding to a desired output voltage; a group of (n-2) first enhancement type MOS transistors whose gate electrodes are commonly connected;
and each gate electrode is commonly connected to the input terminal
V ₁ , V ₂ , ..., V _o-1 (｜V ₁ ｜＜｜V ₂ ｜＜...＜
A second enhancement-type MOS in which (n-1) m sets of enhancement-type MOS transistors having a threshold voltage of |V _o-1 |) are connected in series.
Consisting of a group of transistors, of the second enhancement type MOS transistor group,
Each drain electrode side of the series circuit of each enhancement type MOS transistor having a threshold voltage of V ₁ , V ₂ , ..., V _o-2 is connected to each source electrode of the first enhancement type MOS transistor group. , the drain electrode side of the series circuit of enhancement type MOS transistors having a threshold voltage of V _o-1 is connected to a common connection point between each drain electrode and each gate electrode of the first enhancement type MOS transistor group, A multivalued logic circuit characterized in that each source potential side is connected to a ground electrode to form an m-input n-value NAND circuit. 3 depletion type MOS transistors whose drain electrodes are connected to a power supply, each having a unique threshold voltage corresponding to a desired output voltage; a group of (n-2) first enhancement type MOS transistors whose gate electrodes are commonly connected;
and each gate electrode is commonly connected to the input terminal
V ₁ , V ₂ , ..., V _o-1 (｜V ₁ ｜＜｜V ₂ ｜＜...＜
A second enhancement-type MOS in which (n-1) m sets of enhancement-type MOS transistors having a threshold voltage of |V _o-1 |) are connected in series.
Consisting of a group of transistors, of the second enhancement type MOS transistor group,
Each drain electrode side of the parallel connection circuit of each enhancement type MOS transistor having a threshold voltage of V ₁ , V ₂ , and V _o-2 is connected to each source electrode of the first enhancement type MOS transistor group,
Enhancement type with threshold voltage of V _o-1
The drain electrode side of the parallel connection circuit of MOS transistors is connected to the common connection point between each drain electrode and each gate electrode of the first enhancement type MOS transistor group, and each source electrode side is connected to the ground electrode to receive m input. A multi-value logic circuit comprising an n-value NOR circuit. 4 depletion type MOS transistors whose drain electrodes are connected to a power supply, each having a unique threshold voltage corresponding to a desired output voltage; a group of (n-2) first enhancement type MOS transistors whose gate electrodes are commonly connected;
and each gate electrode is commonly connected to the input terminal
V ₁ , V ₂ , ..., V _o-1 (｜V ₁ ｜＜｜V ₂ ｜＜...＜
The second enhancement type MOS transistor group is composed of m sets of (n-1) enhancement type MOS transistor groups connected in series or in parallel, each having a threshold voltage of |V _o-1 |). Of the enhancement type MOS transistor group, each drain electrode side of the series or parallel connection circuit of each enhancement type MOS transistor having a threshold voltage of V ₁ , V ₂ , ..., V _o-2 is connected to the first enhancement type transistor. The drain electrode side of the series or parallel connection circuit of enhancement type MOS transistors having a threshold voltage of V _o-1 is connected to each source electrode of the group of type MOS transistors.
Two circuits are connected to the common connection point between each drain electrode and each gate electrode of the enhancement type MOS transistor group, and each source electrode side is connected to the ground potential. 1. A multivalued logic circuit characterized in that an n-value stable circuit is constructed by alternately connecting the output terminals and the remaining input terminals as set (S) and reset (R) terminals.