JPS59208860A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59208860A
JPS59208860A JP8274183A JP8274183A JPS59208860A JP S59208860 A JPS59208860 A JP S59208860A JP 8274183 A JP8274183 A JP 8274183A JP 8274183 A JP8274183 A JP 8274183A JP S59208860 A JPS59208860 A JP S59208860A
Authority
JP
Japan
Prior art keywords
alloy
adsorbent
hydrogen
cavity
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8274183A
Other languages
Japanese (ja)
Inventor
Takayuki Okinaga
隆幸 沖永
Hiroshi Ozaki
尾崎 弘
Kanji Otsuka
寛治 大塚
Kazumichi Mitsusada
光定 一道
Masamichi Ishihara
政道 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP8274183A priority Critical patent/JPS59208860A/en
Publication of JPS59208860A publication Critical patent/JPS59208860A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE:To remove defective factors, such as H2, H2O, etc. having an adverse effect on a semiconductor device by incorporating an adsorbent into the cavity of a semiconductor package. CONSTITUTION:A metallized layer 7 consisting of an Mg group alloy as a hydrogen adsorbent is formed on the back, the cavity side, of a cap 1 for a cerdip type semiconductor package, and a porous alumina layer 8 as a moisture adsorbent is formed to one part on the surface of the metallized layer 7. It is desirable that the Mg group alloy, such as an alloy consisting of Mg and Ni, an alloy consisting of Mg and Cu or the like is used as the hydrogen adsorbent employed. An alloy or a metal adsorbing hydrogen, such as a Pd metal, an LaCo alloy or the like may be used as other metals or alloys.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に適用して有効な技術に関するもの
であり、特に半導体パッケージのキャビティ内の水素や
水分を除去する技術にアr1用して有効な技術に関する
ものである。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to semiconductor devices, and in particular to a technique that is effective when applied to a technique for removing hydrogen and moisture in a cavity of a semiconductor package. It's about technology.

〔背景技術〕[Background technology]

周知のごとく、半導体装置は水蒸気などの影響を受けや
すいっこれらの影響によりその特性が変化し半導体装W
が不良となり使用できなくなることを防止するため、半
導体素子(ベレット)を外気から保護するようにハーメ
チックシール、レジンモールドなどの封止が行われてい
る。
As is well known, semiconductor devices are susceptible to the effects of water vapor, etc. These influences change their characteristics, causing semiconductor devices to deteriorate.
In order to prevent semiconductor devices (bullets) from becoming defective and becoming unusable, hermetic seals, resin molds, etc. are used to protect them from the outside air.

しかし、ペレットを封止するため半導体パッケージに形
成されたキャビティ内には、刺止後にもH20JPH,
やその池のガス状物が存在し、これらが半導体素子に悪
影響を与えること力瓢本発明者の実験により明らかにな
ったつここに、キャビティとは半導体素子が載置される
部分であって外萌器(パッケージ)で外部と遮断された
空間をいい、例えはセラミックタイプの半導体パッケー
ジはべ−ス基板の半導体素子配設部(溝部)に半導体素
子を載置しくダイボンディング)、半導体素子とリード
とをワイヤボンディング後、AU−8nろう材や低融点
ガラスな封止材料として用いキャップをかぶせて作られ
るが、この際のキャップと前記配設部とで区画される半
導体パッケージ内部空間がこれに相当する。
However, in the cavity formed in the semiconductor package to seal the pellet, H20JPH,
Experiments conducted by the present inventor have revealed that there are gaseous substances in the pond and that these have an adverse effect on semiconductor devices. It refers to a space that is isolated from the outside by a package.For example, a ceramic type semiconductor package is used to place a semiconductor element in the semiconductor element mounting area (groove) of a base substrate (die bonding). After wire bonding with the leads, a cap is used as a sealing material such as AU-8n brazing material or low-melting glass to cover the semiconductor package. corresponds to

この半導体素子に悪影響を与えるH、やH,O’Pガス
状物は半導体装置の製造過程において、また使用した材
料から様々に発生し、またキャビティ内に封止後も残存
し、あるいは導入されてくる。
These H, H, and O'P gaseous substances that have an adverse effect on semiconductor devices are generated in various ways during the manufacturing process of semiconductor devices and from the materials used, and may remain in the cavity even after sealing or may be introduced. It's coming.

以下に本発明者の実験により明らかになった上記ガス状
物の発生の原因について述べる。
The causes of the generation of the gaseous substances as revealed by the inventor's experiments will be described below.

fil  α線によるンフトエラー(メモリを誤動作さ
せる現象)f!r:防止1−るためにチップ表面に高分
子材料例えばポリイミド糸合成樹脂をコートすることが
行わ五ている。パッケージの封幻ま400C前後で行わ
れるので加熱により当該樹脂が分解し。
fil Error due to alpha rays (phenomenon that causes memory to malfunction)f! r: To prevent this, the chip surface is coated with a polymeric material such as polyimide thread synthetic resin. Since the package is sealed at around 400C, the resin decomposes due to heating.

Ht O’F Htその他の分解ガス?生じる。Ht O’F HtOther decomposed gas? arise.

(2)  ダイボンディングの方法の一つとして、セラ
ミックベース上の導体面をAu面にしておぎ、400C
前後に加熱してSiチップの裏面をスクライプしてAu
−8i共晶により合金化して接続する方法がある。この
Au−8i共晶は加熱されると雰囲気中の微少のH,0
と反応し、N7を放出する。
(2) As one of the die bonding methods, the conductor surface on the ceramic base is set as the Au surface, and 400C
Scrape the back side of the Si chip by heating it back and forth to make Au.
There is a method of alloying and connecting using -8i eutectic. When this Au-8i eutectic is heated, a small amount of H, 0 in the atmosphere
reacts with and releases N7.

13+  気密封止する場合金属キャップなA u −
S nプリホームを用いてセラミックキャップに半田付
けすることが行われているうこの加熱封圧の際にA u
 −S nブリホームの酸化を防止し還元雰111気に
するためにN2を添加すると、このH,カスはキャピテ
イ内にとどまり半導体素子に悪影響を及ぼす。
13+ For airtight sealing, use a metal cap A u −
A u
When N2 is added to prevent the oxidation of the -Sn preform and create a reducing atmosphere, the H and dregs remain within the cavity and adversely affect the semiconductor device.

(4)半導体装置のパッジベージコン1換としてプラズ
マCVD法により形成したシリコンナイトライド(Si
N)膜を使用1−ろことかある。このSiN膜はHlを
トラップする性質があろう +51  パッケージを構成1−るセラミックは多孔質
のものであるのでH,0などをトラップする性質があり
、これらは封止後にキャビティ内に出てくる。
(4) Silicon nitride (Si
N) Use a membrane 1- It may be a loco. This SiN film probably has the property of trapping Hl.+51 Since the ceramic that constitutes the package is porous, it has the property of trapping H, 0, etc., which come out into the cavity after sealing. .

〔発明の目的〕[Purpose of the invention]

本発明は半導体装置の製造過桂および製造後に、半導体
素子に悪影gを与えるカス状物特に■I、やH,0な容
易な化学的手段により除去することを目的としたもので
あり1%に■I、やH!0を除去してホットキャリアに
よるデバイス動作不良という問題点を解消した半導体装
いを提供することを目的とする。
The purpose of the present invention is to remove by easy chemical means, especially ① I, H, 0, etc., residues that give a bad impression to semiconductor elements during and after the manufacture of semiconductor devices. % ■I, YaH! An object of the present invention is to provide a semiconductor device which eliminates the problem of device malfunction due to hot carriers by removing 0's.

本発明の前記およびその11ルの目的ならびに新規な特
徴は本明細書の記載および添附図面からあきらかになる
であろう。
The foregoing and eleventh objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

〔発明のi要〕[Key points of the invention]

本発明は半導体パッケージのキャビティ内に吸着剤を内
蔵させることにより、半導体装置に悪影響を与えるH、
やH,0なとの不良因子を除去1°′るようにしたもの
である。
The present invention incorporates an adsorbent into the cavity of a semiconductor package to eliminate H, which has an adverse effect on semiconductor devices.
It is designed to remove defective factors such as , H, and 0 by 1°'.

〔実施例1〕 第1図はサーディツプタイプの半導体パッケージを示す
。図中、1はセラミックなどよりなるキャップ、2は低
融点カラス(鉛ガラス)なとよりなるシーリング材、3
はセラミックなどよりなるベース、4はメモリ回路や論
理回路などが形成された半導体チップ、5は42アロイ
材などよりなるリード、6は半導体チップとリードとを
tlL i(、「Jに接続するコネクタワイヤ(ボンデ
ィングワイヤ)である。
[Embodiment 1] FIG. 1 shows a cerdip type semiconductor package. In the figure, 1 is a cap made of ceramic or the like, 2 is a sealing material such as low-melting glass (lead glass), and 3 is a cap made of ceramic or the like.
is a base made of ceramic or the like, 4 is a semiconductor chip on which a memory circuit, logic circuit, etc. are formed, 5 is a lead made of 42 alloy material, etc., and 6 is a connector that connects the semiconductor chip and the lead to tlL i (, ``J''). It is a wire (bonding wire).

第2図はこのようなサーディツプタイプの半導体パッケ
ージの当該キャップ1に本発明を油出した例を示す。キ
ャップ1の15面1−なわちキャビティ側にブず水嵩v
!W剤としてのMy糸合金のスクライプM7を形成し、
さらに、このスクライプ層7の表面上の一部に水分吸着
剤としての多孔質アルミナ層を形成しているう 本発明に使用される水素吸着剤としてはMll系合金例
えばMgとN1とからなる合金1MgとCLIとからな
る合金を用いるのが望ましい。その他Pd 金属、La
Co合金など水素をg&層する合金。
FIG. 2 shows an example in which the present invention is applied to the cap 1 of such a cerdip type semiconductor package. 15 side 1 of cap 1 - that is, there is water volume v on the cavity side.
! Form a scribe M7 of My yarn alloy as a W agent,
Furthermore, a porous alumina layer is formed as a moisture adsorbent on a part of the surface of the scribe layer 7.The hydrogen adsorbent used in the present invention is an Mll-based alloy, for example, an alloy consisting of Mg and N1. Preferably, an alloy consisting of 1Mg and CLI is used. Other Pd metal, La
Alloys that contain hydrogen such as Co alloys.

金員を用いてもよい。水素吸着剤をキャビティ内に内蔵
させる方法としては導体パターンやfttdt<パター
ンの形成技術として使用されているメタライゼーション
や溶融金属を滴下させるボノティング技術などを用いろ
。メタライゼーションにより形成する場合はセラミック
パッケージを焼成した後に行うのがよい。
Money may also be used. As a method for incorporating the hydrogen adsorbent into the cavity, use metallization, which is used as a technique for forming conductor patterns or patterns, or a bonoting technique in which molten metal is dropped. When forming by metallization, it is preferable to do so after firing the ceramic package.

M、9にNi、Cuを混ぜ合金とする理由は、Mllの
水素吸沼力を高めるためである。Ni、CuはMyが水
素を吸着しMg・Hとなる反応を促進する触媒のような
殿きをする。NLCuの混入比率をほぼ2%〜50%の
範囲で潤整することにより、パッケージ内の水素の吸着
時間をW1v整できる。50%を越えるとMgの体積が
少ないので十分な吸着ができない。したがって、水素の
吸着時間があまり問題とならないときは1Mg合金に代
えてMIのみを用いてもよいっこれはPdなどの金8を
用いる場合でも同様である。
The reason why M and 9 are mixed with Ni and Cu to form an alloy is to increase the hydrogen absorbing ability of Mll. Ni and Cu act as catalysts that promote the reaction of My adsorbing hydrogen to form Mg.H. By adjusting the mixing ratio of NLCu within the range of approximately 2% to 50%, the hydrogen adsorption time in the package can be adjusted to W1v. If it exceeds 50%, the volume of Mg is so small that sufficient adsorption cannot be achieved. Therefore, when the hydrogen adsorption time is not so important, only MI may be used in place of the 1Mg alloy. This also applies to the case where gold 8 such as Pd is used.

なお、水素を充分吸着させるにはアニール(熱処理)を
行い、活性化するのがよい。これにより。
In addition, in order to adsorb hydrogen sufficiently, it is preferable to perform annealing (heat treatment) and activate it. Due to this.

パッケージのセラミックやパッシベーション膜中に内在
するガスがキャビティ内に放出されるからである。
This is because gas inherent in the ceramic and passivation film of the package is released into the cavity.

水分吸着剤としては多孔質アルミナを使用するのがよく
、ボッティング技術により内蔵させることができる。ま
た、これに代えてシリカなどを用いてもよい。
Porous alumina is preferably used as the moisture adsorbent, and can be incorporated using the botting technique. Moreover, silica or the like may be used instead of this.

これら水累吸着剤、水分吸着剤を内蔵させろ場合、キャ
ビティ表面積の5%以上を占有させることが好ましい。
When these water accumulation adsorbents and moisture adsorbents are incorporated, it is preferable that they occupy 5% or more of the cavity surface area.

これにより、十分な吸着画情を確保できる。Thereby, sufficient suction image quality can be ensured.

このように、キャップに水素吸着剤と水分(1!& 3
?:f剤とを設けておくことにより、キャピテイ内の1
−120 、Htは容易に除去されろ、すなわち、第3
図に示すように、ベース3に半導体チップ4を載置固着
し、当該半導体チップの出力電←ことリード5とをコネ
クタワイヤ6によりワイヤボンディングした後に、シー
リング材2を匣用して、水素吸着剤7と水分吸着剤8と
を(ii+!えたキャップ1を封止するとき、封正によ
り半導体チップ4表面にコートされたポリイミド樹脂か
らなるンフトエラー防止樹脂9が分解してHtO2Ht
その他分解ガスを放出しても、キャビティlO内のガス
は前記水素g&着剤、水分吸着剤により吸着され除去さ
れる。
In this way, the cap is filled with hydrogen adsorbent and water (1! & 3
? : By providing an f agent, one
−120, Ht is easily removed, i.e., the third
As shown in the figure, a semiconductor chip 4 is placed and fixed on a base 3, and the output voltage of the semiconductor chip is wire-bonded to the leads 5 using a connector wire 6, and then a sealing material 2 is applied to absorb hydrogen. When sealing the cap 1 containing the agent 7 and the moisture absorbent 8 (ii+!), the error prevention resin 9 made of polyimide resin coated on the surface of the semiconductor chip 4 decomposes and becomes HtO2Ht.
Even if other decomposed gases are released, the gases in the cavity IO are adsorbed and removed by the hydrogen g, adhesive, and moisture adsorbent.

尚第3図にはベース3の表面にさらに水分吸着剤7を配
設してなる実施例を示す。
FIG. 3 shows an embodiment in which a moisture adsorbent 7 is further provided on the surface of the base 3.

〔実施例2〕 8i¥4図はセラミックタイプの半導体パッケージを示
1゜図中、11は合メッキされたコバール利などよりな
るキャップ、12はAu−8n共晶什金などよりなるろ
う材(プリホーム)、13はリード、14は層状の、へ
β203セラミックなどよりなるパッケージ本体、15
はタングステンなどよりなるメタライゼーション(配線
)である。また第4図中、16はキャビティであり、ろ
う材12よりキャップ11を封d−すると半導体パッケ
ージ内に形成される。尚第4図中には半導体チップやワ
イヤボンディングなどは省略しである、このよ51tC
h’i ANセラミックタイプの半導体パッケージにお
いて、第5図は当該キャビティ内に本発明を1角用した
実がす例を示1゜尚、第5図はキャップをとった状態を
示し、当該キャビティ内に載1寵された半導体チップ1
7はワイヤボンディング(図示せず)によりインナーリ
ード18と′電気的な接続がとられる。
[Example 2] Figure 8i¥4 shows a ceramic type semiconductor package. In the figure, 11 is a cap made of co-plated Kovar alloy, etc., and 12 is a brazing filler metal (made of Au-8N eutectic filler metal, etc.). 13 is a lead, 14 is a layered package body made of β203 ceramic, etc., 15
is metallization (wiring) made of tungsten or the like. Further, in FIG. 4, reference numeral 16 denotes a cavity, which is formed in the semiconductor package when the cap 11 is sealed with the brazing material 12. Semiconductor chips, wire bonding, etc. are omitted in Figure 4.
In a h'i AN ceramic type semiconductor package, Fig. 5 shows an example in which the present invention is used in one corner in the cavity. Semiconductor chip 1 placed inside
7 is electrically connected to the inner lead 18 by wire bonding (not shown).

第5図に示す実施例において1本発明は半導体チップ1
7とインナーリード18とを接続1−るボンディングワ
イヤの下部空間キャビティ底面に水素吸着剤としてのM
y糸金合金19配設し、またインナーリード18が配さ
れた段部に水素吸着剤としての多孔質アルミナ21を設
けである。
In the embodiment shown in FIG.
M as a hydrogen adsorbent is placed on the bottom surface of the cavity in the lower space of the bonding wire 1 which connects 7 and the inner lead 18.
A metal thread alloy 19 is disposed, and porous alumina 21 as a hydrogen adsorbent is disposed at the stepped portion where the inner lead 18 is disposed.

かかる半導体パッケージの構造を第6図によりさらに説
明てろ。パッケージ本体14の上面に第1の実施例で示
した水素吸着剤19を敷設し、またキャビティ内股部2
0に第1の実施例で示した水分吸着剤21をvl、設し
、半導体チップ17とインナーリード18とをコネクタ
ワイヤ22によりワイヤボンディング後、Au−8nプ
リホーム12を用いてキャップ11を封止1〜る。
Please further explain the structure of such a semiconductor package with reference to FIG. The hydrogen adsorbent 19 shown in the first embodiment is laid on the upper surface of the package body 14, and the inner thigh part 2 of the cavity is laid down.
After wire bonding the semiconductor chip 17 and the inner leads 18 with the connector wire 22, the cap 11 is sealed using the Au-8n preform 12. Stop 1~ru.

このAu−8nプリホームにより封止−1−る際にI−
1。
When sealing with this Au-8n preform, I-
1.

が添加されるが、キャビティ16内のII、は水素吸着
剤19により吸着除去される。
is added, but II in the cavity 16 is adsorbed and removed by the hydrogen adsorbent 19.

上記実施例では水素吸着剤および水分吸着剤両方をキャ
ビティ内に内蔵させる実施例ケ示したが。
In the above embodiments, both the hydrogen adsorbent and the moisture adsorbent are built into the cavity.

本発明においては水素g&着剤のみな内蔵させてもよい
In the present invention, only hydrogen g and adhesive may be incorporated.

〔効 果〕〔effect〕

(11封止の際にポリイミド樹脂等のソフトエラー防止
樹脂が熱で分解しても、この分解ガスをキャビティ内の
水YG吸着剤、水分吸着剤が吸着するので、H’t  
、HtOの存在によるホットキャリアによるデバイスの
動作不良を防止できる。
(Even if soft error prevention resin such as polyimide resin decomposes due to heat during sealing, the water YG adsorbent and moisture adsorbent in the cavity will adsorb this decomposed gas, so H't
, it is possible to prevent device malfunctions due to hot carriers due to the presence of HtO.

(2)水素吸着剤と水分吸着剤をキャビティ内に設けた
のでダイポンディングや封止の際にAu−8i共晶とH
t0との反応で放出されるHlやA u −Snプリホ
ームな用いてハーメチックシーリングする場合に添加す
るHtやシリコンナイトライド膜やセラミックキャップ
やベーストラップしたH、JPH20?答易に除去でき
る。
(2) Since a hydrogen adsorbent and a moisture adsorbent are provided inside the cavity, Au-8i eutectic and H
Hl released by reaction with t0, Ht added when hermetic sealing is performed using Au-Sn preform, silicon nitride film, ceramic cap, base trapped H, JPH20? It can be easily removed.

(;3)キャビティ内のH,、H,Oは容易に除去され
るので、H,、H,Oの存在により悪影響を受ける半導
体素子の不良を低減でき、q#にHt−HtOの存在と
ホットキャリアとによるデバイスの動作不良の問題を解
消できる。
(;3) Since H,, H, and O in the cavity are easily removed, it is possible to reduce defects in semiconductor devices that are adversely affected by the presence of H,, H, and O, and the presence of Ht-HtO in q# can be reduced. This solves the problem of device malfunctions caused by hot carriers.

(4)封止時のみならず封止後にも有効であり、簡単な
化学的手段により半導体装置の不良を低減できる。
(4) It is effective not only during sealing but also after sealing, and can reduce defects in semiconductor devices by simple chemical means.

以上本発明者によってなされた発明な実施例にもとづき
具体的に説明したが1本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲でトn々変史
可能であることはいうまでもない。
Although the invention has been specifically explained above based on the embodiments of the invention made by the present inventor, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Needless to say.

例えば、パッケージのペースに半導体ペレットを固定す
る接着剤1−なわちAJ’ペースト材料や低融点ガラス
材料中に前述した水素吸着剤な混入してもよい。また、
凹部な有しない平坦なセラミックベースにペレットを固
着しキャップ封比するノ(ッケージにおいて、水素吸着
剤、水分吸オ)剤をキャップに設けろこともできる。以
上のように、パッケージの形態、キャピテイの形態+ 
吸yli剤な設ける位置やその形成方法など必要に応じ
て区形できる。
For example, the above-mentioned hydrogen adsorbent may be mixed into the adhesive 1, ie, the AJ' paste material or the low melting point glass material, which fixes the semiconductor pellet to the package paste. Also,
It is also possible to provide the cap with a hydrogen adsorbent or water absorbent agent for fixing the pellets to a flat ceramic base having no recesses and sealing the cap. As mentioned above, package form, capacity form +
The location of the lysing agent and its formation method can be determined as necessary.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体装置のハーメ
チックタイプのパッケージに適用した場合について説明
してきたが、それに限定されるものではなく1例えばホ
ットキャリアによるデバイス動作不良パッケージ内水分
量・水素量が問題となる電子部品のパッケージなどに適
用できる。
In the above description, the invention made by the present inventor has been mainly applied to a hermetic type package for a semiconductor device, which is the background field of application, but the present invention is not limited thereto. It can be applied to electronic component packages where the amount of moisture and hydrogen in the package is a problem due to device malfunction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はサーディツプタイプの半導体パッケージの一部
切欠斜視図。 第2図は本発明の実施例を示す要部断面図。 第3図は本発明の実施例を示す側断面図。 第4図はDILCタイプの半導体パッケージの斜視図。 第5図は同タイプのパッケージに本発明を節用した実施
例を示す一部断面平面図。 第6図は本発明の実施例を示す側断面図である。 1・・・セラミックキャップ、2・・・低融点ガラス。 3・・・セラミックペース、4・・・半導体チップ、5
・・・リード、6・・・ボンディングワイヤ、7・・・
水素吸着剤、8・・・水分吸着剤、9・・・ポリイミド
樹脂、10・・・キャビティ、11・・・キャップ、1
2・・・ろう材。 13・・・リード、14・・・パッケージ、15・・・
配腺。 16・・・キャビティ、17・・・半導体チップ、18
・・・インナーリード、19・・・水素吸着剤、20・
・・段部。 21・・・水分吸着剤。 代理人 弁理士  高 橋 明 夫 (1)第  1 
 図 / 第  2 図 第  3  図 第  4  図 第  5  図 4 第  6 図 1頁の続き 0発 明 者 石原政道 小平市上水本町1450番地株式会 社日立製作所デバイス開発セン タ内 ■出 願 人 株式会社日立製作所 東京都千代田区神田駿河台四丁 目6番地
FIG. 1 is a partially cutaway perspective view of a cerdip type semiconductor package. FIG. 2 is a sectional view of a main part showing an embodiment of the present invention. FIG. 3 is a side sectional view showing an embodiment of the present invention. FIG. 4 is a perspective view of a DILC type semiconductor package. FIG. 5 is a partially sectional plan view showing an embodiment in which the present invention is applied to the same type of package. FIG. 6 is a side sectional view showing an embodiment of the present invention. 1...Ceramic cap, 2...Low melting point glass. 3... Ceramic paste, 4... Semiconductor chip, 5
...Lead, 6...Bonding wire, 7...
Hydrogen adsorbent, 8... Moisture adsorbent, 9... Polyimide resin, 10... Cavity, 11... Cap, 1
2... Brazing material. 13...Lead, 14...Package, 15...
Gland distribution. 16... Cavity, 17... Semiconductor chip, 18
...Inner lead, 19...Hydrogen adsorbent, 20.
・Danbe. 21... Moisture adsorbent. Agent Patent Attorney Akio Takahashi (1) No. 1
Figures / Figure 2 Figure 3 Figure 4 Figure 5 Figure 4 Figure 6 Continued from page 1 0 Inventor: Masamichi Ishihara Inside Hitachi, Ltd. Device Development Center, 1450 Kamizu Honmachi, Kodaira City ■Applicant: Hitachi, Ltd. Manufacturing location: 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo

Claims (1)

【特許請求の範囲】 1、 半導体パッケージキャピテイ内に水分吸着剤およ
び水素吸着剤を内蔵させたことを特徴とする牛導体装敢
。 2、水素吸着剤がマグネシウム又はマグネシウムの合金
である特FP icy求の範囲第1項記載の!t!導体
装置。 3、MIの合金がMJIとNi  とからなる合金であ
る特許請求の範囲wr、2項記載の半導体装置。 4、MPの合金がMIとCuとからなる合金である特#
’r&7求の範囲第2項記載の半導体装[1゜5、水素
吸着剤がPd金属である%許en求の範曲第1項記戦の
半導体装置。 6、水素吸着剤がLaCo合金である特許請求の範囲第
1項記載の半導体装置。 7、水分吸着剤が多孔質アルミナである特許請求の範囲
第1項記帳の半導体装置。
[Claims] 1. A conductor device characterized in that a moisture adsorbent and a hydrogen adsorbent are built into the semiconductor package cavity. 2. The hydrogen adsorbent is magnesium or an alloy of magnesium. T! conductor device. 3. The semiconductor device according to claim 2, wherein the alloy of MI is an alloy of MJI and Ni. 4.Special # where the alloy of MP is an alloy consisting of MI and Cu
The semiconductor device according to item 2 of the range of requirements [1°5, the semiconductor device according to item 1 of the range of requirements, in which the hydrogen adsorbent is Pd metal. 6. The semiconductor device according to claim 1, wherein the hydrogen adsorbent is a LaCo alloy. 7. The semiconductor device according to claim 1, wherein the moisture adsorbent is porous alumina.
JP8274183A 1983-05-13 1983-05-13 Semiconductor device Pending JPS59208860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8274183A JPS59208860A (en) 1983-05-13 1983-05-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8274183A JPS59208860A (en) 1983-05-13 1983-05-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59208860A true JPS59208860A (en) 1984-11-27

Family

ID=13782837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8274183A Pending JPS59208860A (en) 1983-05-13 1983-05-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59208860A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0472866A2 (en) * 1990-07-23 1992-03-04 National Semiconductor Corporation Ferroelectric device packaging techniques
US5491361A (en) * 1994-10-14 1996-02-13 The Aerospace Corporation Hydrogen out venting electronic package
JPH0878445A (en) * 1994-09-02 1996-03-22 Tomoegawa Paper Co Ltd Hermetically sealed package and its manufacture
EP0707360A1 (en) * 1994-10-11 1996-04-17 Corning Incorporated Impurity getters in laser enclosures
EP0837502A2 (en) * 1996-10-15 1998-04-22 Texas Instruments Inc. Improvements in or relating to hydrogen gettering
US5770473A (en) * 1993-07-14 1998-06-23 Corning Incorporated Packaging of high power semiconductor lasers
EP0993047A1 (en) * 1998-10-06 2000-04-12 Koninklijke Philips Electronics N.V. Semiconductor device with elements of integrated circuits of III-V group and means to prevent the pollution by hydrogen

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0472866A2 (en) * 1990-07-23 1992-03-04 National Semiconductor Corporation Ferroelectric device packaging techniques
EP0472866A3 (en) * 1990-07-23 1994-09-07 Nat Semiconductor Corp Ferroelectric device packaging techniques
US5770473A (en) * 1993-07-14 1998-06-23 Corning Incorporated Packaging of high power semiconductor lasers
JPH0878445A (en) * 1994-09-02 1996-03-22 Tomoegawa Paper Co Ltd Hermetically sealed package and its manufacture
EP0707360A1 (en) * 1994-10-11 1996-04-17 Corning Incorporated Impurity getters in laser enclosures
US5491361A (en) * 1994-10-14 1996-02-13 The Aerospace Corporation Hydrogen out venting electronic package
EP0837502A2 (en) * 1996-10-15 1998-04-22 Texas Instruments Inc. Improvements in or relating to hydrogen gettering
EP0837502A3 (en) * 1996-10-15 2004-06-02 Texas Instruments Inc. Improvements in or relating to hydrogen gettering
US6958260B2 (en) 1996-10-15 2005-10-25 Texas Instruments Incorporated Hydrogen gettering system
EP0993047A1 (en) * 1998-10-06 2000-04-12 Koninklijke Philips Electronics N.V. Semiconductor device with elements of integrated circuits of III-V group and means to prevent the pollution by hydrogen
US6703701B2 (en) 1998-10-06 2004-03-09 Koninklijke Philips Electronics N.V. Semiconductor device with integrated circuit elements of group III-V comprising means for preventing pollution by hydrogen

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