JPS5833856A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5833856A JPS5833856A JP13153081A JP13153081A JPS5833856A JP S5833856 A JPS5833856 A JP S5833856A JP 13153081 A JP13153081 A JP 13153081A JP 13153081 A JP13153081 A JP 13153081A JP S5833856 A JPS5833856 A JP S5833856A
- Authority
- JP
- Japan
- Prior art keywords
- package
- thermal expansion
- semiconductor device
- lead frame
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Compositions Of Macromolecular Compounds (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device.
従来、いわゆる７リツグチツプ型パツケージ構造におけ
るチップＩ？ｆリアとしては、一般にセライック材料が
使用されている。しかしながら、セラミック材料は製造
が複雑である上に、高価であるという欠点がある。Conventionally, a chip I? in a so-called 7-rig chip package structure. Ceracic material is generally used as the f rear. However, ceramic materials have the drawback of being complex to manufacture and expensive.
一方、ガラス入りエポキシ樹脂なパッケージ基板として
使用するととも提案しうるがこのガラス入りエポキシ樹
脂は熱膨張係数が高く、シリコン（８轟）の熱膨張係数
との差が大きいので、繰返し使用により熱な受けると、
半導体ベレット（チップ）およびリードフレームとパッ
ケージ基板との間に剥離が生じ、その剥離部分からの水
分の浸入により信頼性の低下を来た丁という欠点がある
。On the other hand, it may be proposed to use glass-filled epoxy resin as a package substrate, but this glass-filled epoxy resin has a high coefficient of thermal expansion and there is a large difference in thermal expansion coefficient from that of silicon (8 Todoroki), so it will not heat up due to repeated use. When you receive it,
There is a drawback that peeling occurs between the semiconductor pellet (chip) and lead frame and the package substrate, and reliability is reduced due to moisture infiltration from the peeled portion.
本発明の目的は、前記従来技術の欠点な解消し。The object of the present invention is to overcome the drawbacks of the prior art.
安価で、しかも半導体ペレットやリードフレームとの剥
−のないパッケージ構造を有する半導体装置な提供する
ことにある。It is an object of the present invention to provide a semiconductor device that is inexpensive and has a package structure that does not separate from semiconductor pellets or lead frames.
この目的な達成するため、本発明による牛導体装置ハ、
パッケージ基板が負の熱膨張係数臀持つ充填材な混入し
た樹脂材料よりなることな＊＊とするものである。In order to achieve this objective, the cattle conductor device according to the invention includes:
The package substrate is not made of a resin material mixed with a filler material having a negative coefficient of thermal expansion.
以下、本発明な図面に示す実施例にしたがってさらに説
明する。Hereinafter, the present invention will be further described according to embodiments shown in the drawings.
第１図は本発明による半導体装置の一実施例のｍ面図で
ある。FIG. 1 is an m-plane view of an embodiment of a semiconductor device according to the present invention.
本実施例における半導体装置はいわゆるチップキャリア
製パッケージよりなり、そのリードフレームｌはたとえ
ば４２アロイまたはコパールで作られ、このリードクレ
ームｌのインナリード側には、シリプン（ｓｉ）よりな
る半導体ペレット３が半田２によって接合されている。The semiconductor device in this embodiment is comprised of a so-called chip carrier package, and its lead frame l is made of, for example, 42 alloy or copal, and a semiconductor pellet 3 made of silicone (si) is placed on the inner lead side of this lead claim l. They are joined by solder 2.
また、前記半導体ペレット３およびリードフレームｌの
インナーリード部はプリモールド腫のパッケージ４およ
びゃヤング５により封止さｎている。Further, the semiconductor pellet 3 and the inner lead portion of the lead frame 1 are sealed with a pre-molded package 4 and a young 5.
本ＩＩｊｌｌ１例のパッケージ４はエポキシ樹脂中和。Package 4 of this IIjll1 example is epoxy resin neutralized.
負の熱膨張係数な持つ充填材、たとえば芳香族ボリアイ
ド’１４Ｈな混入した材料よりなる。したがって、パッ
ケージ４の１１％膨張係数は半導体ペレット３およびリ
ードフレームｌの七３に近いので、こｎらとパッケージ
４との剥離がなく、またこのような樹脂材料はセライッ
ク材料に比して非常に安価であるという重畳な利点が得
られる。It consists of a material mixed with a filler having a negative coefficient of thermal expansion, such as aromatic borioid '14H. Therefore, the 11% expansion coefficient of the package 4 is close to that of the semiconductor pellet 3 and the lead frame 1, so there is no peeling between these and the package 4, and such a resin material is much more effective than the ceramic material. It has the added advantage of being inexpensive.
第２ｗＡは本発明の第２実施例を示す断面図であ仝００
本実施では、半導体ペレット３はパッケージ４の上に取
り付けら−ｎ、＃牛導体ベレット３の電極パッドとリー
ドフレームｌのインナーリード部とはワイヤ６により電
気的に接続ざｎている。The second wA is a sectional view showing the second embodiment of the present invention.
In this embodiment, the semiconductor pellet 3 is mounted on a package 4, and the electrode pads of the conductor pellet 3 and the inner leads of the lead frame l are electrically connected by wires 6.
本実施例においても、パッケージ４は、エポキシ樹脂中
に、負の熱膨張係数を持つ充填材、たとえば芳香族ボリ
アイド樹脂さらに具体的には［６ｖｌａｒ（３ｅｇｉｓ
ｔｅｒｅｄ Ｔｒａｄａｍｉｒｋ ｏｆ 夙Ｉ、 Ｄｕ
ｐｏｎｔｄｅＮｅｍｏｕｒｓ ＆ Ｃｏｍｐａｎｙ）
ｆ混入した材料で作られている。したかって１本実施例
においても、安価で、しかもパッケージ４の剥離がない
という利点が得らｎる。In this embodiment as well, the package 4 is made of an epoxy resin containing a filler having a negative coefficient of thermal expansion, such as an aromatic polyamide resin, and more specifically [6vlar (3egis
tered Tradamirk of 夙I, Du
Pont de Nemours & Company)
Made with f-contaminated materials. Therefore, this embodiment also has the advantage that it is inexpensive and that the package 4 does not peel off.
なお、パッケージ４の構成材料としては、前記した−の
以外に、たとえばフッ素系ポリイミド樹脂中に負の熱膨
張係数を持つ充填材、たとえば芳香族ボリアイド樹ａｔ
混入したものを用いること等も可能である。In addition to the above-mentioned material, the package 4 may be made of a filler having a negative coefficient of thermal expansion, such as an aromatic polyamide resin, etc.
It is also possible to use a mixed substance.
本発明は実装密度の大きいチップキャリア製パッケージ
に適用すれば、樹脂材料の低コスト性をより有効に生か
すことかできるが、前記したようにワイヤボンディング
屋のもの等にも有利に適用できる。If the present invention is applied to a package made of a chip carrier with a high packaging density, the low cost property of the resin material can be more effectively utilized, but as described above, it can also be advantageously applied to a package made by a wire bonding shop.
以上説明したように１本発明によれば、パッケージが非
常圧安価な樹脂材料で構成されるので、半導体装置自体
のコストも大幅に低減でき、またパッケージと半導体ペ
レットあるいはり−ド７レームとの剥離も防止できる。As explained above, according to the present invention, the package is made of an extremely cheap resin material, so the cost of the semiconductor device itself can be significantly reduced, and the package and the semiconductor pellet or board frame can be combined together. Peeling can also be prevented.
第１１！！ｌＩは本発明による半導体装置の第１実施例
な示す断面図、第２図は本発明による半導体装置の第２
実施例な示す断面図である。
！・・・リードフレーム、２・・・半田％３・・・半導
体ペレット、４・・・パッケージ、５・・・キャップ、
６・・・ワイヤ。
代理人 弁理士 薄 １）利 幸
一−−
′・で−７・
第 １ 図11th! ! 1I is a sectional view showing a first embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing a second embodiment of a semiconductor device according to the present invention.
FIG. 3 is a sectional view showing an example. ! ...Lead frame, 2...Solder%3...Semiconductor pellet, 4...Package, 5...Cap,
6...Wire. Agent Patent attorney Susuki 1) Koichi Toshi --'・de-7・ Figure 1
Claims (1)
入した樹脂材料よりなることを特徴とする半導体装置。 λ パッケージが、芳香族ボリア〈ド欄脂ＩｋｆＩ１人
したエポキシ樹脂またはフッ素系ボリイ（ドａｍよりな
ることｔｔ４Ｉ黴とする＊＊請求の範８ＫＬ項記載の半
導体装置。 ３、パッケージがチップΦヤリアコパックージであるこ
とＶ＊黴とする特許請求の範囲第１項または＃Ｅ２項記
載の半導体装置。[Scope of Claims] 1. A semiconductor device characterized in that the package is made of a resin material mixed with a filler having a negative coefficient of thermal expansion. λ The package is made of an epoxy resin made of aromatic boria or a fluorocarbon resin. **The semiconductor device according to claim 8KL. 3. The semiconductor device according to claim 1 or #E2, wherein the semiconductor device is V* mold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13153081A JPS5833856A (en) | 1981-08-24 | 1981-08-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13153081A JPS5833856A (en) | 1981-08-24 | 1981-08-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5833856A true JPS5833856A (en) | 1983-02-28 |
Family
ID=15060219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13153081A Pending JPS5833856A (en) | 1981-08-24 | 1981-08-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5833856A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62141742A (en) * | 1985-12-17 | 1987-06-25 | Fujitsu Ltd | Package of semiconductor device |
| EP1772481A1 (en) * | 2005-10-05 | 2007-04-11 | The Goodyear Tire & Rubber Company | Tire with low thermal expansion component |
-
1981
- 1981-08-24 JP JP13153081A patent/JPS5833856A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62141742A (en) * | 1985-12-17 | 1987-06-25 | Fujitsu Ltd | Package of semiconductor device |
| EP1772481A1 (en) * | 2005-10-05 | 2007-04-11 | The Goodyear Tire & Rubber Company | Tire with low thermal expansion component |
| US7347242B2 (en) | 2005-10-05 | 2008-03-25 | The Goodyear Tire & Rubber Company | Tire with low thermal expansion component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH11514149A (en) | Electronic package with improved thermal properties | |
| JPH02130865A (en) | Flag-less semiconductor package | |
| JPS5992556A (en) | Semiconductor device | |
| JPH05211262A (en) | Resin sealed semiconductor device | |
| JPS5833856A (en) | Semiconductor device | |
| JPS60171733A (en) | Semiconductor device | |
| JPH11297917A (en) | Semiconductor device and its manufacture | |
| JPS628033B2 (en) | ||
| JPH08115941A (en) | Semiconductor device | |
| CA2017080A1 (en) | Semiconductor device package structure | |
| JPS6329960A (en) | Lead frame for resin seal type semiconductor device | |
| JPH01282846A (en) | Hybrid integrated circuit | |
| JP3145892B2 (en) | Resin-sealed semiconductor device | |
| JP2765265B2 (en) | Lead frame for semiconductor device | |
| JPH01204453A (en) | Structure of pin grid array using resin substrate | |
| JPS6169162A (en) | Semiconductor device | |
| JPH0433357A (en) | Structure of multichip package | |
| KR940010298A (en) | Semiconductor package and manufacturing method thereof | |
| JPH02178953A (en) | Resin-sealed semiconductor device | |
| KR200154510Y1 (en) | Lead on chip package | |
| JPH08264686A (en) | Resin sealed semiconductor device and its manufacture | |
| JPH01171251A (en) | Pin grid array package | |
| JPH0870089A (en) | Semiconductor device and its manufacture | |
| JPH0451554A (en) | Lead frame | |
| JPH04252061A (en) | Multichip type semiconductor device |