JPS58223352A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58223352A JPS58223352A JP57107208A JP10720882A JPS58223352A JP S58223352 A JPS58223352 A JP S58223352A JP 57107208 A JP57107208 A JP 57107208A JP 10720882 A JP10720882 A JP 10720882A JP S58223352 A JPS58223352 A JP S58223352A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- base body
- resin
- cap
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置 ° ゛に関するもの
であり、特に大規模集積回路、いわゆるＬＳＩに於ける
放射線入射による誤動作の防止を容易に実現する為の半
導体装置用パッケージを提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and in particular provides a package for semiconductor devices that easily prevents malfunctions caused by radiation incidence in large-scale integrated circuits, so-called LSIs. It is something.
従来の半導体パッケージを第１図をもとに説明する。第
１図は、ＬＳＩペレットを塔載したセラミックパッケー
ジの断面図を示すものである。第１図に於いてＬＳＩペ
レット１が、セラミックパッケージ基本部２に接着固定
されたのち、外部リード３に接続される内部り−１・４
とＬＳＩぺｌ／ 、７ト１の電極とがＡｐ線６を介して
接続される。史に、キヤ、プロの一部に設けらハ、たハ
ンダ７を加熱せしめ、ギャップ６にて気密封正さ７′１
．る。A conventional semiconductor package will be explained based on FIG. FIG. 1 shows a cross-sectional view of a ceramic package on which LSI pellets are mounted. In FIG. 1, after the LSI pellet 1 is adhesively fixed to the ceramic package basic part 2, the internal leads 1 and 4 are connected to the external leads 3.
and the electrode of LSI Pel/7 and 1 are connected via Ap line 6. In history, the solder 7 provided in a part of the camera was heated, and the gap 6 was hermetically sealed 7'1.
．． Ru.
近年、ＬＳＩにおいては、益々構成素子の微細化、高密
度化、高集積化に伴い、６４にピッｉ・。In recent years, as LSI components have become increasingly finer, denser, and more highly integrated, the number of chips has increased to 64.
２５６にビットメモリに代表され、る様に、人界Ｍ″メ
モリが実現されている。これらメモリの記憶動作は、半
導体基板に回路構成したフリップフロップの状態又は半
導体基板表面に形成した電荷蓄積コンデンサに蓄えた電
荷量によって行っており、素子の微細化により駆動電流
の微小化及び蓄積ココンデンサの微小化に伴い、僅か々
電荷変動により記憶動作を誤る事になる。この誤動作の
原因となる電荷変動は、一般に論じられている様にパッ
ケージ材料に含まれる微量のトリウム、ジルコニウム、
ウラン等の放射性元素から発生するα線が半導体基板に
照射される事によるものである。Human world M'' memories have been realized, as represented by the bit memory in 256.The storage operation of these memories is in the state of a flip-flop circuit configured on a semiconductor substrate, or in the form of a charge storage capacitor formed on the surface of a semiconductor substrate. As the drive current and storage co-capacitor become smaller due to the miniaturization of elements, slight fluctuations in charge can cause errors in memory operation.The charge that causes this malfunction The fluctuations are caused by trace amounts of thorium, zirconium, and
This is due to alpha rays generated from radioactive elements such as uranium being irradiated onto the semiconductor substrate.
以上の誤動作を防止する為には、パッケージ月料中に含
まれる放射性元素を除去すれば良いが、技術的に極めて
困離とされている。又他の方法と（７て絶縁性樹脂によ
るα線の遮蔽又は減衰によって半導体基板へのα線の照
射を阻止する方法が有力校されている。本発明は、半導
体ペレットを収納するパッケージに、α線阻止用の樹脂
を一体化せしめ、α線によるＬＳＩの誤動作を容易に防
止できる半導体装置用パッケージを提供する事を目的と
するものである。In order to prevent the above-mentioned malfunctions, it would be possible to remove the radioactive elements contained in the package monthly charge, but this is technically extremely difficult. In addition, there are other effective methods (7) of preventing irradiation of the semiconductor substrate with α-rays by shielding or attenuating the α-rays with an insulating resin. It is an object of the present invention to provide a package for a semiconductor device that integrates a resin for blocking alpha rays and can easily prevent malfunctions of LSIs caused by alpha rays.
以下本発明の一実施例を第２図に基づき説明する。An embodiment of the present invention will be described below with reference to FIG.
第２図Ａ、 Ｂに於いて１〜６は第１図と同様である
。先ず、第２図人においてキャップ６の接着面ＶＣは、
パンケージ基体部との環状封止接着面７にて囲ｉ ｈ、
る主面８上の一部には、熱加硬化性の樹脂９を設けであ
る。ここで、樹脂９は、パッケージ基体部２に接着固定
された時に基体部２に接着固定された半導体ペレット１
の位置に対応する部分に設けである。ここで樹脂の性質
としては、α線の含有量が少なくかつα線に対する阻止
能力の高いものが好ましい、本実施例では、エホキシ樹
脂を用いている。樹脂９の厚さ及び形状は、前記半導体
ペレット並びに後述のＡ７ｉ 線を損傷しない程度とす
る。In FIGS. 2A and 2B, 1 to 6 are the same as in FIG. 1. First, in Figure 2, the adhesive surface VC of the cap 6 is
Surrounded by the annular sealing adhesive surface 7 with the pan cage base portion,
A thermosetting resin 9 is provided on a part of the main surface 8. Here, when the resin 9 is adhesively fixed to the package base part 2, the semiconductor pellet 1 that is adhesively fixed to the base part 2 is
It is provided in the part corresponding to the position of. Here, as for the properties of the resin, it is preferable that the resin has a low content of alpha rays and a high blocking ability for alpha rays, and in this example, an epoxy resin is used. The thickness and shape of the resin 9 are set so as not to damage the semiconductor pellet and the A7i wire described below.
次に第２図Ｂに於いて、ＬＳＩペレッｌ−１１７１パツ
ケージの基本部２に接着固定され、ＬＳＩベレット１の
電極と、パッケージの外部リード３Ｑ：１、リード線５
及び内部リード４を介し電気的に接ｈ；されている。更
に前述の樹脂９を載置せしめたギヤ、プロと一体化さ７
″１７る。次にパッケージ内を気密化封止する為に、接
着剤７に熱印加し、封止する。ここで接着剤７は通常ハ
ンダ若しくに１樹脂をを用いる。本実施例に於いては、
ハンダを用いている。一般的にギャップ６とパッケージ
基体２とを一体化接着する場合、これらを全体にＡ ｆ
Ａ！雰囲気に放置する。これにより、高部放置の初期段
階に於いて、前記樹脂９がゲル化し、ＬＳＩペレット１
を包み込む。更に樹脂の温度が−１−昇すると、本樹脂
は硬化を始めると同時に前記ハンダが溶融し、ギャップ
６と基体２の封止が行わ）１．る。Next, in FIG. 2B, the LSI pellet 1-1171 is adhesively fixed to the base part 2 of the package, and the electrodes of the LSI pellet 1, the external lead 3Q:1 of the package, and the lead wire 5
and are electrically connected via internal leads 4. Furthermore, the gear on which the aforementioned resin 9 is placed is integrated with the professional 7.
17.Next, in order to hermetically seal the inside of the package, heat is applied to the adhesive 7 to seal it.Here, the adhesive 7 is usually solder or resin. In that case,
Uses solder. Generally, when bonding the gap 6 and the package base 2 together, they are bonded together as a whole.
A! Leave it in the atmosphere. As a result, the resin 9 gels and the LSI pellet 1
wrap around. When the temperature of the resin further increases by -1, the resin begins to harden and at the same time the solder melts, sealing the gap 6 and the base 2).1. Ru.
以上の様にして封止の終了したパッケージの様子を第３
図に示す。ゲル化し更に細形硬化した樹脂９がＬＳＩペ
レットを完全封入している。ここで、樹脂の形状は、樹
脂の量、温度、ペレットの形状更に樹脂の種類によって
異なってくるが、ＬＳＩペレット１を包み込んでしまえ
ば問題なく硬化時の形状は特に問題ない。The state of the package that has been sealed in the above manner is shown in the third image.
As shown in the figure. The resin 9, which has been gelatinized and further hardened into a thin shape, completely encapsulates the LSI pellet. Here, the shape of the resin varies depending on the amount of resin, the temperature, the shape of the pellet, and the type of resin, but once the LSI pellet 1 is wrapped, there is no problem and there is no particular problem with the shape when cured.
以上の様に本発明によれは、パッケージ制料に含有され
る放射性元素から照射されるα線を阻止する小ができる
。As described above, according to the present invention, it is possible to block the alpha rays irradiated from the radioactive elements contained in the package material.
第１図に従来のパッケージの断面図、第２図人は本発明
のパッケージにおけるキャップの平面図、第２図Ｂ、第
３図は本発明の一実施例のパッケージの製造工程図であ
る。
１・・・・・半導体ペレット、２・・・・・・パッケー
ジ基体、６・・・・・・ギャップ、９・・・・・・樹脂
。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第
１ 図
■ ［FIG. 1 is a sectional view of a conventional package, FIG. 2 is a plan view of a cap in a package of the present invention, and FIGS. 2B and 3 are manufacturing process diagrams of a package according to an embodiment of the present invention. 1... Semiconductor pellet, 2... Package base, 6... Gap, 9... Resin. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure ■ [
Claims (1)
記キャップと基体部間の前記半導体ペレット主面上に熱
硬化性樹脂を載置したことを特徴とした半導体装置。[Scope of Claims] A base portion on which a semiconductor pellet is mounted and fixed; a gasket for hermetically sealing the semiconductor pellet; A semiconductor device characterized by having a synthetic resin placed thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57107208A JPS58223352A (en) | 1982-06-21 | 1982-06-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57107208A JPS58223352A (en) | 1982-06-21 | 1982-06-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58223352A true JPS58223352A (en) | 1983-12-24 |
Family
ID=14453217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57107208A Pending JPS58223352A (en) | 1982-06-21 | 1982-06-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58223352A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITUB20155681A1 (en) * | 2015-11-18 | 2017-05-18 | St Microelectronics Srl | RADIATION-RESISTANT ELECTRONIC DEVICE AND METHOD TO PROTECT AN ELECTRONIC DEVICE FROM IONIZING RADIATION |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55128851A (en) * | 1979-03-28 | 1980-10-06 | Hitachi Ltd | Semiconductor memory device |
| JPS5658249A (en) * | 1979-10-19 | 1981-05-21 | Hitachi Ltd | Package for integrated circuit |
| JPS56148852A (en) * | 1980-04-21 | 1981-11-18 | Nec Corp | Semiconductor device |
-
1982
- 1982-06-21 JP JP57107208A patent/JPS58223352A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55128851A (en) * | 1979-03-28 | 1980-10-06 | Hitachi Ltd | Semiconductor memory device |
| JPS5658249A (en) * | 1979-10-19 | 1981-05-21 | Hitachi Ltd | Package for integrated circuit |
| JPS56148852A (en) * | 1980-04-21 | 1981-11-18 | Nec Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITUB20155681A1 (en) * | 2015-11-18 | 2017-05-18 | St Microelectronics Srl | RADIATION-RESISTANT ELECTRONIC DEVICE AND METHOD TO PROTECT AN ELECTRONIC DEVICE FROM IONIZING RADIATION |
| US10319686B2 (en) | 2015-11-18 | 2019-06-11 | Stmicroelectronics S.R.L. | Radiation-hard electronic device and method for protecting an electronic device from ionizing radiation |
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