JPS60160626A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60160626A
JPS60160626A JP59015618A JP1561884A JPS60160626A JP S60160626 A JPS60160626 A JP S60160626A JP 59015618 A JP59015618 A JP 59015618A JP 1561884 A JP1561884 A JP 1561884A JP S60160626 A JPS60160626 A JP S60160626A
Authority
JP
Japan
Prior art keywords
package
lead
thin film
semiconductor chip
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59015618A
Other languages
Japanese (ja)
Inventor
Shigeki Harada
Kiyoshi Muratake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59015618A priority Critical patent/JPS60160626A/en
Publication of JPS60160626A publication Critical patent/JPS60160626A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

PURPOSE:To obtain an excellent alpha-ray shielding effect by mounting a resin film having a thin film lead on a semiconductor chip having a bump electrode in such a fashion as covering the surface of semiconductor chip and by mounting a semiconductor chip within a package so that a thin film lead of resin film is clamped onto an inner lead of package. CONSTITUTION:A polyimide film 11 having a thin film lead 10 is mounted on a semiconductor chip 7 having a bump electrode 9 by clamping a bump electrode 9 and thin film lead 10 by, for example, the thermal pressurizing bonding and a semiconductor chip 7 is mounted within a package 1 with the polyimide film 11 surface placed upward by thermally bonding a thin film lead 10 of polyimide film 11 on the inner lead 4 of package 1. A conductive bonding agent 6 is used for giving a potential to a semiconductor substrate forming a chip 1 through a chip stage 5 and realizing heat radiation through the package.
JP59015618A 1984-01-31 1984-01-31 Semiconductor device Pending JPS60160626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59015618A JPS60160626A (en) 1984-01-31 1984-01-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59015618A JPS60160626A (en) 1984-01-31 1984-01-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60160626A true JPS60160626A (en) 1985-08-22

Family

ID=11893693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59015618A Pending JPS60160626A (en) 1984-01-31 1984-01-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60160626A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0388345A (en) * 1989-08-31 1991-04-12 Toshiba Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0388345A (en) * 1989-08-31 1991-04-12 Toshiba Corp Semiconductor integrated circuit device

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