JPS6127663A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6127663A JPS6127663A JP14810184A JP14810184A JPS6127663A JP S6127663 A JPS6127663 A JP S6127663A JP 14810184 A JP14810184 A JP 14810184A JP 14810184 A JP14810184 A JP 14810184A JP S6127663 A JPS6127663 A JP S6127663A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- package
- film
- gas
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/20—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device gaseous at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3164—Partial encapsulation or coating the coating being a foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 （発明の属する技術分野） 本発明は半導体集積回路用パッケージの構造に関する。[Detailed description of the invention] (Technical field to which the invention pertains) The present invention relates to the structure of a package for a semiconductor integrated circuit.
（従来技術の説明）
従来この種の半導体パッケージは半導体チップ表面に対
するパッケージ構成材料の接触状態により次の２種に大
別される。(Description of Prior Art) Conventionally, this type of semiconductor package is roughly classified into the following two types depending on the contact state of the package constituent materials with the surface of the semiconductor chip.
（ｌ）二パッケージ構成材料がチップに直接接触するタ
イプ。(l) A type in which the two package constituent materials directly contact the chip.
例としてモールドパッケージや第１図のように樹脂４を
ボッティングしてチップ１および配線パターン２を有す
るフィルム３の先端部を保護しているタイプのものが挙
げられる。この種のパッケージは、一般にパッケージ自
体が安価で組立工程が自動化しやすい特徴をもっている
。しかし、その反面欠点としてチップパッドのポンディ
ング部へのパッケージ材料の収縮のストレスによる断線
やパッケージ材料の含む不純物による汚染による特性の
劣化や耐湿性などの問題があシ高信頼性を必要とする半
導体装置には適していない。Examples include a molded package and a type shown in FIG. 1 in which resin 4 is potted to protect the tip of a film 3 having a chip 1 and a wiring pattern 2. This type of package generally has the characteristics that the package itself is inexpensive and the assembly process can be easily automated. However, on the other hand, there are disadvantages such as disconnection due to the stress of shrinkage of the package material on the bonding part of the chip pad, deterioration of characteristics due to contamination due to impurities contained in the package material, and moisture resistance, which requires high reliability. Not suitable for semiconductor devices.
（２）：チップを中空状の容器の中に収めるタイプ。(2): A type in which the chip is housed in a hollow container.
第２図のようにセラミックなどのケース３の中にチップ
ｌを収め窒素や乾燥空気５のもとてセラミック系のキャ
ップｌＯで封止するタイプである。As shown in FIG. 2, this is a type in which a chip 1 is housed in a case 3 made of ceramic or the like and sealed with a cap 10 made of ceramic to prevent nitrogen or dry air 5 from entering.
又、チップｌの電極と配線パターン２とはボンディング
ワイヤ８で接続されている。この種のパッケージは（１
）のタイプとは逆で信頼性は高い反面パッケージが高価
で組立工程も複雑となる欠点をもっている。Further, the electrodes of the chip 1 and the wiring pattern 2 are connected by bonding wires 8. This kind of package is (1
) type, it is highly reliable but has the disadvantage that the package is expensive and the assembly process is complicated.
（発明の目的および構成）
本発明は、半導体チップをそれを保持しパッドよりの配
線パターンを形成する支持体と共に柔軟なフィルムによ
り包み囲み、その内部へチップの特性に対し不活性な気
体を封入しふくらませた構造をとることにより、上記の
二種のパッケージの欠点を解決し、ボンディング部への
ストレスチップ表面の汚染を軽減し、耐湿性がある信頼
性の高い安価で組立工程の簡便な半導体集積回路パッケ
ージを提供するものである。(Objective and Structure of the Invention) The present invention involves wrapping a semiconductor chip together with a support that holds it and forming a wiring pattern from pads in a flexible film, and filling the interior with an inert gas that is compatible with the characteristics of the chip. The inflated structure solves the drawbacks of the two types of packages mentioned above, reduces stress on the bonding area and contamination of the chip surface, and creates a semiconductor that is moisture resistant, reliable, inexpensive, and has a simple assembly process. The company provides integrated circuit packages.
（実施例） 次に本発明の実施例について図面を診照して説明する。(Example) Next, embodiments of the present invention will be described with reference to the drawings.
第３図は、本発明の半導体集積回路パッケージの第１の
実施例の断面図である。半導体チップｌのパッドは支持
体である中層フィルム３上の配線パターン２により外部
とのコンタクトがとられる。封入気体の窒素５は、チッ
プｌの表面を保護すると同時に中層フィルム３に接着さ
れた柔軟な上層フィルム９と下層フィルム６とをふくら
ませ外部からの圧力、衝撃からチップｌを守るパッケー
ジ構造を形成する。FIG. 3 is a sectional view of the first embodiment of the semiconductor integrated circuit package of the present invention. The pads of the semiconductor chip 1 are brought into contact with the outside through a wiring pattern 2 on an intermediate film 3 serving as a support. The nitrogen gas 5 protects the surface of the chip 1 and at the same time inflates the flexible upper film 9 and lower film 6 bonded to the middle film 3 to form a package structure that protects the chip 1 from external pressure and impact. .
このように形成された半導体装置において、チップ１は
窒素５の雰囲気中にあるため樹脂などで固められたパッ
ケージのように、ボンディング部への樹脂の収縮による
ストレスや不純物の影響がなく、信頼性が高まる。In the semiconductor device formed in this way, since the chip 1 is in an atmosphere of nitrogen 5, unlike a package hardened with resin, the bonding part is not affected by stress due to resin contraction or impurities, and reliability is improved. increases.
また、パッケージの組立工程は、従来のテープキャリア
と同じ構造の中層フィルム３上の配線パターン２のチッ
プバッドへの熱圧着の後窒素５を充てんしながら上層フ
ィルム４と下層フィルム９を中層のテープ３へ密ぺい接
着すれば完成し、自動化が容易である。In addition, in the package assembly process, the wiring pattern 2 on the middle layer film 3, which has the same structure as a conventional tape carrier, is thermocompression bonded to the chip pad, and then the upper layer film 4 and the lower layer film 9 are attached to the middle layer tape while being filled with nitrogen 5. It is completed by tightly gluing it to 3, and it is easy to automate.
次に第４図は第２の実施例の断面図である。第１例の構
造に加え支持体の中層フィルム３と下層フィルム６との
間にも配線パターン７を有することで半導体チップ１の
裏面との１気的接続を可能にし、機械的にもチップ１を
固定する働きをする。Next, FIG. 4 is a sectional view of the second embodiment. In addition to the structure of the first example, by having the wiring pattern 7 between the middle layer film 3 and the lower layer film 6 of the support, it is possible to make a one-dimensional connection with the back surface of the semiconductor chip 1, and mechanically the chip 1 It works to fix.
また、組立工程では中層フィルム３上の配線パターン２
のチップｌのパッドへの熱圧着までは従来通りで、その
後導電性接着剤などでチップ１の裏面と下層フィルム６
上の配線パターン７を接着し、さらに上層フィルム９と
下層フィルム６を窒素５を充てんしながら、中層フィル
ム３へ接着することによりパッケージを容易に形成する
ことが可能である。In addition, in the assembly process, the wiring pattern 2 on the middle layer film 3 is
The process up to thermocompression bonding of the chip 1 to the pad is the same as before, and then the back surface of the chip 1 and the lower layer film 6 are bonded with conductive adhesive etc.
A package can be easily formed by bonding the upper wiring pattern 7 and then bonding the upper layer film 9 and the lower layer film 6 to the middle layer film 3 while filling them with nitrogen 5.
（発明の効果）
本発明は以上説明したように半導体チップを保持しパッ
ドよりの配線パターンを形成する支持体とそれを包む柔
軟なフィルムとそのフィルム内に封止されフィルムをふ
くらませるチップ特性に対し不活性な気体とにより構成
することにより信頼性の高い安価で組立工程の容易なパ
ッケージを提供することができる。(Effects of the Invention) As explained above, the present invention provides a support that holds a semiconductor chip and forms a wiring pattern from pads, a flexible film that wraps it, and a chip that is sealed within the film and expands the film. By using an inert gas, it is possible to provide a package that is highly reliable, inexpensive, and easy to assemble.
第１図は従来のテープキャリアパッケージの断面図であ
る。第２図は従来のセラミツクツ（ツケージの断面図で
ある。第３図は本発明の半導体集積回路用パッケージの
第１の実施例の断面図である。
第４図は本発明の第２の実施例の断面図である。
尚、図において、１・・・・・・半導体チップ、２・・
・・・・配線パターン、３・・・・・・フィルム、４・
・・・・・樹脂、５・・・・・・窒素等の不活性ガス、
６・・・・・・下層フィルム、７、・・・・・配線パタ
ーン、８・・・・・・ボンディングワイも９・・・・・
・上層フィルム、１０・・・・・・キャップ。
卒３回
卒４−凹FIG. 1 is a cross-sectional view of a conventional tape carrier package. FIG. 2 is a sectional view of a conventional ceramic cage. FIG. 3 is a sectional view of a first embodiment of a semiconductor integrated circuit package of the present invention. FIG. 4 is a sectional view of a second embodiment of the present invention. It is a sectional view of an example. In the figure, 1... semiconductor chip, 2...
...Wiring pattern, 3...Film, 4.
... Resin, 5 ... Inert gas such as nitrogen,
6...lower film, 7...wiring pattern, 8...bonding wire 9...
- Upper layer film, 10...cap. 3rd year graduate 4-concave
Claims (1)
の配線パターンを形成する支持体と、該半導体チップお
よび該支持体を上下より包み囲む柔軟なフィルムとを有
し、該フィルム内へチップ特性に対し不活性な気体を導
入し、該フィルムをふくらませたことを特徴とする半導
体集積回路。It has a semiconductor chip, a support that holds the semiconductor chip and forms a wiring pattern from pads, and a flexible film that wraps and surrounds the semiconductor chip and the support from above and below. A semiconductor integrated circuit characterized in that the film is expanded by introducing an inert gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14810184A JPS6127663A (en) | 1984-07-17 | 1984-07-17 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14810184A JPS6127663A (en) | 1984-07-17 | 1984-07-17 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6127663A true JPS6127663A (en) | 1986-02-07 |
Family
ID=15445263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14810184A Pending JPS6127663A (en) | 1984-07-17 | 1984-07-17 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127663A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GR890100475A (en) * | 1988-11-10 | 1991-12-30 | Rheinmetall Gmbh | Accelaration resistant packing for complete circuits and fabrication method therefor |
| EP0528684A2 (en) * | 1991-08-20 | 1993-02-24 | Kabushiki Kaisha Toshiba | Thin type semiconductor device |
| EP2270854A3 (en) * | 2004-09-14 | 2012-04-25 | Semiconductor Energy Laboratory Co, Ltd. | Wiresless chip and manufacturing method of the same |
| CN105706229A (en) * | 2013-11-07 | 2016-06-22 | 大赛璐赢创株式会社 | Sealing member, sealed substrate sealed by sealing member, and method for manufacturing same |
-
1984
- 1984-07-17 JP JP14810184A patent/JPS6127663A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GR890100475A (en) * | 1988-11-10 | 1991-12-30 | Rheinmetall Gmbh | Accelaration resistant packing for complete circuits and fabrication method therefor |
| EP0528684A2 (en) * | 1991-08-20 | 1993-02-24 | Kabushiki Kaisha Toshiba | Thin type semiconductor device |
| US5448106A (en) * | 1991-08-20 | 1995-09-05 | Kabushiki Kaisha Toshiba | Thin semiconductor integrated circuit device assembly |
| EP2270854A3 (en) * | 2004-09-14 | 2012-04-25 | Semiconductor Energy Laboratory Co, Ltd. | Wiresless chip and manufacturing method of the same |
| US8698262B2 (en) | 2004-09-14 | 2014-04-15 | Semiconductor Energy Laboratory Co., Ltd. | Wireless chip and manufacturing method of the same |
| CN105706229A (en) * | 2013-11-07 | 2016-06-22 | 大赛璐赢创株式会社 | Sealing member, sealed substrate sealed by sealing member, and method for manufacturing same |
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