JPS63133653A - Optically erasable semiconductor storage device - Google Patents
Optically erasable semiconductor storage deviceInfo
- Publication number
- JPS63133653A JPS63133653A JP28242786A JP28242786A JPS63133653A JP S63133653 A JPS63133653 A JP S63133653A JP 28242786 A JP28242786 A JP 28242786A JP 28242786 A JP28242786 A JP 28242786A JP S63133653 A JPS63133653 A JP S63133653A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor memory
- resin material
- memory chip
- erasable semiconductor
- photo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 9
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000000465 moulding Methods 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000004035 construction material Substances 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 5
- 238000002844 melting Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical class [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- -1 for example Polymers 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、情報消去が光でなされる光消去型半導体メモ
リ装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a photo-erasable semiconductor memory device in which information is erased using light.
従来の技術
従来の光消去型半導体メモリ装置のパッケージは、主と
してセラミックパッケージとされている。2. Description of the Related Art Conventional packages for photo-erasable semiconductor memory devices are mainly ceramic packages.
このセラミックパッケージは、セラミック裂のベースと
キャップ、リードフレーム、透光窓形成用の石英ガラス
およびベースとキャップ、石英ガラスとキャップを接着
するための鉛低融点ガラスなどの構成用部材からなって
いる。This ceramic package consists of structural members such as a ceramic cracked base and cap, a lead frame, quartz glass for forming a transparent window, the base and cap, and lead low-melting glass for bonding the quartz glass and cap. .
このセラミックパッケージに半導体メモリチップを搭載
して光消去型半導体メモリ装置を製作する場合、４００
〜５００’Ｃの温度に保たれたベース上に金又は銀の粉
末を主体とするペーストを塗布し、このペースト面上に
半導体メモリチップ（シリコン製）を載せ、さらに、数
回こすりつけてベースに固着するときの熱処理、ベース
の上にキャップを載せ、さらに、キャップとベースの合
わせずれを防ぐとともに、適当な加圧力を与えるために
、スプリングクリップで固定したのち、４００〜５００
°Ｃのオーブン中に通し、キャップとベースのシール部
に配設した低融点ガラスの溶融により、半導体メモリチ
ップを封じ込めるときの熱処理が不可欠である。また、
この熱処理に要する時間は数十分にも及んでいる。When manufacturing a photo-erasable semiconductor memory device by mounting a semiconductor memory chip on this ceramic package, 400
A paste consisting mainly of gold or silver powder is applied onto a base kept at a temperature of ~500'C, a semiconductor memory chip (made of silicone) is placed on the paste surface, and the base is rubbed several times. Heat treatment for fixing, placing the cap on the base, fixing with a spring clip to prevent misalignment of the cap and base and applying appropriate pressure, then
Heat treatment is essential when enclosing the semiconductor memory chip by passing it through a °C oven and melting the low melting point glass disposed in the cap and base seals. Also,
The time required for this heat treatment extends to several tens of minutes.
発明が解決しようとする問題点
半導体メモリチップでも他の半導体集積回路チップと同
様にパターンの微細化が急速に進んでお沙、これに伴っ
て、半導体メモリチップの二次元的な寸法のみならず、
三次元的な寸法の縮小化が進み、半導体メモリ素子の特
性は従来以上に熱的な影響あるいは熱応力にもとづく機
械応力的な影響を受けやすくなっている。Problems to be Solved by the Invention As with other semiconductor integrated circuit chips, the pattern size of semiconductor memory chips is rapidly becoming finer. ,
As three-dimensional dimensions continue to shrink, the characteristics of semiconductor memory devices are becoming more susceptible to thermal influences or mechanical stresses based on thermal stress than ever before.
したがって、微細パターンを有する光消去型半導体メモ
リチップを４００〜ＳＯＯ°Ｃの熱処理を数十分間にわ
たり施すことが必要な妄ラミックパッケージに搭載した
場合、特性に重大な影響が及ぼされてしまう。Therefore, when a photo-erasable semiconductor memory chip having a fine pattern is mounted in a lamic package that requires heat treatment at 400 to SOO° C. for several tens of minutes, the characteristics will be seriously affected.
さらにセラミックパッケージの構成部材は、そのいずれ
もが高価な材料であシ、半導体チップを搭載するパッケ
ージが高価となり、製品価格の引き下げの障害となる問
題も存在した。Furthermore, all of the constituent members of the ceramic package are made of expensive materials, making the package in which the semiconductor chip is mounted expensive, which poses a problem that becomes an obstacle to lowering the product price.
問題点を解決するだめの手段
本発明は、上述した問題を解決するだめに、セラミック
材料、低融点ガラスあるいは石英ガラスなどの高価な部
材の使用を避け、プラスチックパッケージに光消去型半
導体メモリチップを搭載した構造を実現するものである
。すなわち、本発明の光消去型半導体メモリ装置は、リ
ードフレームの基板支持部に光消去型半導体メモリチッ
プが固着され、同光消去型半導体メモリチップ上の電極
とインナリード間が金属Ｓ線で接続されてなる組立構体
を樹脂で封止するとともに、誘記光消去型半導体メモリ
チップ上の樹脂部分が透明もしくは半透明の樹脂体の埋
め込みで構成されて透光窓を形成した構造となっている
。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention avoids the use of expensive materials such as ceramic materials, low-melting glass, or quartz glass, and provides a photo-erasable semiconductor memory chip in a plastic package. This is to realize the installed structure. That is, in the photo-erasable semiconductor memory device of the present invention, a photo-erasable semiconductor memory chip is fixed to a substrate supporting portion of a lead frame, and an electrode on the photo-erasable semiconductor memory chip and an inner lead are connected by a metal S wire. The assembled structure is sealed with resin, and the resin part on the photo-erasable semiconductor memory chip is embedded with a transparent or translucent resin body to form a light-transmitting window. .
作 用
本発明の光消去型半導体メモリ装置は、樹脂封止構造で
あるため、これの裏作過程で必要とされる熱処理の温度
を引き下げることができる。また、高価な構成部材を用
いることなく製作することが可能である。Function: Since the photo-erasable semiconductor memory device of the present invention has a resin-sealed structure, it is possible to lower the temperature of the heat treatment required in the back-up process. Furthermore, it can be manufactured without using expensive components.
実施例
以下に本発明の光消去型半導体メモリ装置を窓つきプラ
スチック封止形デュアルインラインパッケージ（以下は
窓つきＤＩＰと記す）構造として実現する実施例を第１
図〜第４図を参照して説明する。Embodiment The following is a first embodiment in which the photo-erasable semiconductor memory device of the present invention is realized as a windowed plastic sealed dual in-line package (hereinafter referred to as windowed DIP) structure.
This will be explained with reference to FIGS.
第１図〜第４図は窓つきＤＩＰ構造を実現するための工
程図を示す。先ず、第１図で示すように、鉄−ニッケル
（４２ωｔ％）合金板または銅−錫合金板を加工し、基
板支持部１、インナーリード２を形成したリードフレー
ムの基板支持部１の上に半導体メモリチップ３をダイボ
ンドする。ダイボンド方法は金−シリコン共晶法、銀ペ
ースト法のどちらでも良く、前者の場合には４００〜４
８０’Ｃ位の還元雰囲気中でダイボンドする。また、後
者の場合には室温で接着し、さらに１６０〜３００°Ｃ
の範囲の空気中又は窒素雰囲気中でペーストの硬化を行
うことでダイボンドを完了する。ダイボンド後、金線又
は銅線からなるワイヤー４を用い、ポールボンティング
法等で半導体メモリチップ３の表面上に形成されている
ポンディングパッド６とインナーリード２の間を電気的
に接続する。なお、実施例では、インナーリードのそれ
ぞれに突起θが設けである。次いで、第２図で示すよう
に半導体メモリテップ３の表面上にゲル状の透明し゛ジ
ン７として、例えば、シリコンレジンを塗布し、一定時
間放置して半導体メモリチップ３の表面全域に均等に拡
がった状態を得る。なお、塗布する透明レジン７の量は
、半導体メモリデフ１３面積に依存して変化するため限
定出来ないが、最も厚いところでも５００μｍ以下とな
るようにする。1 to 4 show process diagrams for realizing a windowed DIP structure. First, as shown in FIG. 1, an iron-nickel (42ωt%) alloy plate or a copper-tin alloy plate is processed and placed on the board support part 1 of the lead frame on which the board support part 1 and the inner leads 2 are formed. The semiconductor memory chip 3 is die-bonded. The die bonding method may be either the gold-silicon eutectic method or the silver paste method, and in the case of the former, 400 to 4
Die bonding is performed in a reducing atmosphere at about 80'C. In the latter case, it can be bonded at room temperature and then heated at 160 to 300°C.
Die bonding is completed by curing the paste in air or a nitrogen atmosphere in the range of . After die bonding, the bonding pads 6 formed on the surface of the semiconductor memory chip 3 and the inner leads 2 are electrically connected using a wire 4 made of a gold wire or a copper wire by a pole bonding method or the like. In the embodiment, each inner lead is provided with a protrusion θ. Next, as shown in FIG. 2, silicone resin, for example, is applied as a gel-like transparent resin 7 on the surface of the semiconductor memory chip 3 and left for a certain period of time to spread evenly over the entire surface of the semiconductor memory chip 3. obtain a state. The amount of the transparent resin 7 to be coated cannot be limited because it changes depending on the area of the semiconductor memory differential 13, but it should be 500 μm or less even at its thickest point.
以上の過程を経てパッケージング前の組立構体が形成さ
れる。Through the above process, an assembled structure before packaging is formed.
こののち、第３図で示すように、インナーリード２に設
けた突起６を位置合わせ用のガイドとして透光用窓板８
を載置する。この時、透光用窓板８の底面にも透明レジ
ン７が拡がって付着する。また、透光用窓板８はシリカ
からなるフィラーの含有量を少なくするとともに、遮光
剤であるカーボンブラックを除いたエポキシ樹脂で成形
したものを用いる。フィラーの含有量は、紫外線で半導
体メモリチップ３の情報消去が可能な透過率を確保する
ために、６０％以下とすることがのぞましい。After this, as shown in FIG. 3, the projection 6 provided on the inner lead 2 is used as a guide for positioning and
Place. At this time, the transparent resin 7 also spreads and adheres to the bottom surface of the light-transmitting window plate 8. In addition, the light-transmitting window plate 8 has a reduced content of filler made of silica, and is molded from epoxy resin excluding carbon black, which is a light shielding agent. The content of the filler is preferably 60% or less in order to ensure a transmittance that allows information erasure of the semiconductor memory chip 3 with ultraviolet rays.
このようにして透光用窓板８をとりつけたのち、これを
１５０〜２００’Ｃのドライエヤーまたはドライ窒素雰
囲気中に配置して透明レジン７を硬化させる。After the light-transmitting window plate 8 is attached in this manner, it is placed in a dry air or dry nitrogen atmosphere at 150 to 200'C to harden the transparent resin 7.
最後に、第４図で示すように、通常のモールド樹脂９で
成形する。なお、モールド樹脂としては、例えば、エポ
キシ樹脂を用いればよく、成形時の熱処理温度は、１７
０°Ｃ〜１９０”Ｃ程度である。Finally, as shown in FIG. 4, it is molded using a normal molding resin 9. Note that as the mold resin, for example, epoxy resin may be used, and the heat treatment temperature during molding is 17
The temperature is about 0°C to 190”C.
以上の工程を経て、窓つきＤＩＰ構造とされた本発明の
光消去型半導体メモリ装置が完成する。Through the above steps, the photo-erasable semiconductor memory device of the present invention having a windowed DIP structure is completed.
なお、以上の説明では、ＤＩＰ構造を例示したがパッケ
ージ構造はこれに限られるものではない。In addition, although the DIP structure was illustrated in the above description, the package structure is not limited to this.
発明の効果
本発明の光消去型半導体メモリ装置は、通常のモールド
樹脂とゲル状透明樹脂を用いて製作可能であり、パンケ
ージングのための最高処理温度が２００’Ｃ以下の低温
となるため、熱による特性変動の受は易い微細パターン
の光消去型半導体メモリ装置にこの構造を採用しても、
特性変動をもたらすおそれはない。さらに、高価な構成
部材が不要となるため、製品価格の高騰を抑えることも
できる。Effects of the Invention The photo-erasable semiconductor memory device of the present invention can be manufactured using ordinary mold resin and gel-like transparent resin, and the maximum processing temperature for pancaging is as low as 200'C or less. Even if this structure is adopted for a light-erasable semiconductor memory device with a fine pattern that is susceptible to characteristic fluctuations due to heat,
There is no risk of changing characteristics. Furthermore, since expensive structural members are not required, it is possible to suppress a rise in product prices.
第１図〜第４図は本発明の光消去型半導体メモリ装置の
製造過程の一例を示す工程図である。
１・・・・・・基板支持部、２・・・・・・インナーリ
ード、３・・・・・・半導体メモリチップ、４・−・ワ
イヤー、５・−・・・ポンディングパツド、６・・・・
・突起、７・・・・・・透明レジン、８・・・・・透光
用窓板、９・・・・・モールド樹脂。1 to 4 are process diagrams showing an example of the manufacturing process of the photo-erasable semiconductor memory device of the present invention. DESCRIPTION OF SYMBOLS 1... Board support part, 2... Inner lead, 3... Semiconductor memory chip, 4... Wire, 5... Bonding pad, 6・・・・・・
-Protrusion, 7...Transparent resin, 8...Translucent window plate, 9...Mold resin.
Claims (3)
モリチップが固着され、同光消去型半導体メモリチップ
上の電極とインナリード間が金属細線で接続されてなる
組立構体を樹脂で封止するとともに、前記光消去型半導
体メモリチップ上の樹脂部分が透明もしくは半透明の樹
脂体の埋め込みで構成されて透光窓を形成していること
を特徴とする光消去型半導体メモリ装置。(1) A photo-erasable semiconductor memory chip is fixed to the substrate support portion of a lead frame, and the electrodes on the photo-erasable semiconductor memory chip and the inner leads are connected by thin metal wires, and the assembled structure is sealed with resin. Further, a photo-erasable semiconductor memory device characterized in that the resin portion on the photo-erasable semiconductor memory chip is formed by embedding a transparent or semi-transparent resin body to form a light-transmitting window.
特徴とする特許請求の範囲第１項に記載の光消去型半導
体メモリ装置。(2) The photo-erasable semiconductor memory device according to claim 1, wherein a protrusion is formed on the inner lead.
状の透明樹脂が介在していることを特徴とする特許請求
の範囲第１項に記載の光消去型半導体メモリ装置。(3) The photo-erasable semiconductor memory device according to claim 1, wherein a gel-like transparent resin is interposed between the resin body and the photo-erasable semiconductor memory chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28242786A JPS63133653A (en) | 1986-11-26 | 1986-11-26 | Optically erasable semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28242786A JPS63133653A (en) | 1986-11-26 | 1986-11-26 | Optically erasable semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63133653A true JPS63133653A (en) | 1988-06-06 |
Family
ID=17652267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28242786A Pending JPS63133653A (en) | 1986-11-26 | 1986-11-26 | Optically erasable semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63133653A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5353899A (en) * | 1991-07-04 | 1994-10-11 | Sugatsune Industrial Co., Ltd. | Damper mechanism |
| WO1996012303A1 (en) * | 1994-10-14 | 1996-04-25 | National Semiconductor Corporation | Integrated circuit package assembly including a window and methods of manufacturing |
| CN1035280C (en) * | 1991-07-04 | 1997-06-25 | 司卡雷工业株式会社 | Buffer |
-
1986
- 1986-11-26 JP JP28242786A patent/JPS63133653A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5353899A (en) * | 1991-07-04 | 1994-10-11 | Sugatsune Industrial Co., Ltd. | Damper mechanism |
| CN1035280C (en) * | 1991-07-04 | 1997-06-25 | 司卡雷工业株式会社 | Buffer |
| WO1996012303A1 (en) * | 1994-10-14 | 1996-04-25 | National Semiconductor Corporation | Integrated circuit package assembly including a window and methods of manufacturing |
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