JPS63133654A - Optically erasable semiconductor storage device - Google Patents
Optically erasable semiconductor storage deviceInfo
- Publication number
- JPS63133654A JPS63133654A JP28242886A JP28242886A JPS63133654A JP S63133654 A JPS63133654 A JP S63133654A JP 28242886 A JP28242886 A JP 28242886A JP 28242886 A JP28242886 A JP 28242886A JP S63133654 A JPS63133654 A JP S63133654A
- Authority
- JP
- Japan
- Prior art keywords
- light
- semiconductor memory
- window plate
- transmitting window
- memory chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 20
- 239000011521 glass Substances 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000010453 quartz Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 239000003822 epoxy resin Substances 0.000 abstract description 6
- 229920000647 polyepoxide Polymers 0.000 abstract description 6
- 238000000465 moulding Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract description 2
- 239000004035 construction material Substances 0.000 abstract 1
- 239000002210 silicon-based material Substances 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 235000009168 Coleus dazo Nutrition 0.000 description 2
- 244000016741 Coleus dazo Species 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000006082 mold release agent Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、情報消去が光でなされる光消去型半導体メモ
リ装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a photo-erasable semiconductor memory device in which information is erased using light.
従来の技術
従来の光消去型半導体メモリ装置のパッケージは、主と
してセラミックパッケージとされている。2. Description of the Related Art Conventional packages for photo-erasable semiconductor memory devices are mainly ceramic packages.
このセラミックパッケージは、セラミック製のベースと
キャップ、リードフレーム、透光窓形成用の石英ガラス
、およびベースとキャップ、石英ガラスとキャップを接
着するだめの鉛低融点ガラスなどの構成用部材からなっ
ている。This ceramic package consists of structural members such as a ceramic base and cap, a lead frame, quartz glass for forming a transparent window, and lead low-melting glass for bonding the base, cap, quartz glass, and cap. There is.
このセラミックパッケージに半導体メモリチップを搭載
して光消去型半導体メモリ装置を表作する場合、400
〜600 ’Cの温度に保たれたベース上に金又は銀の
粉末を主体とするペーストを塗布し、このペースト面上
に半導体メモリチップ(シリコン製)を載せ、さらに、
数回こすりつけてベースに固着するときの熱処理、ベー
スの上にキャップを載せ、さらに、キャップとベースの
合わせずれを防ぐとともに、適当な加圧力を与えるため
に、スプリングクリップで固定したのち、400〜s
o o ’cのオーブン中に通し、キャソプとベースの
シール部に配設した低融点ガラスの溶融により、半導体
メモリチップを封じ込めるときの熱処理が不可欠である
。また、この熱処理に要する時間は数十分にも及んでい
る。When a semiconductor memory chip is mounted in this ceramic package to produce a photo-erasable semiconductor memory device, it costs 400 yen.
A paste mainly composed of gold or silver powder is applied onto a base maintained at a temperature of ~600'C, a semiconductor memory chip (made of silicon) is placed on the paste surface, and further,
After rubbing several times and heat treatment to make it stick to the base, place the cap on the base, and fix it with a spring clip to prevent the cap and base from misaligning and to apply appropriate pressure. s
Heat treatment is essential when enclosing the semiconductor memory chip by passing it through an o'c oven and melting the low melting point glass disposed at the sealing portion of the cassop and base. Moreover, the time required for this heat treatment extends to several tens of minutes.
発明が解決しようとする問題点
半導体メモリチップでも他の半導体集積回路チップと同
様にパターンの微細化が急速に進んでおり、これに伴っ
て、半導体メモリチップの二次元的な寸法のみならず、
三次元的な寸法の縮小化が進み半導体メモリ素子の特性
は従来以上に熱的な影響あるいは熱応力にもとづく機械
応力的な影響を受けやすくなっている。Problems to be Solved by the Invention Similar to other semiconductor integrated circuit chips, the pattern size of semiconductor memory chips is rapidly becoming finer.
As three-dimensional dimensions continue to shrink, the characteristics of semiconductor memory devices are becoming more susceptible to thermal influences or mechanical stress based on thermal stress than ever before.
したがって、微細パターンを有する光消去型半導体メモ
リチップを400〜600’Cの熱処理を数十分間にわ
たり施すことが必要なセラミックパッケージに搭載した
場合、特性に重大な影響が及ぼされてしまう。Therefore, when a photo-erasable semiconductor memory chip having a fine pattern is mounted in a ceramic package that requires heat treatment at 400 to 600'C for several tens of minutes, the characteristics will be seriously affected.
さらにセラミックパッケージの構成部材はそのいずれも
が高価な材料であり、半導体チップを搭載するパッケー
ジが高価となシ、製品価格の引き下げの障害となる問題
も存在した。Furthermore, the constituent members of the ceramic package are all made of expensive materials, and the package on which the semiconductor chip is mounted is expensive, which poses a problem that becomes an obstacle to lowering the product price.
問題点を解決するだめの手段
本発明は、上記の問題を解決するために、セラミック材
料1召英ガラスあるいは低融点ガラスなどの高価な部材
の使用を避け、低温度の熱処理でパッケージングが可能
なプラスチックパッケージに光消去型半導体メモリチッ
プを搭載した構造を実現するものである。Means to Solve the Problems In order to solve the above problems, the present invention uses a ceramic material (1) that avoids the use of expensive components such as glass or low-melting glass, and can be packaged by heat treatment at low temperatures. This realizes a structure in which a photo-erasable semiconductor memory chip is mounted in a plastic package.
すなわち1本発明の光消去型半導体メモリ装置の特徴は
、リードフレームの基板支持部に光消去型半導体メモリ
チップが固着され、同党消去型半導体メモリチップ上の
電極とインナーリード間が金属細線で接続されてなる組
立構体の前記光消去型半導体メモリチップの直上に1石
英もしくは硬質ガラスからなる透光用窓板が配設され1
さらに、これらが前記透光用窓板を露出させて樹脂で封
止されている構造にある。In other words, the feature of the photo-erasable semiconductor memory device of the present invention is that the photo-erasable semiconductor memory chip is fixed to the substrate supporting portion of the lead frame, and a thin metal wire is used between the electrodes on the same erasable semiconductor memory chip and the inner leads. A light-transmitting window plate made of quartz or hard glass is disposed directly above the optically erasable semiconductor memory chip of the connected assembled structure;
Furthermore, these have a structure in which the transparent window plate is exposed and sealed with resin.
作用
本発明の光消去型半導体メモリ装置は、樹脂封止構造で
あるため、これの製作過程で必要とされる熱処理温度を
引き下げることができる。また。Function: Since the photo-erasable semiconductor memory device of the present invention has a resin-sealed structure, the heat treatment temperature required during its manufacturing process can be lowered. Also.
高価な構成部材の使用が透光用窓板のみに限られる。The use of expensive components is limited to the light-transmitting window panel.
実施例
以下に本発明の光消去型半導体メモリ装置をプラスチッ
ク封止形デュアルインラインパッケージ(以下DIPと
記す)構造として実現する実施例を第1図〜第6図を参
照して説明する。Embodiment An embodiment in which the photo-erasable semiconductor memory device of the present invention is realized as a plastic sealed dual in-line package (hereinafter referred to as DIP) structure will be described below with reference to FIGS. 1 to 6.
第1図〜第6図は、DIP構造を実現するための工程図
を示す。1 to 6 show process diagrams for realizing the DIP structure.
先ず、第1図で示すように、基板支持部1とインナーリ
ード2を有するリードフレームの基板支持部1の上に金
−シリコン共晶法または銀ペースト法で光消去型半導体
メモリチップ(以下半導体チップと略記する)3を固着
する。金−シリコン共晶法による固着は400〜500
°Cの不活性ガス中で行なう。一方、銀ペースト法によ
る固着は。First, as shown in FIG. 1, a photo-erasable semiconductor memory chip (hereinafter referred to as semiconductor (abbreviated as chip) 3 is fixed. Fixation by gold-silicon eutectic method is 400-500
Carry out under inert gas at °C. On the other hand, fixation using the silver paste method.
半導体チップ3を基板支持部1に銀ペーストで貼り付け
た後、150〜300 ’Cの温度雰囲気中で銀ペース
トを硬化させて行なう。つぎに、金あるいは銅からなる
細いワイヤー4を用いて半導体チップ3の上に形成され
ているポンデイングパツド6をリードフレームのインナ
ーリード2の先端部に接続する。この接続に際しては例
えば熱圧着ポールボンディング法を採用する。次いで1
第2図で示すように、半導体チップ30表面上に硬化状
態で弾力性を示すシリコーン等のゲル状の透明樹脂6を
塗布し、さらに、はぼ150’Cのドライエヤー雰囲気
中で硬化する。なお、透明樹脂6の塗布厚は、ワイヤー
4の最高点と同程度となるように設定する。After the semiconductor chip 3 is attached to the substrate supporting part 1 with silver paste, the silver paste is cured in an atmosphere at a temperature of 150 to 300'C. Next, the bonding pad 6 formed on the semiconductor chip 3 is connected to the tip of the inner lead 2 of the lead frame using a thin wire 4 made of gold or copper. For this connection, for example, a thermocompression pole bonding method is employed. then 1
As shown in FIG. 2, a gel-like transparent resin 6 such as silicone which exhibits elasticity in a cured state is applied onto the surface of the semiconductor chip 30, and is further cured in a dry air atmosphere at 150'C. The coating thickness of the transparent resin 6 is set to be approximately the same as the highest point of the wire 4.
こののち、第3図で示すように石英または硬質ガラスか
らなる適当な厚みの透光用窓板7を用意し、この片側の
面にも半導体チップ3の上面に塗布したものと同じ透明
樹脂8を薄く塗布し、さらに、透光用窓板7の上に、塗
布した透明樹脂8とリードフレーム上に固着した半導体
チップ3を覆う透明樹脂6とを対向させ、次いで両者を
当接させるとともに、再度160′C〜200°Cのド
ライエヤー雰囲気中で硬化させる。この処理で双方の透
明樹脂が一体化した透明樹脂層9を介して半導体チップ
3と透光用窓板7とが向い合った一体構成物が形成され
る(第4図)。Thereafter, as shown in FIG. 3, a light-transmitting window plate 7 made of quartz or hard glass with an appropriate thickness is prepared, and one side of the plate 7 is coated with the same transparent resin 8 as that applied to the top surface of the semiconductor chip 3. Further, on the transparent window plate 7, the coated transparent resin 8 and the transparent resin 6 covering the semiconductor chip 3 fixed on the lead frame are made to face each other, and then the two are brought into contact with each other. It is cured again in a dry air atmosphere at 160'C to 200C. Through this process, an integral structure is formed in which the semiconductor chip 3 and the light-transmitting window plate 7 face each other via the transparent resin layer 9 in which both transparent resins are integrated (FIG. 4).
以上のようにして形成された一体構成物を、プラスチッ
ク成型用金型内に配置し、遮光剤であるカーボンブラン
クのみが除かれ1通常の充填剤および他の混合物が混ぜ
られたエポキシ樹脂でDIP構造となるように対土成型
する。なお、成型時の温度は160〜180″Cとする
。第6図は、成型後の状態を示し、透光用窓板7はエポ
キシ樹脂10の中へ完全には埋め込まず1透光用窓板7
の一部のみが埋め込まれるようにしてその周囲に溝11
を設けておく。The integral structure formed as described above is placed in a plastic mold, and only the carbon blank, which is a light shielding agent, is removed. The soil is formed to form a structure. The temperature during molding is 160 to 180"C. Figure 6 shows the state after molding, and the light-transmitting window plate 7 is not completely embedded in the epoxy resin 10. Board 7
A groove 11 is formed around it so that only a part of it is embedded.
Set it up.
次いで、第6図で示すように、溝11の中に使用時には
ゲル状で硬化後は周囲のエポキシ樹脂1oと同様な性質
を有するエポキシ系の埋め込み樹脂12を流”し込み、
160〜200″Cの温度で硬化させる。Next, as shown in FIG. 6, an epoxy-based embedding resin 12 is poured into the groove 11, which is gel-like when in use and has similar properties to the surrounding epoxy resin 1o after hardening.
Cure at a temperature of 160-200"C.
なお、埋め込み樹脂12は、熱膨張率が透光用窓板7と
エポキシ樹脂10の熱膨張率の中間の値を有し1離型剤
が混合されず、しかも接着剤が多量に混合されたもので
あって、温度変化に対して透光用窓板7とエポキシ樹脂
1oとの間に位置し、熱膨張に対する緩衝効果が得られ
るようなものであることが望ましい。なお、当然のこと
ではあるが、埋め込み樹脂12としては遮光剤であるカ
ーボンブラックが混入されていないものを選ぶ。Note that the embedding resin 12 has a thermal expansion coefficient that is intermediate between those of the transparent window plate 7 and the epoxy resin 10, and no mold release agent was mixed therein, and a large amount of adhesive was mixed therein. It is desirable that it be located between the light-transmitting window plate 7 and the epoxy resin 1o to provide a buffering effect against thermal expansion against temperature changes. It goes without saying that the embedding resin 12 should be one that does not contain carbon black, which is a light shielding agent.
以上の過程を経て、DIP構造を有する本発明の光消去
型半導体メモリ装置が完成する。Through the above process, a photo-erasable semiconductor memory device of the present invention having a DIP structure is completed.
なお5以上の説明では、DIP構造を例示したがパッケ
ージ構造はこれに限られるものではない。In the explanation above, the DIP structure is exemplified, but the package structure is not limited to this.
発明の効果
本発明の光消去型半導体メモリ装置は、通常のモールド
樹脂を用いて製作可能であり1パツケージングのための
最高処理温度が200′C以下の低温となるため、熱に
よる特性変動の受は易い微細パターンの光消去型半導体
メモリ装置にこの構造を採用しても、特性変動をもたら
すおそれはない。Effects of the Invention The photo-erasable semiconductor memory device of the present invention can be manufactured using ordinary molding resin, and the maximum processing temperature for one packaging is a low temperature of 200'C or less, so there is no characteristic variation due to heat. Even if this structure is adopted for a photo-erasable semiconductor memory device with a fine pattern that is easy to accept, there is no risk of causing characteristic fluctuations.
さらに、透光用窓板を除き、高価な構成部材が不要とな
るため、製品価格の高騰を抑えることもできる。Furthermore, since no expensive structural members are required except for the light-transmitting window plate, it is possible to suppress a rise in product prices.
第1図〜第6図は1本発明の光消去型半導体メモリ装置
の製造過程の一例を示す工程図である。
1・・・・・・基板支持部、2・・・・・・インナーリ
ード、3・・・・・半導体メモリチップ、4・・・・・
・ワイヤー、6・・・・・・ポンディングパッド16.
8・・・・・・透明樹脂、7・・・・・・透光用窓板、
9・・・・・・透明樹脂層、IQ・・・・・・エポキシ
樹脂、11・・・・・・溝、12・・・・・・埋め込み
樹脂。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名渭塑
Hq製
区 区 区 区
F−I N cQ
リ塚 城 塚 脈
区 区
の Q
憾 塚1 to 6 are process diagrams showing an example of the manufacturing process of a photo-erasable semiconductor memory device of the present invention. 1... Board support part, 2... Inner lead, 3... Semiconductor memory chip, 4...
・Wire, 6...Ponding pad 16.
8...Transparent resin, 7...Translucent window plate,
9...Transparent resin layer, IQ...Epoxy resin, 11...Groove, 12...Filled resin. Name of agent: Patent attorney Toshio Nakao and one other person
Rizuka Castle Mound Q Rizuka
Claims (2)
モリチップが固着され、同光消去型半導体メモリチップ
上の電極とインナーリード間が金属細線で接続されてな
る組立構体の前記光消去型半導体メモリチップの直上に
、石英もしくは硬質ガラスからなる透光用窓板が配設さ
れ、さらに、これらが前記透光用窓板を露出させて樹脂
で封止されていることを特徴とする光消去型半導体メモ
リ装置。(1) The photo-erasable semiconductor memory chip is fixed to the substrate supporting portion of the lead frame, and the electrodes on the photo-erasable semiconductor memory chip and the inner leads are connected by thin metal wires. A light erasing device characterized in that a light-transmitting window plate made of quartz or hard glass is disposed directly above the memory chip, and further, the light-transmitting window plate is exposed and sealed with a resin. type semiconductor memory device.
にゲル状の透明樹脂が介在していることを特徴とする特
許請求の範囲第1項に記載の光消去型半導体メモリ装置
。(2) A photo-erasable semiconductor memory device according to claim 1, characterized in that a gel-like transparent resin is interposed between the photo-erasable semiconductor memory chip and the light-transmitting window plate. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28242886A JPS63133654A (en) | 1986-11-26 | 1986-11-26 | Optically erasable semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28242886A JPS63133654A (en) | 1986-11-26 | 1986-11-26 | Optically erasable semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63133654A true JPS63133654A (en) | 1988-06-06 |
Family
ID=17652282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28242886A Pending JPS63133654A (en) | 1986-11-26 | 1986-11-26 | Optically erasable semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63133654A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121675A (en) * | 1997-09-22 | 2000-09-19 | Fuji Electric Co., Ltd. | Semiconductor optical sensing device package |
-
1986
- 1986-11-26 JP JP28242886A patent/JPS63133654A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121675A (en) * | 1997-09-22 | 2000-09-19 | Fuji Electric Co., Ltd. | Semiconductor optical sensing device package |
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