JPS59205744A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59205744A
JPS59205744A JP58080312A JP8031283A JPS59205744A JP S59205744 A JPS59205744 A JP S59205744A JP 58080312 A JP58080312 A JP 58080312A JP 8031283 A JP8031283 A JP 8031283A JP S59205744 A JPS59205744 A JP S59205744A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
connection
semiconductor
external circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58080312A
Other languages
Japanese (ja)
Inventor
Isamu Kitahiro
北広 勇
Hiroshi Takahashi
弘 高橋
Kenzo Hatada
畑田 賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58080312A priority Critical patent/JPS59205744A/en
Publication of JPS59205744A publication Critical patent/JPS59205744A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67138Apparatus for wiring semiconductor or solid state device
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To facilitate the connection of the metal leads with the semiconductor element by thinning one-side ends of the leads as well as the connection with the external circuit by thickening another-side ends of the leads. CONSTITUTION:One end 25 of a metal lead 23 gilt with Sn is connected to an Au projecting electrode 22 on a semiconductor element 21 by Au-Su alloy junction and the lead 23 is stuck and fixed to the element 21 with resin 24. Furthermore, a connection terminal 27 projects from the bottom of the element 21 to contrive facility of connection with a circuit board 31. In this constitution, the semiconductor device 33 can be fitted to the board 31 easily by similar process to be applied to the general passive parts 34 such as a chip resistance and high- density mounting is attained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は高密度実装に最適の半導体装置の構造に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a structure of a semiconductor device that is optimal for high-density packaging.

従来例の構成とその問題点 近年、機器の小型化・薄型化に伴い高密度実装技術が強
く要望されるようになって来た。そのために半導体素子
の接続にもワイヤレスボンディング技術が広く使用され
るようになって来た。以下第1図にフリップチップを、
第2図にはフィルムキャリヤ(以下TABと書く)の例
を示す〇第1図において、1は半導体素子、2.2’は
半田バンプ、3は基板、4は導体、5.5’は半田バン
プが接合される領域である。第1図の例では半導体素子
上電極の上に半田で突起電極が形成されるため、基板へ
の接続及び多数個実装する際極めて高密度化が実現でき
る。
Conventional configurations and their problems In recent years, as devices have become smaller and thinner, there has been a strong demand for high-density packaging technology. For this reason, wireless bonding technology has come to be widely used for connecting semiconductor elements. The flip chip is shown in Figure 1 below.
Figure 2 shows an example of a film carrier (hereinafter referred to as TAB). In Figure 1, 1 is a semiconductor element, 2.2' is a solder bump, 3 is a substrate, 4 is a conductor, and 5.5' is solder. This is the area where the bumps are bonded. In the example shown in FIG. 1, the protruding electrodes are formed with solder on the electrodes of the semiconductor elements, so that extremely high density can be achieved when connecting to the substrate and mounting a large number of semiconductor elements.

しかしながら、上記の例では電極は一面にしかついてな
い土、フェースダウンで接合する際に位置合せが困難で
ある。
However, in the above example, the electrodes are attached only to one side, making it difficult to align them when joining face down.

また、他の従来例としてTABの断面スケッチ図を第2
図に示した。第2図において、6は半導体素子、7は半
導体素子上に形成されたAu突起電極、8はSnメッキ
Cuリード、9はポリイミドフィルム、10.10’は
外部回路と接続するための領域である。この場合、半導
体素子6上に形成されたムU電極7と(iuリード上の
Snメッキ8で合金接続されるため、その信頼性は極め
て高いとされている。さらに第2図の半導体装置を基板
に搭載した例を第3図に示した。第3図において、第2
図と同一箇所には同一番号を付した。11は基板、12
は導体配線、13は外部回路との接続部分、14は半導
体素子を接着固定している接着剤又は半田である。
In addition, as another conventional example, a cross-sectional sketch diagram of TAB is shown in the second
Shown in the figure. In FIG. 2, 6 is a semiconductor element, 7 is an Au protruding electrode formed on the semiconductor element, 8 is a Sn-plated Cu lead, 9 is a polyimide film, and 10.10' is an area for connection with an external circuit. . In this case, the reliability is said to be extremely high because the alloy connection is made between the mu-U electrode 7 formed on the semiconductor element 6 and the Sn plating 8 on the iu lead. An example of mounting on a board is shown in Figure 3. In Figure 3, the second
The same numbers are given to the same parts as in the figure. 11 is a substrate, 12
1 is a conductor wiring, 13 is a connecting portion with an external circuit, and 14 is an adhesive or solder for adhesively fixing the semiconductor element.

このようにリード8は一度成型され(フォーミングと呼
ぶ)、領域13で導体配線12に接続される。必要な場
合、半導体素子6は基板11に接着剤14を用い固定さ
れる。
In this way, the lead 8 is once formed (referred to as forming) and connected to the conductor wiring 12 in the region 13. If necessary, the semiconductor element 6 is fixed to the substrate 11 using an adhesive 14.

しかしながら上記の例では基板11に搭載するためには
り一ド8をフォーミングレなければならず、ハンドリン
グが極めて困難である。
However, in the above example, it is necessary to form the beam 8 in order to mount it on the substrate 11, which makes handling extremely difficult.

このような実状に鑑み、本発明は、金属リードの一端は
半導体素子上の電極と接続しやすい構造、他の一端は外
部回路と接続しやすい構造とし、上記従来例の問題点を
解決することができたものである。
In view of these circumstances, the present invention solves the problems of the conventional example by providing one end of the metal lead with a structure that makes it easy to connect to an electrode on a semiconductor element, and the other end with a structure that makes it easy to connect with an external circuit. This is what was created.

発明の目的 本発明は従来の問題に鑑み、高密度と実装しうる構造と
形態を有する半導体装置を提供することを目的とする。
OBJECTS OF THE INVENTION In view of the conventional problems, it is an object of the present invention to provide a semiconductor device having a structure and form that allows high-density packaging.

発明の構成 本発明は金属リードの一端は半導体素子上の突起電極と
接続容易なように薄くし、他端は外部回路と接続しやす
いよう厚くし、こうした金属リードに半導体素子を接続
することにより高密度に実装しうる半導体装置を提供す
るものである。
Structure of the Invention The present invention has one end of a metal lead made thin so that it can be easily connected to a protruding electrode on a semiconductor element, and the other end made thick so that it can be easily connected to an external circuit, and by connecting a semiconductor element to such a metal lead. The present invention provides a semiconductor device that can be mounted at high density.

実施例の説明 第4図は本発明の第1の実施例における断面構造を示し
た。第3図において、21は半導体素子、22は半導体
素子上の突起電極で通常人U又は半田、23は金属リー
ド、24は樹脂、26は金属リードの半導体素子上電極
との接合部で比較的薄い部分、26は金属リードの外部
回路接続部で厚みtl有する比較的厚い部分、27は接
続端子となる。
DESCRIPTION OF EMBODIMENTS FIG. 4 shows a cross-sectional structure in a first embodiment of the present invention. In FIG. 3, 21 is a semiconductor element, 22 is a protruding electrode on the semiconductor element, usually by soldering, 23 is a metal lead, 24 is a resin, and 26 is a joint between the metal lead and the electrode on the semiconductor element. The thin portion 26 is a relatively thick portion having a thickness tl of the external circuit connection portion of the metal lead, and the numeral 27 is a connection terminal.

本実施例ではSnメッキされた金属リード23の一端2
6が半導体素子上の電極22即ちAu突起電極にAu−
Sn合金接合されており、かつり−ド23は半導体素子
21に接着性樹脂24で接着・固定されている。
In this embodiment, one end 2 of the metal lead 23 is Sn-plated.
6 is an Au-
Sn alloy bonding is performed, and the cross-domain 23 is bonded and fixed to the semiconductor element 21 with an adhesive resin 24.

さらに、接続端子となる27は半導体素子21の底部よ
り突出した構造とすることにより、基板への接続が容易
になる。本実施例に示す構造で作られた半導体装置を基
板に搭載した例を第6図に示す。第6図において、31
は基板(セラミック又は樹脂基板)、32は基板31上
の導体配線。
Furthermore, the connecting terminals 27 are structured to protrude from the bottom of the semiconductor element 21, thereby facilitating connection to the substrate. FIG. 6 shows an example in which a semiconductor device manufactured with the structure shown in this embodiment is mounted on a substrate. In Figure 6, 31
is a substrate (ceramic or resin substrate); 32 is a conductor wiring on the substrate 31;

33は第4図に示す半導体装置、34はチップ抵抗等の
チップ部品、36は半田、である。このように本発明に
よる半導体装置33は一般の受動部品例えばチップ抵抗
、チップ部品34と同様の工程で基板31に容易に取付
けることができる。
33 is a semiconductor device shown in FIG. 4, 34 is a chip component such as a chip resistor, and 36 is solder. In this manner, the semiconductor device 33 according to the present invention can be easily attached to the substrate 31 in the same process as that for general passive components such as chip resistors and chip components 34.

第6図に本発明の第2の実施例の半導体装置を示す。第
6図において、41は半導体素子、42は半導体素子と
リードを接続する電極、43は金属リード、44は外部
回路と接続する比較的厚い接続部、46は半導体素子と
接続する比較的薄い接続部、46は保護用の樹脂である
。本構造では外部回路との接合部44が下面に突出した
形状になっており、基板との接続が容易になる。第7図
に本発明の第6図の構造により製造された半導体装置を
基板に搭載した例を示す。第7図において第5図と共通
部分には同一番号を付したが36は半導体装置下を通っ
ている導体配線である。半導体装置33はチップ部品3
4と同じ方法即ち半田35を用い同一工程で接続するこ
とができる。さらに、外部回路との金属リード43の接
続端部が半導体素子より外方へ突出しているため位置合
せが容易となる上半導体装置の下に導体配線を通すこと
ができる。
FIG. 6 shows a semiconductor device according to a second embodiment of the present invention. In FIG. 6, 41 is a semiconductor element, 42 is an electrode that connects the semiconductor element and a lead, 43 is a metal lead, 44 is a relatively thick connection part that connects to an external circuit, and 46 is a relatively thin connection that connects to the semiconductor element. 46 is a protective resin. In this structure, the joint portion 44 with the external circuit has a shape protruding from the bottom surface, which facilitates connection with the board. FIG. 7 shows an example in which a semiconductor device manufactured according to the structure of FIG. 6 of the present invention is mounted on a substrate. In FIG. 7, parts common to those in FIG. 5 are given the same numbers, and 36 is a conductor wiring running under the semiconductor device. The semiconductor device 33 is a chip component 3
The connection can be made in the same process using the same method as in No. 4, that is, using solder 35. Furthermore, since the connection ends of the metal leads 43 with external circuits protrude outward from the semiconductor element, alignment is facilitated and conductor wiring can be passed under the semiconductor device.

発明の効果 以上のように、本発明では金属リードの一端を薄くする
ことにより半導体素子との接続を容易にし、他端を厚く
することにより第4図、第6図の構造となしうるので、
第6図、第7図の如く外部回路との接続が極めて容易と
なる。さらには第4図、第6図の構造のものを適切なス
ペーサーを介して重さね合せ、その側面で相互接続する
ことにより容易に三次え構造を実現することもできる。
Effects of the Invention As described above, in the present invention, one end of the metal lead is made thinner to facilitate connection with a semiconductor element, and the other end is made thicker to achieve the structures shown in FIGS. 4 and 6.
Connection with external circuits is extremely easy as shown in FIGS. 6 and 7. Furthermore, a tertiary structure can be easily realized by stacking the structures shown in FIGS. 4 and 6 through appropriate spacers and interconnecting them on their sides.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は従来の半導体装置の断面図、第3図は
従来の半導体装置実装例の断面図、第4図は本発明の一
実施例の半導体装置の断面図、第6図は第1の実施例を
基板に搭載した状態の断面図、第6図は本発明の第2の
実施例の半導体装置の断面図、第7図は上記第2の実施
例を基板に搭載した状態の断面図である。 21.41 ・・・・・半導体素子、23.43・・・
・・・金属リード、25.45・・・・・・素子電極と
の接合部、26.44・・・・・・外部回路との接続部
、31・・・・・・基板、32・・・・・・導体配線、
33・・・・・半導体装置。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 、2□    3 第7図
1 and 2 are cross-sectional views of a conventional semiconductor device, FIG. 3 is a cross-sectional view of a conventional semiconductor device mounting example, FIG. 4 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view of a conventional semiconductor device. 6 is a sectional view of the semiconductor device of the second embodiment of the present invention, and FIG. 7 is a sectional view of the semiconductor device of the second embodiment of the present invention mounted on a substrate. It is a sectional view of the state. 21.41...Semiconductor element, 23.43...
...metal lead, 25.45...junction with element electrode, 26.44...connection with external circuit, 31...substrate, 32... ...conductor wiring,
33...Semiconductor device. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure, 2□ 3 Figure 7

Claims (1)

【特許請求の範囲】[Claims] (1)半導体素子上電極と接続する側は薄く、外部回路
と接続する側は厚くなった金属リード群に半導体素子上
電極を接続したことを特徴とする半導体装置。 (′;4 金属リードの外部回路と接続するために厚く
なった部分で囲まれた領域に半導体素子を挿入し、前記
素子の電極を金属リード群に接続したことを特徴とする
特許請求の範囲第1項記載の半導体装置。 (旬 半導体素子の少なくとも側面で金属リード群を接
着固定したことを特徴とする特許請求の範囲第2項記載
の半導体装置。 請求の範囲第2項記載の半導体装置。 (@ 金属リードの外部回路と接続するために厚くなっ
た部分とは反対側で半導体素子電極と金属リードとを接
続したことを特徴とする特許請求の範囲第1項記載の半
導体装置。
(1) A semiconductor device characterized in that the semiconductor element upper electrode is connected to a group of metal leads which are thin on the side connected to the semiconductor element upper electrode and thick on the side connected to an external circuit. (';4) A semiconductor element is inserted into the area surrounded by the thickened part of the metal lead for connection to an external circuit, and the electrode of the element is connected to the group of metal leads. The semiconductor device according to claim 1. The semiconductor device according to claim 2, characterized in that a group of metal leads is adhesively fixed to at least a side surface of the semiconductor element. The semiconductor device according to claim 2 (@ The semiconductor device according to claim 1, wherein the semiconductor element electrode and the metal lead are connected on the side opposite to the thickened portion of the metal lead for connection to an external circuit.
JP58080312A 1983-05-09 1983-05-09 Semiconductor device Pending JPS59205744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58080312A JPS59205744A (en) 1983-05-09 1983-05-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58080312A JPS59205744A (en) 1983-05-09 1983-05-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59205744A true JPS59205744A (en) 1984-11-21

Family

ID=13714743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58080312A Pending JPS59205744A (en) 1983-05-09 1983-05-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59205744A (en)

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