JPS59194462A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59194462A JPS59194462A JP6859183A JP6859183A JPS59194462A JP S59194462 A JPS59194462 A JP S59194462A JP 6859183 A JP6859183 A JP 6859183A JP 6859183 A JP6859183 A JP 6859183A JP S59194462 A JPS59194462 A JP S59194462A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- semiconductor substrate
- integrated circuit
- prevention layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 230000002265 prevention Effects 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 150000002500 ions Chemical class 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はセルフバイアスをもたない半導体集積回路が
形成される半導体装置において、半導体基板の電位を強
制的に接地電位に下げることができる半導体装置に関す
る。−
〔発明の技術的背景〕
セルフバイアスをもたない半導体集積回路においては半
導体基板を接地電位に保つことが不可欠である。従来、
半導体基板を接地するためには、半導体基板表面に形成
されるフィールド反転防止層に通ずるコンタクトホール
を形成し、このフィールド反転防止層を介して半導体基
板を接地していた。ここで、フィールド反転防止層は通
常イオン注入により形成されるが、その抵抗値はイオン
注入時の加速電圧、ドーズ量、熱処理工程により決定さ
れる。第１図にセルフバイアスをもたないＭＯ８集積回
路を例にとり、従来の問題点について記述する。第１図
（Ｎにおいて、１１は接地用のＡＡ層、１２は接地用の
コンタクトホール、１３はソース領域に通ずるコンタク
トホールである。また第１図（Ｂ）はｌ＜ ］図（Ａ）
のＡ−Ａ線に沿った断面図である。第１図（Ｂ）におい
て、２１はＰ型シリコン半導体基板、２２は、この半導
体基板２１上に、イオン注入により形成されたＰ−のフ
ィールド反転防止層、２３は計のソース領域、２４はＳ
ｉ Ｏ，膜、２５はＣＶＤ５Ｉ０２膜、２６はＢａＯ
膜である。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device in which a semiconductor integrated circuit having no self-bias is formed, in which the potential of a semiconductor substrate can be forcibly lowered to a ground potential. Regarding. - [Technical Background of the Invention] In a semiconductor integrated circuit having no self-bias, it is essential to maintain the semiconductor substrate at a ground potential. Conventionally,
In order to ground a semiconductor substrate, a contact hole communicating with a field reversal prevention layer formed on the surface of the semiconductor substrate is formed, and the semiconductor substrate is grounded through this field reversal prevention layer. Here, the field reversal prevention layer is usually formed by ion implantation, and its resistance value is determined by the acceleration voltage, dose amount, and heat treatment process during ion implantation. In FIG. 1, conventional problems will be described using an MO8 integrated circuit having no self-bias as an example. In Figure 1 (N), 11 is an AA layer for grounding, 12 is a contact hole for grounding, and 13 is a contact hole leading to the source region.
FIG. 2 is a sectional view taken along line A-A of FIG. In FIG. 1(B), 21 is a P-type silicon semiconductor substrate, 22 is a P- field reversal prevention layer formed on this semiconductor substrate 21 by ion implantation, 23 is a source region, and 24 is an S
i O, film, 25 is CVD5I02 film, 26 is BaO
It is a membrane.
しかし、従来においては、フィールド反転防止層２２の
形成はイオン注入により行なわれているが、その抵抗値
はイオン注入時の加速電圧、ドーズ量あるいは熱処理工
程で決定されるが、このフィールド反転防止層２２の抵
抗値にはばらつきがある。この抵抗値のばらつきにより
フィールド反転防止層２２のコンタクトホール１２との
接触部分の抵抗値がばらつく。このため、セルフバイア
スをもたないＭＯ８集積回路が常に良い性能を保つこと
はできなかっだ０ところで、上記フィールド反転防止層
２２を形成する場合のイオン注入時にドーズ量を多くし
てフィールド反転防止層２２を全面にわたってその抵抗
値を下げて、ＡＡ層１１と接触する部分のフィールド反
転防止層２２の抵抗を下げて半導体基板を接地電位に下
げて良い性能をもった集積回路を提供することも考えら
れるが、フィールド反転防止層２２に対するドーズ量を
多くするとソース・ドレイン間のｉ４ンチスルー電圧が
低下してしまうという欠点があった。さらに、従来のよ
うにフィールド反転防止層２２を半導体基板２ノを接地
する場合に使用している集積回路ではフィールド反転防
止層２２の抵抗値及びフィールド反転防止層２２とＡｅ
層１１との接触抵抗によシ大電流を流したときに、半導
体基板２１の電位が接地電位より上昇して、集積回路の
性能が低下するという欠点があった。However, conventionally, the field reversal prevention layer 22 is formed by ion implantation, and its resistance value is determined by the accelerating voltage, dose amount, or heat treatment process during ion implantation. There are variations in the resistance value of 22. Due to this variation in resistance value, the resistance value of the contact portion of the field inversion prevention layer 22 with the contact hole 12 varies. For this reason, MO8 integrated circuits that do not have self-bias cannot always maintain good performance. However, when forming the field inversion prevention layer 22, the dose amount is increased during ion implantation to form the field inversion prevention layer 22. It is also possible to provide an integrated circuit with good performance by lowering the resistance value of the field reversal prevention layer 22 over the entire surface and lowering the resistance of the field reversal prevention layer 22 in the portion that contacts the AA layer 11 to lower the semiconductor substrate to the ground potential. However, there is a drawback that when the dose amount to the field inversion prevention layer 22 is increased, the i4 inch-through voltage between the source and drain decreases. Furthermore, in an integrated circuit where the field inversion prevention layer 22 is conventionally used to ground the semiconductor substrate 2, the resistance value of the field inversion prevention layer 22 and the field inversion prevention layer 22 and Ae
When a large current is applied to the semiconductor substrate 21 due to the contact resistance with the layer 11, the potential of the semiconductor substrate 21 rises above the ground potential, resulting in a deterioration in the performance of the integrated circuit.
この発明は上記の点に鑑みてなされたもので、その目的
はセルフバイアスをもたない半導体集積回路が形成され
る半導体装置において、半導体基板の電位を接地電位に
保ち、性能の良い半導体装置を提供することにある。This invention has been made in view of the above points, and its purpose is to maintain the potential of the semiconductor substrate at the ground potential in a semiconductor device in which a semiconductor integrated circuit without self-bias is formed, thereby providing a semiconductor device with good performance. It is about providing.
セルフバイアスをもたない半導体集積回路が形成される
半導体装置において、半導体基板を接地するために設け
られたコンタクトホール部下のフィールド反転防止層及
び半導体基板領域に半導体基板と同導電型不純物をイオ
ン注入することによシ上記フィールド反転防止層の不純
物濃度よりさらに濃く形成して、半導体基板の電位を強
制的に接地電位に下げるようにしている０
〔発明の実施例〕
以下、図面を参照してこの発明の一実施例について説明
する。第２図において、第１図と同一名称には同一番号
を付する。第２図において、２２はコンタクトボール１
２下のフィールド反転防止層２２及び半導体基板２１領
域にイオン注入によシ形成されたＰ−一層である。°こ
のＰ−一層２７の不純物濃度は上記フィールド反転防止
層２２よシさらに濃度が濃くなるように、イオン注入時
にそのドーズ量が決定される。ここで、第３図にイオン
注入における不純物ドーズ量とフィールド反転防止層２
２の抵抗値の関係を示しておく。従って、半導体基板２
１の接地は、半導体基板２ノからｒ一層２７を介してＡ
！層１１を通して行なわれる。Ｐ−一層２７は上記した
ようにドーズ量が多いため、その抵抗値が小′ さい。In a semiconductor device in which a semiconductor integrated circuit without self-bias is formed, impurities of the same conductivity type as the semiconductor substrate are ion-implanted into the field reversal prevention layer and the semiconductor substrate region under the contact hole provided for grounding the semiconductor substrate. By doing so, the impurity concentration is formed to be higher than that of the field inversion prevention layer, so that the potential of the semiconductor substrate is forcibly lowered to the ground potential. An embodiment of this invention will be described. In FIG. 2, the same names as in FIG. 1 are given the same numbers. In FIG. 2, 22 is the contact ball 1
This is a P- layer formed by ion implantation in the field inversion prevention layer 22 and the semiconductor substrate 21 region below the field inversion prevention layer 22 and the semiconductor substrate 21 region. The dose of the P- layer 27 is determined at the time of ion implantation so that the impurity concentration is higher than that of the field inversion prevention layer 22. Here, FIG. 3 shows the impurity dose in ion implantation and the field inversion prevention layer 2.
The relationship between the two resistance values will be shown below. Therefore, the semiconductor substrate 2
1 is connected to A from the semiconductor substrate 2 through the r layer 27.
! This is done through layer 11. Since the P-layer 27 has a large dose as described above, its resistance value is small.
従って、集積回路に大電流を流した場合でも半導体基板
２１を接地電位に保つことができる。甘だ、半導体基板
２１の接地は抵抗値が高く、その抵抗値にばらつきがあ
るフィールド反転防止−２２を介して行なわれないため
、安定した性能のよい集積回路を提供することができる
。Therefore, even when a large current is passed through the integrated circuit, the semiconductor substrate 21 can be maintained at the ground potential. The semiconductor substrate 21 is not grounded through the field reversal prevention circuit 22, which has a high resistance value and varies in resistance value, so that an integrated circuit with stable and good performance can be provided.
以上詳述したようにこの発明によれば、セルフバイアス
をもたない半導体集積回路が形成される半導体装置にお
いて、半導体基板をフィールド反転防止層よりさらに濃
度の高い領域を介して接地用のＡ１層に接続して行なう
ようにしたので、半導体基板の電位をフィールド反転防
止層の抵抗値に無関係に接地電位に保つことができたの
で、半導体集積回路の性能を安定させることができる。As detailed above, according to the present invention, in a semiconductor device in which a semiconductor integrated circuit having no self-bias is formed, a semiconductor substrate is connected to a grounding A1 layer through a region having a higher concentration than a field inversion prevention layer. Since the potential of the semiconductor substrate can be maintained at the ground potential regardless of the resistance value of the field inversion prevention layer, the performance of the semiconductor integrated circuit can be stabilized.
【図面の簡単な説明】
第１図（Ａ）は従来の半導体装置に設けられた配線パタ
ーンを示す平面図、第１図（Ｂ）は第１図（Ｎに示した
半導体装置のＡ−Ａ線に″沿った断面図、第２図はこの
発明の一実施例に係る半導体装置の断面図、第３図はド
ーズ量と抵抗値との関係を示す図である。
２ノ・・・半導体基板、２２・・・フィールド反転防止
層、２４・・・ＳｉＱ、膜、２７・・・Ｐ−一層○出願
人代理人 弁理士 鈴 江 武 彦第１図[Brief Description of the Drawings] Fig. 1(A) is a plan view showing a wiring pattern provided in a conventional semiconductor device, and Fig. 1(B) is a plan view of the semiconductor device shown in Fig. 1(N). 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a diagram showing the relationship between dose amount and resistance value. 2. Semiconductor Substrate, 22...Field reversal prevention layer, 24...SiQ, film, 27...P-layer ○Applicant's representative Patent attorney Takehiko Suzue Figure 1
Claims (1)
半導体装置において、半導体基板を接地するために設け
られたコンタクトホール部下のフィールド反転防止層及
び半導体基板領域に半導体基板と同導電型不純物をイオ
ン注入することにより上記フィールド反転防止層の不純
物濃度よシさらに高く形成したことを特徴とする半導体
装置。In a semiconductor device in which a semiconductor integrated circuit without self-bias is formed, impurities of the same conductivity type as the semiconductor substrate are ion-implanted into the field reversal prevention layer and the semiconductor substrate region under the contact hole provided for grounding the semiconductor substrate. A semiconductor device characterized in that the impurity concentration is higher than that of the field inversion prevention layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6859183A JPS59194462A (en) | 1983-04-19 | 1983-04-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6859183A JPS59194462A (en) | 1983-04-19 | 1983-04-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59194462A true JPS59194462A (en) | 1984-11-05 |
Family
ID=13378184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6859183A Pending JPS59194462A (en) | 1983-04-19 | 1983-04-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59194462A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004282022A (en) * | 2003-03-12 | 2004-10-07 | Hynix Semiconductor Inc | Well structure of high voltage device |
-
1983
- 1983-04-19 JP JP6859183A patent/JPS59194462A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004282022A (en) * | 2003-03-12 | 2004-10-07 | Hynix Semiconductor Inc | Well structure of high voltage device |
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