JPS58159377A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58159377A JPS58159377A JP4318282A JP4318282A JPS58159377A JP S58159377 A JPS58159377 A JP S58159377A JP 4318282 A JP4318282 A JP 4318282A JP 4318282 A JP4318282 A JP 4318282A JP S58159377 A JPS58159377 A JP S58159377A
- Authority
- JP
- Japan
- Prior art keywords
- implanted
- oxide film
- ions
- semiconductor substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims description 22
- 238000007254 oxidation reaction Methods 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract 3
- -1 boron ion Chemical class 0.000 abstract 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 238000009826 distribution Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000037303 wrinkles Effects 0.000 description 2
- 244000241257 Cucumis melo Species 0.000 description 1
- 235000015510 Cucumis melo subsp melo Nutrition 0.000 description 1
- 240000002834 Paulownia tomentosa Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- FJJCIZWZNKZHII-UHFFFAOYSA-N [4,6-bis(cyanoamino)-1,3,5-triazin-2-yl]cyanamide Chemical compound N#CNC1=NC(NC#N)=NC(NC#N)=N1 FJJCIZWZNKZHII-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 210000001072 colon Anatomy 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007127 saponification reaction Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係ゎ夛、特に耐酸化
膜による選択酸化法を用いえ半導体装置の製造方法に関
する・
〔発明の技術的背景とその問題点〕
近時、半導体装置の製造工程において１耐酸化Ｗ１を用
いた選択酸化法が使用されている働ζσ・方法では、ま
ず第１図（ａ） Ｋ示す如くシリコン基板１の一生面に
熱酸化法によ）酸化膜２を形成する・次いで、＃Ｅ１ａ
Ａ（ｂ）に示す如く酸化膜２ｔ、 Ｋ ＩＩ化シリコン
膜１を形成し、この窒化シリコンａ３の必！！部分を７
オトレジスト４でマスクし、マスクされていない部分を
、例えばＣＦ４のプラズマエツチングで除去する・次す
で、第１図（＠）Ｋ示す如く酸化膜２を介してシリコン
基＆Ｊ内へＩロンのイオン注入を行すい％ｄＨフイオン
注入注入層形成する・その＠ｓ ７ ＃ ）レノスト４
を除去し、縞１図（葡に示す如く選択酸化を行ないフィ
ールド酸化膜−を形成する・これ以降は、周知の技術に
よりｆ−）電極および配線層等を形成することによって
、ＭＯＳ ）ランジスタが作成される・
しかしながら、この種の方法にあって拡次のような問題
があった。すなわち、ＭＯＳ ）ランゾスタの製造に適
用した場合、第２図に示す如くチャンネル幅が狭くなる
に従いしきい値電圧が増大する御所ｎ狭チャネル効果が
生じると云う欠点がある・さらに、シリコン基板中にイ
オン注入し一＃：、コロンが素子形成領域にしみ出し、
第３図に示す如き不純物分布となり、前記狭チャネル効
果が強調される・狭チャネル効果によるしきい値電圧の
チャネル幅依存性は、素子の微細化と共に増大し素子の
特性に悪影醤を与える・このように、しきい値電圧のチ
ャネル幅依存性が重要な問題となってい友。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device using a selective oxidation method using an oxidation-resistant film. Background and Problems] Recently, in the selective oxidation method using 1 oxidation resistant W1 in the manufacturing process of semiconductor devices, first, as shown in FIG. Form an oxide film 2 (by thermal oxidation method) on the whole surface・Next, #E1a
As shown in A(b), an oxide film 2t and a KII silicon film 1 are formed, and this silicon nitride film a3 is removed. ! part 7
Mask with photoresist 4, and remove the unmasked portion by plasma etching of CF4, for example.Next, as shown in FIG. It is easy to implant %dH ion implantation to form an implantation layer.
After that, selective oxidation is performed to form a field oxide film as shown in Figure 1 (Fig. However, there are problems with this type of method, such as expansion. In other words, when applied to the manufacture of MOS (MOS) Lanzostars, there is a drawback that a narrow channel effect occurs in which the threshold voltage increases as the channel width becomes narrower, as shown in Figure 2. After ion implantation, colon seeps into the element formation area,
The impurity distribution becomes as shown in Fig. 3, and the narrow channel effect is emphasized. - The dependence of the threshold voltage on the channel width due to the narrow channel effect increases with the miniaturization of the device and has a negative impact on the characteristics of the device.・Thus, the dependence of threshold voltage on channel width has become an important issue.
本発明の目的は、し龜い値電圧のチャネル幅依存性を防
止することができ、素子特性および信頼性の向上をはか
）得る半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent channel width dependence of threshold voltage and improve device characteristics and reliability.
本発明の骨子は、半導体基板と同導電屋を作るイオンが
素子領域へしみ出すのを防止するために、基板と逆導電
蓋を作る不純物のイオン注入を行ない第４図に示す如く
素子領域中央部よりも卓子領域周辺部において不純物濃
度が低くなるような不純物分布を得ることにある・すな
わち本発明は、耐酸化性被膜をマスクとして用い半導体
基板上に選択的に熱酸化層を形成する１桐を含む半導体
装置の製造方法において、上記半導体基板上に耐酸化性
被膜を選択的ｙｃ影形成九のち、上記半導体基板および
耐鹸化性被膜上の全面にイオン注入制御層を堆積し、次
いで上記イオン注入制御層を介して前記半導体基板と同
導電皺を作る第１の不純物を上記半導体基板にイオン注
入し、次いで前記イオン注入制御層を除去し、次いで前
記半導体基板と逆導電１１會作る第２の不純物を前記第
１の不純物より少ない注入量で上記半導体基板にイオン
注入し、しかるのち前記半導体基板の前記耐酸化性被膜
で覆われていない部分に熱酸化層を形成するようにし丸
方法である。 ・
〔発明の効果〕
本発明によれば、半導体基板と逆導電蓋を作る不純物の
イオン注入にょ）前記第４図に示す如き不純物濃度を得
ることができ、これにょ）第５図に示す如く狭チャネル
効果が従来よシも抑えられ九半導体装置を得ることがで
きる・このため、信頼性の向上をはかｐ得て、また集積
度の向上に寄与し得る等の効果を奏する・〔発明の実施
例〕
第６図（ａ）〜（ｇ）は本発明の一実施例に係わるＭＯ
ｓトランジスタ製造工Ｓを示す断面図である。ｔず〜第
６ａＡ（ａ）に示す如＜ｐｍシリコン基板（半導体基板
）１上に熱酸化法にょ夛厚さ３００（Ｈの酸化膜１２を
形成する０次いで、第６図ら）に示す如く酸化膜１２の
上に厚さ４０００ （Ｘ）の窒化シリコンＩＩ（耐酸化
性被膜）１ｓｔ形成し、さらに同図（ｂ） Ｋ示す如く
窒化シリコン膜１１の巻装部分をフォトレゾスト１４で
マスクシ、マスクサレない部分をＣＦ４のプラズマエッ
チンクで除去する。次いで、フォトレジスト１４を除去
したのち、第６図（ｄ）に示す如く試料上の全面ＫＣＶ
Ｄ法Ｋｊ ｆｉ ５０００ （Ｘ 〕０１ｍｌ化膜イオ
ン注入制御層）１５を形感する・このとき亀前ｓ＋ｌｌ
化シリコン膜ＩＪの存在に起因する断差により、酸化膜
１６ＪＩＣもこの段差に応じ九段差が形成される。そし
て、酸化膜１５の窒化シリコン膜１３の端＠１６におけ
る膜厚が他の部分より４ｈ＊くなる。The gist of the present invention is to implant impurity ions that form a conductive lid opposite to the substrate in order to prevent ions that form a conductive layer from the semiconductor substrate from seeping into the element area, as shown in FIG. The purpose of the present invention is to obtain an impurity distribution in which the impurity concentration is lower in the peripheral area of the table area than in the peripheral area of the table area.In other words, the present invention is to form a thermal oxidation layer selectively on a semiconductor substrate using an oxidation-resistant film as a mask. In the method of manufacturing a semiconductor device including paulownia, after selectively forming an oxidation-resistant film on the semiconductor substrate, an ion implantation control layer is deposited on the entire surface of the semiconductor substrate and the saponification-resistant film, and then the above-mentioned A first impurity that forms the same conductive wrinkles as the semiconductor substrate is ion-implanted into the semiconductor substrate through an ion-implantation control layer, and then the ion-implantation control layer is removed, and then a first impurity that forms conductive wrinkles opposite to the semiconductor substrate is formed. 2 impurities are ion-implanted into the semiconductor substrate at a smaller dose than the first impurity, and then a thermal oxidation layer is formed in a portion of the semiconductor substrate not covered with the oxidation-resistant film. It is.・ [Effects of the Invention] According to the present invention, it is possible to obtain the impurity concentration as shown in FIG. It is possible to obtain a semiconductor device in which the narrow channel effect is suppressed compared to the conventional one. Therefore, it is possible to obtain effects such as improving reliability and contributing to an improvement in the degree of integration. Embodiment] FIGS. 6(a) to 6(g) show an MO according to an embodiment of the present invention.
FIG. As shown in Fig. 6A(a), a thermal oxidation method is applied to a <pm silicon substrate (semiconductor substrate) 1 to form an oxide film 12 of 300 mm (H) as shown in Fig. 6. A first silicon nitride II (oxidation-resistant film) with a thickness of 4000 mm (X) is formed on the film 12, and as shown in FIG. The portion is removed using a CF4 plasma etch. Next, after removing the photoresist 14, the entire surface of the sample is covered with KCV as shown in FIG. 6(d).
D method Kj fi 5000 (X 〕01ml film ion implantation control layer) 15. At this time, Kamemae s+ll
Due to the difference caused by the presence of the silicon oxide film IJ, nine steps are formed in the oxide film 16JIC in accordance with this step. The film thickness of the oxide film 15 at the end @16 of the silicon nitride film 13 is 4h* greater than that at other parts.
次に％前記酸化膜１５を通して加速電圧２５０〔ｋｖ〕
、ドーズ量ｌＸｌ０ （ｆｆｉ ）で、フィールド
イオン注入を行なう・注入イオンには一ロン（第１の不
純物）を使用した・ζζで１前記窒化シリコン膜ＩＪで
覆われている部分にはイオン注入されず、を九前記酸化
属１８０ｍ厚の違いから窒化シリ；ン膜１１０端部では
その注入イオン量は極めて少ないものとな為・このため
、第６ＷＪ（・）に示す如（ｚ ｔａｘンイオン注入層
１１は窒化シリコン膜１３およびその端部近傍を除いた
部分に選択的に形成される。Next, an acceleration voltage of 250 [kv] is applied through the oxide film 15.
, Field ion implantation is performed at a dose of lXl0 (ffi) - Iron (first impurity) is used for the implanted ions Due to the difference in the thickness of the silicon oxide layer 180 m, the amount of ions implanted at the end of the silicon nitride film 110 is extremely small. 11 is selectively formed on the silicon nitride film 13 and its portions other than the vicinity of its ends.
次に１前記酸化膜１５をＮＨ４Ｆ等によシエ、チング除
去したのち、加速電圧６Ｇ（ｋＶ）、ドーズ量Ｉ Ｘ
１０”（国−２〕で砒素（第２の不純物）をイオン注入
し第６図（ｆ）に示す如く砒素イオン注入層１Ｍを形成
する。このとき砒素イオン注入は前記がロンイオン注入
の注入量よや少ないので、砒素イオン注入による反転防
止層は繭記輩化シリ；ン膜１１の端部近傍のみに形成さ
れることＫなる・すなわち、シリコン基板１１上の不純
物濃度が前記第４図に示す如き状態にな為。Next, after removing the oxide film 15 by oxidation using NH4F or the like, the acceleration voltage is 6G (kV) and the dose is IX.
Arsenic (second impurity) is ion-implanted at 10" (Country-2) to form an arsenic ion-implanted layer 1M as shown in FIG. Since the amount of impurity is relatively small, the inversion prevention layer by arsenic ion implantation is formed only near the end of the silicon film 11. In other words, the impurity concentration on the silicon substrate 11 is as shown in FIG. The situation is as shown.
次に、熱酸化法を用いて第６図−）に示す如くフィール
ド酸化膜１９を形成する・その後、窒化シリコン１ｓ１
３を除去したのち１周知の技術を用いてｆ−）電極およ
び配線層等を形成することによってＭＯＢ ）ランジス
タが作製されることになる・かくして形成されたＭＯＢ
）ランゾスタは、前記第４図に示す不純物分布を有す
ることから、狭チャネル効果を抑える仁とかで亀、なお
、本発明は上述した実施例に＠定されるものではなく、
その要旨を逸脱しない範囲で、檜々変形して実施するこ
とができる・例えば１前記ＣＶＤ法によゐイオン注入制
御層は、前記第６図（ｄ）に示す形状に形成される膜で
あればシリコン酸化膜、Ｐ２Ｏ（リン・シリケート・ガ
ラス）膜、多結晶シリコン膜、アル建ニウム膜等でもよ
く１またこれらを組み合わせた多層膜でもよい。また、
半導体基板としてはＰｇを用いたが、ｎ型を用いてもよ
いのは勿論である。ただしこの場合、前記第１および＃
Ｉ２の不純物を変える会費がある。つ１夛、第１の不純
物は半導体基板と同導電麺を作るもので、第２の不純物
は半導体基板と逆導電臘を作る−ので、かつ第２の不純
物のイオン注入量が第１の不純物のイオン注入量より少
ないものであればよいφｔた、ＭＯ８トランソスタに限
らず％ｃ −Ｂｉ！Ｏｓその他の半導体装置に適用でき
るのも勿論のむとマある・Next, a field oxide film 19 is formed using a thermal oxidation method as shown in FIG.
After removing 3, a MOB transistor is fabricated by forming f-) electrodes, wiring layers, etc. using a well-known technique.The thus formed MOB
) Lanzosta has the impurity distribution shown in FIG.
It can be carried out with various modifications without departing from the gist of the invention. For example, 1. The ion implantation control layer by the CVD method may be a film formed in the shape shown in FIG. 6(d). For example, it may be a silicon oxide film, a P2O (phosphorus silicate glass) film, a polycrystalline silicon film, an aluminum film, or a multilayer film combining these. Also,
Although Pg was used as the semiconductor substrate, it goes without saying that an n-type substrate may also be used. However, in this case, the first and #
There is a fee to change the impurity of I2. First, the first impurity forms the same conductive layer as the semiconductor substrate, and the second impurity forms the opposite conductive layer with the semiconductor substrate. φt is sufficient as long as it is less than the ion implantation amount of %c-Bi! Of course, it is also useful to be able to apply it to OS and other semiconductor devices.
第１図（ａ）〜（ｄ）は従来の選択酸化法を用いたＭＯ
Ｂトランジスタ袈造工程を示す断面図、第２図は従来法
により得られたトランジスタのしきい値電圧のチャネル
幅依存性を示す特性図、第３図は従来法による酸化膜シ
リコンとの界面における不純物分布を示す特性図、第４
図は本発明による酸化膜とシリコンとの界面における不
純物分布を示す特性図、第５図は本発明により得られる
トランジスタのしきい値電圧のチャネル幅依存性を示す
特性図、第６図（ａ）〜葎）は本発明の一実施例に係わ
るＭＯＢ ）ランジスタ製造工糧を示す断面図である。
１１・・・ｐ型シリコン基板（半導体基板）、１２・・
・酸化膜、ＩＪ・・・窒化シリコン披（耐鈑化性被ＩＩ
）、１４°゛フ゛オドレジスト、１５・・・酸化膜（イ
オン注入制御層）、１１・・・メロンイオン注入層、１
ａ・・・砒素イオン注入層、１＃・・・フィールド酸化
膜。
第１図
第２図
第３図
一干ッネーｂｔｓｗ−
第５図
第６図
２
第６図
ｓFigures 1 (a) to (d) show MO using the conventional selective oxidation method.
A cross-sectional view showing the B transistor fabrication process, Fig. 2 is a characteristic diagram showing the channel width dependence of the threshold voltage of a transistor obtained by the conventional method, and Fig. 3 is a cross-sectional view showing the channel width dependence of the threshold voltage of the transistor obtained by the conventional method. Characteristic diagram showing impurity distribution, 4th
5 is a characteristic diagram showing the impurity distribution at the interface between an oxide film and silicon according to the present invention, FIG. 5 is a characteristic diagram showing the channel width dependence of the threshold voltage of a transistor obtained according to the present invention, and FIG. ) to ) are sectional views showing MOB transistor manufacturing equipment according to an embodiment of the present invention. 11...p-type silicon substrate (semiconductor substrate), 12...
・Oxide film, IJ...silicon nitride (paneling resistance II)
), 14° photoresist, 15... oxide film (ion implantation control layer), 11... melon ion implantation layer, 1
a... Arsenic ion implantation layer, 1#... Field oxide film. Figure 1 Figure 2 Figure 3 Ichikune btsw- Figure 5 Figure 6 Figure 2 Figure 6 s
Claims (1)
に熱酸化層を形成する工程を含む半導体装置の製造方法
において、上記半導体基板上に耐酸化性被膜を選択的に
形成したのち、上記半導体基板および耐酸化性被膜上の
全面にイオン注入制御層を堆積し、次いで上記イオン注
入制御層を介して前記半導体基板と同導電型を作る第１
の不純物を上記半導体基板にイオン注入し、次いで前記
イオン注入制御層を除去し、次いで前記半導体基板と逆
導電臘を作る第２の不純物を前記第１の不純物より少な
い注入量で上記半導体基板にイオン注入し、しかるのち
前記半導体基板の前記耐酸化性被膜で覆われていない部
分に熱酸化層を形成することを特徴とする半導体装置の
製造方法。In a method for manufacturing a semiconductor device including a step of selectively forming a thermal oxidation layer on a semiconductor substrate using an oxidation-resistant film as a mask, the oxidation-resistant film is selectively formed on the semiconductor substrate, and then the semiconductor A first layer that deposits an ion implantation control layer on the entire surface of the substrate and the oxidation-resistant film, and then forms the same conductivity type as the semiconductor substrate through the ion implantation control layer.
ions of an impurity are implanted into the semiconductor substrate, the ion implantation control layer is removed, and a second impurity that forms a conductivity opposite to the semiconductor substrate is implanted into the semiconductor substrate in a smaller amount than the first impurity. 1. A method of manufacturing a semiconductor device, comprising implanting ions and then forming a thermal oxidation layer on a portion of the semiconductor substrate not covered with the oxidation-resistant film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4318282A JPS58159377A (en) | 1982-03-18 | 1982-03-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4318282A JPS58159377A (en) | 1982-03-18 | 1982-03-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58159377A true JPS58159377A (en) | 1983-09-21 |
Family
ID=12656749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4318282A Pending JPS58159377A (en) | 1982-03-18 | 1982-03-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159377A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6097637A (en) * | 1983-11-01 | 1985-05-31 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1982
- 1982-03-18 JP JP4318282A patent/JPS58159377A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6097637A (en) * | 1983-11-01 | 1985-05-31 | Matsushita Electronics Corp | Manufacture of semiconductor device |
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