JPS59194439A - Method for forming pattern of semiconductor device - Google Patents
Method for forming pattern of semiconductor deviceInfo
- Publication number
- JPS59194439A JPS59194439A JP6830583A JP6830583A JPS59194439A JP S59194439 A JPS59194439 A JP S59194439A JP 6830583 A JP6830583 A JP 6830583A JP 6830583 A JP6830583 A JP 6830583A JP S59194439 A JPS59194439 A JP S59194439A
- Authority
- JP
- Japan
- Prior art keywords
- film
- radiation
- layer
- etching
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 26
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000005530 etching Methods 0.000 claims abstract description 22
- 230000005855 radiation Effects 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims 1
- 238000002161 passivation Methods 0.000 abstract description 11
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 28
- 239000005360 phosphosilicate glass Substances 0.000 description 15
- 238000000059 patterning Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000010894 electron beam technology Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000012010 growth Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
(発明の技術分野)
本発明はレノスト層を用いない半導体装置の・ぐターン
形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for forming a pattern in a semiconductor device without using a renost layer.
(従来技術の説明)
一般に半導体装置の製造に当たシいわゆるマスキング技
術を用い半導体装置に必要とされる各種の領域、配線パ
ターンその他の構成部分を形成している。(Description of Prior Art) In general, when manufacturing a semiconductor device, a so-called masking technique is used to form various regions, wiring patterns, and other constituent parts required for the semiconductor device.
第1図は半導体層又は金属薄膜等の基層上に形成した絶
縁薄膜のような堆積層の・ぐターニング工程、特に−例
としてパッシベーション膜のパターニング工程を示す工
程図である。この第1図A〜Cに示す従来例では、先ず
第1図Aに示すように半導体基板上に形成した半導体回
路素子を具える半導体層(又は半導体装置ともいう)1
上にパッシベーション膜2を形成する。通常はこの・や
ッシベーション膜としてリン珪酸ガ゛ラス(PSG)又
は窒化珪素(s 13N4)の膜を用いている。このノ
Pツノベーンヨン膜をパターン成形する場合には、第1
図Bに示すようにこの・ぐッシベーション膜2上にレジ
スト層3を塗布し、然る後フォトマスクを介して選択的
に紫外線4″f:照射し、その後に第1図Cに示すよう
にこのレジスト層3の選択エツチングを行って所定箇所
にレジスト層3を残す。そしてその後残存レジスト層3
をマスク層として用いて下側の7J?ツシベーンヨン膜
2の選択エツチングを行う。FIG. 1 is a process diagram illustrating a patterning process of a deposited layer such as an insulating thin film formed on a base layer such as a semiconductor layer or a metal thin film, and particularly, as an example, a patterning process of a passivation film. In the conventional example shown in FIGS. 1A to 1C, first, as shown in FIG.
A passivation film 2 is formed thereon. Usually, a film of phosphosilicate glass (PSG) or silicon nitride (S13N4) is used as this passivation film. When pattern forming this NOP horn veinyon film, the first
As shown in FIG. This resist layer 3 is selectively etched to leave the resist layer 3 at predetermined locations.Then, the remaining resist layer 3
using the lower 7J? as a mask layer. Selective etching of the blade film 2 is performed.
このように従来のバターニング工程では、レジスト層e
tE布し、これをマスクとして絶縁膜であるパッシベー
ション膜をエツチングするのであるから、この絶縁膜と
レジスト層との間の密着性の問題力・らサイドエツチン
グが生ずるという欠点がある。又、レジスト層を用い、
紫外線によシレジスト層のパターニングを行う工程で、
光の回折とか多重反射とかの光学的効果によシフオドマ
スクと・母ターン成形されたレノストマスクとの寸法変
換差が生じ正確な・ぐターニングを行い得ないという欠
点がある。さらに、使用するレジスト層は有機物質であ
るので、其の後の工程に進む前に充分に洗浄する必要が
あり、従ってそれだけ工程数が増え、製造コストが上が
る欠点がある。In this way, in the conventional patterning process, the resist layer e
Since the passivation film, which is an insulating film, is etched using a tE cloth as a mask, there are drawbacks such as problems in adhesion between the insulating film and the resist layer, and side etching. Also, using a resist layer,
In the process of patterning the resist layer using ultraviolet rays,
There is a drawback that accurate turning cannot be performed because of optical effects such as light diffraction and multiple reflections that cause a difference in dimensional conversion between the shifted mask and the master turn molded Renost mask. Furthermore, since the resist layer used is an organic material, it must be thoroughly cleaned before proceeding to subsequent steps, which has the drawback of increasing the number of steps and manufacturing costs.
(発明の目的)
本発明の目的は上述した従来のパターン形成方法の有す
る欠点を除去したレジスト層を用いない半導体装置のパ
ターン形成方法を提供することにある。(Objective of the Invention) An object of the present invention is to provide a method of patterning a semiconductor device without using a resist layer, which eliminates the drawbacks of the conventional patterning method described above.
(発明の構成)
この目的の達成を図るため本発明によれば1先ず基層表
面上にノRターン成形されるべき堆積層を形成し、続い
てこの堆積層に対し放射を選択的に照射し、この堆積層
のうちこの放射の照射を受けた部分と受けな−かった部
分とにおけるエツチング速度の差を利用して前述の堆積
層のエツチングを行ってパターン成形することを特徴と
する。(Structure of the Invention) In order to achieve this object, according to the present invention, first, a deposited layer to be formed into a R-turn is formed on the surface of the base layer, and then this deposited layer is selectively irradiated with radiation. The method is characterized in that the deposited layer is etched to form a pattern by utilizing the difference in etching rate between the portions of the deposited layer that are irradiated with the radiation and the portions that are not.
(実施例の説明)
以下、図面につき本発明の半導体装置のパターン形成方
法の実施例につき説明する。(Description of Examples) Examples of the method for forming a pattern of a semiconductor device of the present invention will be described below with reference to the drawings.
第2図A〜Cは本発明によるパターン形成方法の一実施
例を示す工程図であり、11は基層、例えば、半導体基
板上に形成した種々の半導体回路素子を具える半導体層
、12はパッシベーション膜、13はレーザ光又は電子
線等の放射、14はこの放射を照射されたパッシベーシ
ョン部分及び15に放射を照射されなかった・ぐッシベ
ーション部分である。2A to 2C are process diagrams showing an embodiment of the pattern forming method according to the present invention, 11 is a base layer, for example, a semiconductor layer comprising various semiconductor circuit elements formed on a semiconductor substrate, 12 is a passivation layer In the film, 13 is a radiation such as a laser beam or an electron beam, 14 is a passivation portion that is irradiated with this radiation, and 15 is a passivation portion that is not irradiated with radiation.
先ず第2図Aに示すように半導体回路素子が形成されて
いる半導体層11上に堆積層としてパッシベーション膜
12を従来既知の方法によ′りviする。続いてこのパ
ッシベーション膜のパターン成形を行うに当たシ、第2
図Bに示すように、所望の・ぐターンに従ってレーザ光
又は電子線等の放射13をこのパッシベーション膜12
に対し選択的に照射する。この時、ノクツシベーション
膜12のうち放射の照射を受けた部分14は等制約に熱
処理を受けたことになシ、従ってその部分14の緊密性
が増す。その結果、放射の照射を受けた部分14と受け
なかった部分15とにおけるエツチング速度に差が生じ
、前者の部分14のエツチング速度は後者の部分15の
エツチング速度に比べて数十分の一七なシ極めて遅くな
る。従って放射照射後、この・母ッシベーション膜12
にxt Lエツチング処理全行うと第2図Cに示すよう
に放射の照射を受けた部分14が残存し、照射を受けな
かった部分はエツチング除去され、よって・母ッシベー
ション膜12の・ぐターン成形が完了する。First, as shown in FIG. 2A, a passivation film 12 is deposited as a deposited layer on the semiconductor layer 11 on which semiconductor circuit elements are formed by a conventionally known method. Next, when patterning this passivation film, a second
As shown in FIG.
selectively irradiates. At this time, the portion 14 of the noxivation film 12 that has been irradiated with radiation has not been subjected to the same heat treatment, and therefore the tightness of the portion 14 is increased. As a result, there is a difference in the etching speed between the portion 14 that has been irradiated with radiation and the portion 15 that has not been irradiated, and the etching speed of the former portion 14 is several tenths of the etching speed of the latter portion 15. It becomes extremely slow. Therefore, after radiation irradiation, this mother passivation film 12
When the entire xt L etching process is carried out, the portion 14 that has been irradiated with radiation remains as shown in FIG. is completed.
本発明によるl?ターン成形方法において)絶縁層とし
ての堆積層12を例えはリン珪酸ガラス(PSC;とい
う)とし、放射としてレーザ光を使用する場合には、炭
酸ガスレーザがこの堆積層であるPSC膜に吸収され易
く使用して好適である。この場合、使用するレーザ光の
エネルギーは約Q、5 J/cm2〜10 J/CJn
2の範囲とするのが好適である。レーザ光がPSC膜で
多重反射する点を考慮してエネルギーの有効利用を図る
ため、このPSC膜のノ厚さを予め適蟲に選定すること
によりよシ効果的な熱処理を行うことができる。l according to the invention? (In the turn forming method) When the deposited layer 12 as an insulating layer is made of, for example, phosphosilicate glass (PSC) and laser light is used as radiation, the carbon dioxide gas laser is easily absorbed by the deposited layer, which is the PSC film. It is suitable to use. In this case, the energy of the laser beam used is approximately Q, 5 J/cm2 to 10 J/CJn
A range of 2 is preferable. In order to effectively utilize energy by taking into consideration the multiple reflection of laser light on the PSC film, more effective heat treatment can be performed by appropriately selecting the thickness of the PSC film in advance.
又放射としてレーザ光の代わシに電子線ヲ用いてもよい
。この場合にもレーザ光のエネルギーと等価のエネル・
ギーの電子線’z PSG膜12に入射させることによ
りレーザ光の場合と同様に良好に放射の照射前後におけ
るPSC膜のエツチング速度に差を生じさせることが出
来る。Also, an electron beam may be used as the radiation instead of a laser beam. In this case as well, the energy equivalent to the energy of the laser beam is
By making the electron beam 'z of radiation incident on the PSG film 12, it is possible to produce a difference in the etching rate of the PSC film before and after irradiation, as well as in the case of laser light.
この様にして放射の照射を受けたPSC膜のエツチング
速度は照射を受けなかったすなわち照射前のPSC膜に
比べて数十分の−に減少し、その後のPSC膜のエツチ
ング処理によってPSC膜の・ぐターン成形を効率良く
かつ正確に行うことが出来る。In this way, the etching rate of the PSC film irradiated with radiation was reduced to several tenths of that of the PSC film that was not irradiated, that is, before irradiation, and the subsequent etching treatment of the PSC film reduced the etching rate of the PSC film.・Can perform turn forming efficiently and accurately.
又、エツチング処理の際のこのようなエッテング速度の
差を予め考慮して、残すべきPSG膜の厚さを予め予想
して堆積させるべきPSG膜の厚さを有効的に設定出来
る、
(効果の説明)
本発明は半導体装置の・やターン成形に轟たり、レノス
ト層を用いることなく基層上のパターン成形されるべき
堆積層に放射の選択照射を行ってこの堆積層の緊密性を
増大せしめて照射部分のエツチング速度を変化せしめ、
この照射前後のエツチング速度の差を用いて堆積層のエ
ツチング除去を行ってパターン成形する方法であるから
、従来の方法に比べてサイドエツチングの量を正確に予
測することが出来、又レジスト層を用いないので従来の
ような寸法変換差が生ぜず従って正確にパターン成形を
行い得る利点がある。さらにレジスト層を使用しないの
で、これを完全に洗浄する工程を省略出来、従ってそれ
だけ製造工程が簡単化し得ると共に製造コストが低下す
るという利点がある。Furthermore, it is possible to effectively set the thickness of the PSG film to be deposited by considering in advance the difference in etching speed during the etching process and predicting the thickness of the PSG film to be left in advance. Description: The present invention is applicable to turn forming of semiconductor devices, and increases the tightness of a deposited layer to be patterned on a base layer by selectively irradiating the deposited layer to be patterned on a base layer without using a rennost layer. By changing the etching speed of the irradiated area,
Since this method uses the difference in etching speed before and after irradiation to remove the deposited layer by etching and form a pattern, it is possible to predict the amount of side etching more accurately than conventional methods, and it is also possible to Since it is not used, there is no dimensional conversion difference as in the conventional case, and therefore there is an advantage that pattern formation can be performed accurately. Furthermore, since no resist layer is used, the step of completely cleaning the resist layer can be omitted, which has the advantage of simplifying the manufacturing process and lowering the manufacturing cost.
(変形例の説明)
不発明は上述した実施例にのみ限定されるものではなく
、多くの変更又は変形を行い得ること明らかである。(Description of Modifications) It is clear that the invention is not limited only to the embodiments described above, but that many modifications and variations can be made.
例えば上述した実施例では堆積層として半導体の特性を
安定化するだめの絶縁層としての・ぐツシベーション膜
のパターニングにつき説明したが、本発明はこれに限定
されず、広く一般に半導体装置の製造に際しパターン成
形されるべき層(又は膜)、例えば半導体層、半絶縁層
又は金属層にも適用出来る。、従って堆積層として上述
したリン、珪酸ガラスの他、所要に応じた材料又は物質
の層を使用出来る。For example, in the above-mentioned embodiments, the patterning of a gutsivation film as a deposited layer and an insulating layer for stabilizing the characteristics of a semiconductor was explained, but the present invention is not limited to this, and is generally applicable to the manufacturing of semiconductor devices. It can also be applied to layers (or films) to be patterned, such as semiconductor layers, semi-insulating layers or metal layers. Therefore, in addition to the above-mentioned phosphorus and silicate glass, a layer of any material or substance can be used as the deposited layer.
さらに基層として半導体層を用いたが、半導体装置の製
造に一般に使用される金属薄膜、絶縁膜その他所要の層
又は支持体を使用することも出来る。Furthermore, although a semiconductor layer is used as the base layer, it is also possible to use a metal thin film, an insulating film, or other necessary layers or supports commonly used in the manufacture of semiconductor devices.
尚、上述した堆積層の堆積は被着、成長、酸化接着その
他生導体技術で普通に用いられている方法で行うことが
出来ること明らかである。It will be appreciated that the deposition of the deposited layers described above can be carried out by deposition, growth, oxidative bonding, or any other method commonly used in the raw conductor technology.
本発明は単一の半導体装置はもとより集積半導体装置に
適用して好適である。The present invention is suitable for application to not only a single semiconductor device but also an integrated semiconductor device.
第1図A−Cは従来の半導体装置のパターン形成方法を
説明するだめの工程図、
第2図A−Cは本発明による半導体装置のパターン形成
方法を説明するための、各製造段階における半導体装置
の状態を拡大して示す工程図である。
1ノ・・・基層、12・・・堆積層、13・・・放射、
14放射の照射を受けた堆積層の部分、15・・・放射
の照射を受けていない堆積層の部分。
特許出願人 沖電気工業株式会社
第1図1A to 1C are process diagrams for explaining a conventional pattern forming method for a semiconductor device, and FIGS. 2A to 2C are process diagrams for explaining a semiconductor device pattern forming method according to the present invention at each manufacturing stage. It is a process diagram showing the state of the device in an enlarged manner. 1. Base layer, 12. Sedimentary layer, 13. Radiation,
14 A portion of the deposited layer that has been irradiated with radiation, 15... A portion of the deposited layer that has not been irradiated with radiation. Patent applicant Oki Electric Industry Co., Ltd. Figure 1
Claims (1)
該堆積層に対し放射を選択的に照射し、該堆積層のうち
該放射の照射を受けた部分と受けなかった部分とにおけ
るエツチング速度の差を利用して前記堆積層のエツチン
グを行ってパターン成形することを特徴とする半導体装
置のパターン形成方法。forming a deposited layer to be patterned on the substrate surface;
The deposited layer is selectively irradiated with radiation, and the deposited layer is etched using the difference in etching rate between the portions of the deposited layer that are irradiated with the radiation and the portions that are not. A method for forming a pattern of a semiconductor device, characterized by molding.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6830583A JPS59194439A (en) | 1983-04-20 | 1983-04-20 | Method for forming pattern of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6830583A JPS59194439A (en) | 1983-04-20 | 1983-04-20 | Method for forming pattern of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59194439A true JPS59194439A (en) | 1984-11-05 |
Family
ID=13369946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6830583A Pending JPS59194439A (en) | 1983-04-20 | 1983-04-20 | Method for forming pattern of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59194439A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04188621A (en) * | 1990-11-19 | 1992-07-07 | Canon Inc | Optical surface treatment method and device |
WO2000065642A1 (en) * | 1999-04-26 | 2000-11-02 | Shin-Etsu Handotai Co., Ltd. | Production methods of compound semiconductor single crystal and compound semiconductor element |
-
1983
- 1983-04-20 JP JP6830583A patent/JPS59194439A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04188621A (en) * | 1990-11-19 | 1992-07-07 | Canon Inc | Optical surface treatment method and device |
WO2000065642A1 (en) * | 1999-04-26 | 2000-11-02 | Shin-Etsu Handotai Co., Ltd. | Production methods of compound semiconductor single crystal and compound semiconductor element |
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