JP2891538B2 - Manufacturing method of wiring board - Google Patents
Manufacturing method of wiring boardInfo
- Publication number
- JP2891538B2 JP2891538B2 JP2336014A JP33601490A JP2891538B2 JP 2891538 B2 JP2891538 B2 JP 2891538B2 JP 2336014 A JP2336014 A JP 2336014A JP 33601490 A JP33601490 A JP 33601490A JP 2891538 B2 JP2891538 B2 JP 2891538B2
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- polyimide resin
- cavity
- conductor circuit
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は配線基板の製造方法に関し、特に半導体素子
等の電子部品を搭載するためのキャビティーを備えてな
る配線基板の製造方法に関する。The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board having a cavity for mounting an electronic component such as a semiconductor element.
［従来の技術］ 従来、予め導体回路が形成されたセラミックス基板の
表面に、スピンコータ等によってポリイミド前駆体から
なるワニスを塗布した後、キャビティーを形成しない部
位に光を照射して該部位のポリイミド前駆体を光硬化さ
せることにより、ポリイミド樹脂層を形成していた。そ
の後、未硬化のポリイミド前駆体をエッチング処理する
ことにより、セラミックス基板上のポリイミド樹脂層の
一部分にキャビティーを形成していた（ホトリソグラフ
ィー法）。[Related Art] Conventionally, a varnish made of a polyimide precursor is applied to the surface of a ceramic substrate on which a conductor circuit has been formed in advance by a spin coater or the like, and then light is applied to a portion where a cavity is not formed to obtain a polyimide at the portion. The polyimide resin layer was formed by photocuring the precursor. Thereafter, an uncured polyimide precursor was etched to form a cavity in a part of the polyimide resin layer on the ceramic substrate (photolithography method).
［発明が解決しようとする課題］ ところが、膜厚が20〜30μｍという比較的厚膜なポリ
イミド樹脂層を形成し、かつ、その樹脂層の一部分にそ
の膜厚と同じ深さのキャビティーを形成するためには、
前記ホトリソグラフィーを複数回（通常は３回以上）繰
り返して、数μｍずつポリイミド樹脂層を順次積層しな
がら、所望する深さのキャビティーを形成しなければな
らなかった。そのため、キャビティー形成のための製造
工程数が多くなるという問題があった。[Problems to be Solved by the Invention] However, a relatively thick polyimide resin layer having a film thickness of 20 to 30 μm is formed, and a cavity having the same depth as the film thickness is formed in a part of the resin layer. To do
The cavity having a desired depth had to be formed by repeating the photolithography a plurality of times (usually three or more times) and sequentially laminating polyimide resin layers by several μm. Therefore, there is a problem that the number of manufacturing steps for forming the cavity is increased.
本発明は上記事情に鑑みなされたものであり、その目
的は、セラミックス基板上に形成されたポリイミド樹脂
層の一部にキャビティーを従来よりも簡便かつ効率的に
形成することが可能な配線基板の製造方法を提供するこ
とにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wiring board which can form a cavity in a part of a polyimide resin layer formed on a ceramic substrate more simply and efficiently than in the past. It is to provide a manufacturing method of.
［課題を解決するための手段及び作用］ 上記課題を解決するために本発明は、予め導体回路が
形成されたセラミックス基板の表面に、前記導体回路を
被覆するポリイミド樹脂層を形成した後、その樹脂層に
エキシマレーザー光を照射して樹脂層の一部を消失さ
せ、前記導体回路の一部を露出するキャビティーを形成
している。[Means and Actions for Solving the Problems] In order to solve the above problems, the present invention provides a method for forming a polyimide resin layer covering the conductor circuit on a surface of a ceramic substrate on which the conductor circuit is formed in advance. An excimer laser beam is applied to the resin layer to cause a part of the resin layer to disappear, thereby forming a cavity exposing a part of the conductor circuit.
この方法によれば、ポリイミド樹脂層が厚膜な場合で
も、エキシマレーザー光の照射によって該樹脂層の一部
に所望する深さのキャビティーが簡便かつ確実に形成さ
れる。According to this method, even when the polyimide resin layer is thick, a cavity having a desired depth is easily and reliably formed in a part of the resin layer by excimer laser light irradiation.
エキシマレーザー（EXCIMA LASER）光を使用すると
き、ポリイミド樹脂層が20〜30μｍと膜厚な場合でも、
一回の照射によってこの厚さのポリイミド樹脂層を消失
させ、該照射部位にキャビティーを形成することができ
る。When using excimer laser (EXCIMA LASER) light, even if the polyimide resin layer is as thick as 20 to 30 μm,
The polyimide resin layer having this thickness can be eliminated by one irradiation, and a cavity can be formed at the irradiation site.
また、エキシマレーザー光が有益な点は、ポリイミド
樹脂層を消失させた部分に露出される加工面が平滑に仕
上がると共に、微小なバイアホール等の加工にも適用す
ることができる点にある。これに対し、仮に炭酸ガスレ
ーザーをポリイミド樹脂層に照射した場合、ポリイミド
が熱に侵され易いため、エネルギー（パルス）コントロ
ールが非常に困難で、微小なバイアホール等の加工に適
用することが困難であった。The excimer laser beam is useful in that the processed surface exposed to the portion where the polyimide resin layer has disappeared is finished smoothly, and can be applied to processing of minute via holes and the like. On the other hand, if the carbon dioxide laser is irradiated to the polyimide resin layer, the polyimide is easily affected by heat, so it is very difficult to control the energy (pulse), and it is difficult to apply it to processing of minute via holes and the like. Met.
更にこの方法によれば、エキシマレーザー光を使用し
ているためその出力が常に一定であるならば、パルス照
射の回数を制御することによって、消失させるポリイミ
ド樹脂の深さ、即ち形成されるキャビティーの深さを調
節することができる。Furthermore, according to this method, if the output is always constant because excimer laser light is used, the depth of the polyimide resin to be eliminated by controlling the number of times of pulse irradiation, that is, the cavity to be formed, The depth of the can be adjusted.
尚、前記セラミックス基板としては、アルミナ製基
板、窒化アルミニウム製基板等があげられる。The ceramic substrate includes an alumina substrate, an aluminum nitride substrate, and the like.
前記導体回路を構成する素材としては、タングステ
ン、銀、銅等の金属材料があげられる。この導体回路は
セラミックス基板上にスパッタリング、メッキ等の手法
によって形成される。Examples of the material constituting the conductor circuit include metal materials such as tungsten, silver, and copper. This conductor circuit is formed on the ceramic substrate by a technique such as sputtering or plating.
［実施例］ 以下に本発明を具体化した一実施例について、図面を
参照しながら説明する。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.
第１図に示すように、窒化アルミニウム多層配線基板
１（縦76.2mm×横76.2mm×厚さ0.635mm）の上面には、
マスクスパッタリング等の手法によって所定パターンの
導体回路２が予め形成されている。この配線基板１は、
複数枚の窒化アルミニウム製グリーンシートを積層して
なる積層体を同時焼成することにより形成されたもので
ある。この配線基板１はスピンコータ（図示せず）の回
転テーブル上に固定され、この回転テーブルと共に高速
回転させた状態で、その上部からポリイミド前駆体（株
式会社東レ製商品名：フォトニースUR3140）のワニスを
少量ずつ供給することにより、配線基板１の表面にポリ
イミド前駆体が均一に塗布される。そして、この配線基
板１を300〜400℃で加熱し、前記ポリイミド前駆体を熱
硬化させることにより、配線基板１の表面には膜厚が25
μｍのポリイミド樹脂層３が形成される。As shown in FIG. 1, the upper surface of the aluminum nitride multilayer wiring board 1 (length 76.2 mm × width 76.2 mm × thickness 0.635 mm)
The conductor circuit 2 having a predetermined pattern is formed in advance by a technique such as mask sputtering. This wiring board 1
It is formed by simultaneously firing a laminate formed by laminating a plurality of green sheets made of aluminum nitride. The wiring board 1 is fixed on a rotating table of a spin coater (not shown), and is rotated at a high speed together with the rotating table. From above, a varnish of a polyimide precursor (trade name: Photo Nice UR3140, manufactured by Toray Industries, Inc.) Is supplied little by little, the polyimide precursor is uniformly applied to the surface of the wiring board 1. Then, the wiring substrate 1 is heated at 300 to 400 ° C. and the polyimide precursor is thermally cured, so that the surface of the wiring substrate 1 has a thickness of 25 mm.
A μm polyimide resin layer 3 is formed.
次に、この配線基板１を前記ポリイミド樹脂層３が上
になるように、第３図に示すエキシマレーザー照射装置
４の照射台５上に固定した。この照射台５はＸ−Ｙ平面
Ｐに沿ってＸ軸及びＹ軸のいずれの方向にも移動するこ
とができる。Next, the wiring board 1 was fixed on an irradiation table 5 of an excimer laser irradiation apparatus 4 shown in FIG. The irradiation table 5 can move along the XY plane P in both directions of the X axis and the Y axis.
ここで、エキシマレーザー照射装置４は、前記照射台
５の他に、レーザー発信管６、型枠７、反射鏡８及び集
光レンズ９を備えている。型枠７はレーザー発信管６と
反射鏡８との間に配設され、その中央部には25mm×8mm
の長方形状のくり抜き7aが設けられている。そのため、
レーザー発信管６から発射されたエキシマレーザーの光
束は、型枠７によって断面長方形状（25mm×8mm）の光
束に整えられて、反射鏡８に照射される。Here, the excimer laser irradiation device 4 includes a laser transmission tube 6, a mold 7, a reflecting mirror 8, and a condenser lens 9 in addition to the irradiation table 5. The formwork 7 is disposed between the laser transmission tube 6 and the reflecting mirror 8 and has a central portion of 25 mm × 8 mm.
A rectangular hollow 7a is provided. for that reason,
The light beam of the excimer laser emitted from the laser transmission tube 6 is shaped into a light beam having a rectangular cross section (25 mm × 8 mm) by the mold 7, and is irradiated on the reflecting mirror 8.
反射鏡８によって反射されたエキシマレーザーの光束
は集光レンズ９を通過した後、照射台５上に固定された
配線基板１の一部表面に照射される。この時、エキシマ
レーザーの光束は集光レンズ９の作用によって8mm×3mm
の断面長方形状にまで絞り込まれる。The light beam of the excimer laser reflected by the reflecting mirror 8 passes through the condenser lens 9 and is then irradiated on a part of the surface of the wiring board 1 fixed on the irradiation table 5. At this time, the luminous flux of the excimer laser is 8 mm × 3 mm by the action of the condenser lens 9.
Is narrowed down to a rectangular section.
配線基板１に対するエキシマレーザーの照射は間欠的
に行われる。一回の照射が完了する毎に照射台５は平面
Ｐ上を所定量ずつ間欠的に移動され、配線基板１に対す
るレーザーの照射位置が変更される。こうして第４図に
示すように、配線基板１表面のポリイミド樹脂層３中央
の長方形状の領域全体に、エキシマレーザー光が照射さ
れる。この結果、第2,4図に示すように、該領域のポリ
イミド樹脂が消失され、キャビティー10が形成されると
共に、その樹脂の下側にあった導体回路２及び配線基板
１の窒化アルミニウム面が露出される。The irradiation of the excimer laser to the wiring substrate 1 is performed intermittently. Each time one irradiation is completed, the irradiation table 5 is intermittently moved by a predetermined amount on the plane P, and the irradiation position of the laser on the wiring substrate 1 is changed. In this way, as shown in FIG. 4, the entire rectangular area at the center of the polyimide resin layer 3 on the surface of the wiring board 1 is irradiated with excimer laser light. As a result, as shown in FIGS. 2 and 4, the polyimide resin in the region is lost, the cavity 10 is formed, and the aluminum nitride surface of the conductor circuit 2 and the wiring board 1 under the resin are formed. Is exposed.
本実施例のエキシマレーザー光によれば、導体回路２
及び窒化アルミニウムに対して悪影響を及ぼすことな
く、ポリイミド樹脂のみを確実に消失させることができ
る。従って、キャビティー10内にて露出する導体回路２
及び窒化アルミニウム面上には、ポリイミド樹脂の残渣
が残ることはほとんどなく、キャビティー10内の底面
（露出された導体回路２及び配線基板１の窒化アルミニ
ウム面）は平滑に仕上げられる。According to the excimer laser beam of this embodiment, the conductor circuit 2
In addition, only the polyimide resin can be reliably eliminated without adversely affecting aluminum nitride. Therefore, the conductor circuit 2 exposed in the cavity 10
The residue of the polyimide resin hardly remains on the aluminum nitride surface, and the bottom surface in the cavity 10 (the exposed aluminum surface of the conductive circuit 2 and the wiring substrate 1) is finished smoothly.
レーザー照射後は必要に応じ、配線基板１を有機溶剤
等にて洗浄してもよい。尚、この後、ポリイミド樹脂層
上には導体回路が形成されると共に、前記キャビティー
10内に固定されるシリコンチップ等との間に、ワイヤー
ボンディングが形成される。After the laser irradiation, if necessary, the wiring substrate 1 may be washed with an organic solvent or the like. Thereafter, a conductor circuit is formed on the polyimide resin layer, and the cavity is formed.
Wire bonding is formed between the silicon chip and the like fixed in the semiconductor device 10.
このように本実施例によれば、従来のホトリソグラフ
ィー法に比べ非常に少ない工程で、ポリイミド樹脂層３
の一部にキャビティー10を簡便かつ確実に形成すること
ができる。As described above, according to this embodiment, the polyimide resin layer 3 can be formed in a very small number of steps as compared with the conventional photolithography method.
The cavity 10 can be simply and reliably formed in a part of the.
また、スピンコータを使用してポリイミド前駆体のワ
ニスをセラミックス基板の表面に塗布する場合、その基
板の四隅部でワニスが盛り上がる傾向にある。そのた
め、従来のホトリソグラフィー法のように塗布及び光硬
化の工程が複数回に及ぶ場合には、基板の中央部に比し
て四隅部がかなり高くなっていた。そして、ポリイミド
樹脂層上に基板の中央部と四隅部とにまたがる導体回路
が形成されている場合、その回路への通電に伴って熱が
発生すると、熱応力によって前記回路が断線することが
あった。In addition, when a varnish of a polyimide precursor is applied to the surface of a ceramic substrate using a spin coater, the varnish tends to rise at four corners of the substrate. Therefore, when the coating and photo-curing steps are performed a plurality of times as in the conventional photolithography method, the four corners are considerably higher than the center of the substrate. When a conductor circuit is formed on the polyimide resin layer over the center and the four corners of the substrate, if heat is generated when the circuit is energized, the circuit may be broken by thermal stress. Was.
しかし、本実施例によれば、25μｍという膜厚なポリ
イミド樹脂層をスピンコータによる一回の塗布と一回の
熱処理とによって形成することができるため、従来法に
比べ、配線基板の四隅部が中央部に対し高く盛り上がる
ということがない。それ故、ポリイミド樹脂層上に形成
された導体回路が、熱応力によって断線するというトラ
ブルを未然に防止することができる。However, according to this embodiment, the polyimide resin layer having a thickness of 25 μm can be formed by one application and one heat treatment using a spin coater. There is no high excitement for the club. Therefore, it is possible to prevent a trouble that the conductor circuit formed on the polyimide resin layer is disconnected due to thermal stress.
尚、本発明は上記実施例に限定されるものではなく、
ポリイミド樹脂層３の形成後、その上にキャビティー形
状に対応するくり抜きが形成されたコンタクトマスクを
載置すると共に、コンタクトマスクの全面にエキシマレ
ーザー光を照射することにより、一度にキャビティーを
形成してもよい。The present invention is not limited to the above embodiment,
After the polyimide resin layer 3 is formed, a contact mask having a cavity formed therein corresponding to the shape of the cavity is placed thereon, and the entire surface of the contact mask is irradiated with excimer laser light to form a cavity at one time. May be.
［発明の効果］ 以上詳述したように本発明によれば、セラミックス基
板上に形成されたポリイミド樹脂層の一部にキャビティ
ーを従来よりも簡便かつ効率的に形成することができ、
また、ポリイミド樹脂層を消失させた部分に露出される
加工面が平滑に仕上がるという優れた効果を奏する。[Effects of the Invention] As described in detail above, according to the present invention, cavities can be formed more easily and efficiently than in the past in a part of the polyimide resin layer formed on the ceramic substrate,
Also, there is an excellent effect that the processed surface exposed at the portion where the polyimide resin layer has disappeared is finished smoothly.
第１〜４図は本発明を具体化した一実施例を示し、第１
図はエキシマレーザー光照射前の状態を示す配線基板の
概略断面図、第２図はエキシマレーザー光照射後の状態
を示す配線基板の概略断面図、第３図はエキシマレーザ
ー照射装置の概略を示す説明図、第４図はエキシマレー
ザー光照射後の配線基板の平面図である。 １……窒化アルミニウム多層配線基板、２……導体回
路、３……ポリイミド樹脂層、10……キャビティー。1 to 4 show an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of a wiring board showing a state before excimer laser light irradiation, FIG. 2 is a schematic cross-sectional view of a wiring board showing a state after excimer laser light irradiation, and FIG. 3 shows a schematic of an excimer laser irradiation apparatus. FIG. 4 is a plan view of the wiring board after excimer laser light irradiation. 1 ... aluminum nitride multilayer wiring board, 2 ... conductor circuit, 3 ... polyimide resin layer, 10 ... cavity.
Claims (2)
クス基板（１）の表面に、前記導体回路（２）を被覆す
るポリイミド樹脂層（３）を形成した後、その樹脂層
（３）にエキシマレーザー光を照射して樹脂層（３）の
一部を消失させ、前記導体回路（２）の一部を露出する
キャビティー（10）を形成することを特徴とする配線基
板の製造方法。A polyimide resin layer (3) for covering said conductor circuit (2) is formed on the surface of a ceramic substrate (1) on which said conductor circuit (2) has been previously formed, and said resin layer (3) Irradiating a portion of the resin layer (3) with an excimer laser beam to form a cavity (10) exposing a portion of the conductor circuit (2). .
30μｍであることを特徴とする請求項１に記載の配線基
板の製造方法。2. The polyimide resin layer (3) has a thickness of 20 to 20.
The method according to claim 1, wherein the thickness is 30 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2336014A JP2891538B2 (en) | 1990-11-29 | 1990-11-29 | Manufacturing method of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2336014A JP2891538B2 (en) | 1990-11-29 | 1990-11-29 | Manufacturing method of wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04199893A JPH04199893A (en) | 1992-07-21 |
| JP2891538B2 true JP2891538B2 (en) | 1999-05-17 |
Family
ID=18294803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2336014A Expired - Lifetime JP2891538B2 (en) | 1990-11-29 | 1990-11-29 | Manufacturing method of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2891538B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4417245A1 (en) * | 1994-04-23 | 1995-10-26 | Lpkf Cad Cam Systeme Gmbh | High resolution structured metallisation prodn. |
| EP0727925A1 (en) * | 1995-02-14 | 1996-08-21 | Lpkf Cad/Cam Systeme Gmbh | Process for structured metallizing of the surface of substrates |
-
1990
- 1990-11-29 JP JP2336014A patent/JP2891538B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04199893A (en) | 1992-07-21 |
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