JPS59121923A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59121923A
JPS59121923A JP22871682A JP22871682A JPS59121923A JP S59121923 A JPS59121923 A JP S59121923A JP 22871682 A JP22871682 A JP 22871682A JP 22871682 A JP22871682 A JP 22871682A JP S59121923 A JPS59121923 A JP S59121923A
Authority
JP
Japan
Prior art keywords
layer
laser
insulating film
step parts
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22871682A
Other languages
Japanese (ja)
Other versions
JPH0410217B2 (en
Inventor
Yasuo Arima
康雄 有馬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22871682A priority Critical patent/JPS59121923A/en
Publication of JPS59121923A publication Critical patent/JPS59121923A/en
Publication of JPH0410217B2 publication Critical patent/JPH0410217B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To improve coverage at the step parts of a semiconductor device by performing heat treatment without deteriorating the characteristic of a semiconductor element by a method wherein a metal wiring layer of Al, etc., is formed, an insulating film adhered thereon is formed to the necessary pattern of the metal wiring in this condition, and laser annealing is performed from the upper side. CONSTITUTION:An insulating layer, an SiO2 layer 3 for example, having a contact hole 2 is formed on a silicon substrate 1, and when an Al layer 4 is formed extending over the whole surface, step parts 5 are generated. Then an insulating film 6 is adhered on the Al layer 4, and patterning is performed. Laser scanning is performed extending over the whole surface according to CO2 laser to perform heat treatment. When the laser beam is irradiated, the temperature of the Al layer 4 is risen only through the patterned insulating film 6, the step parts 5 also heated, and because the step parts are molten a little, step coverage is improved. At the regions not formed with the pattern of the insulating film 6 because the Al layer 4 is left in the exposed condition, even when laser is irradiated thereto, laser is reflected wholly, a semiconductor element formed in the silicon substance 1 is not heated.

Description

【発明の詳細な説明】 (1) 発明の技術分野 本発明は半導体装置の製造方法に係り、特にレーザアニ
ール等の熱処理方法を用いてアルミニウムの如き配線金
属層のステップカバーレンジの改善を行なう半導体装置
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to a semiconductor device in which the step coverage range of a wiring metal layer such as aluminum is improved using a heat treatment method such as laser annealing. The present invention relates to a method for manufacturing a device.

(2) 技術の背景 近年、LSI技術は著しく発展している。これは例えば
微細加工技術の進歩と共にゲート当りの占有面積の少な
い、工程が簡単なMO3型半導体装置がLSI化に適し
ておりこの発展に大きな貢献をなしている。
(2) Background of the technology In recent years, LSI technology has developed significantly. For example, along with advances in microfabrication technology, MO3 type semiconductor devices, which occupy a small area per gate and are easy to process, are suitable for LSI integration and have made a major contribution to this development.

係るMO3型半導体装置の高密度化に際して例えばその
寸法がホトレジスト工程に用いる露光光源の波長に近づ
くにつれ光よりも短い波長を有する電子ビーム或いはX
線等による集積回路のパターン形成及び転写の方式が種
々開発されている。
When increasing the density of such MO3 type semiconductor devices, for example, as the dimensions approach the wavelength of the exposure light source used in the photoresist process, electron beams or X
Various methods for forming and transferring patterns of integrated circuits using lines and the like have been developed.

このため加工技術にも各種微細化技術の開発要請がおき
ている。
For this reason, there is a demand for the development of various miniaturization technologies in processing technology.

(3) 従来技術と問題点 半導体基板上に絶縁層を形成してこの絶縁層にコンタク
トホールをあけ、表面にアルミニウム配線を行う際に、
コンタクトホールの近傍におけるアルミニウム配線の段
部におけるステップカバレッジを改善し、微細化加工技
術を進展させるために、レーザーアニールの適用が考え
られている。
(3) Prior art and problems When forming an insulating layer on a semiconductor substrate, making contact holes in this insulating layer, and wiring aluminum wiring on the surface,
The application of laser annealing is being considered in order to improve the step coverage in the stepped portion of the aluminum wiring near the contact hole and to advance miniaturization technology.

係るレーザーアニールは、アルミニウムへ直接レーザ照
射しても吸収率が低いため、アルミニウム配線のバクー
ニングが終了した後で、表面全体にPSG (リンシリ
ケートガラス)等の絶縁膜を形成しこのPSGの表面か
らレーザを照射し、アルミニウム配線層を若干溶解させ
コンタクトホール近傍においてアルミニウム配線の段部
を緩かにすることによりステンプカバレソジを向上させ
るものである。
In such laser annealing, since the absorption rate is low even if the laser is irradiated directly onto aluminum, after the vacuuming of the aluminum wiring is completed, an insulating film such as PSG (phosphosilicate glass) is formed on the entire surface of the aluminum wiring. The stencil coverage method is improved by irradiating a laser to slightly melt the aluminum wiring layer and making the stepped portion of the aluminum wiring loose in the vicinity of the contact hole.

しかしながら、従来のレーザ照射は、全面に形成された
PSG層の上からなされるために、アルミニウム配線層
以外の部分も加熱し、これによって半導体基板に形成さ
れた半導体素子の例えば拡散深さなどに影響を与えてし
まい、半導体素子の特性を劣化させてしまうという欠点
があった。
However, since conventional laser irradiation is performed from above the PSG layer formed on the entire surface, parts other than the aluminum wiring layer are also heated, which causes damage to the diffusion depth, etc. of the semiconductor element formed on the semiconductor substrate. This has the disadvantage that it affects the semiconductor device and deteriorates the characteristics of the semiconductor element.

また、レーザアニールによる加熱が半導体素子に影響を
及ぼさないようにするため、全面に形成される絶縁膜を
予め厚く形成すると、半導体装置の微細化には適さなく
なってしまう。
Furthermore, if the insulating film formed over the entire surface is formed thick in advance in order to prevent heating by laser annealing from affecting the semiconductor element, it will not be suitable for miniaturization of semiconductor devices.

4、 発明の目的 本発明の目的は上記従来の欠点に鑑み全面にA文等の金
属配線層を形成した状態でその上の絶縁膜を所要の金属
配線のパターンに形成して、上方からレーザアニールす
ることによって、絶縁膜により形成された配線パターン
部分のみ選択的に加熱処理を行ない半導体素子の特性を
劣化させることなく段部でのカバーレンジの改善を行う
半導体装置の製造方法を提供することにある。
4. Purpose of the Invention In view of the above-mentioned conventional drawbacks, the purpose of the present invention is to form a metal wiring layer such as pattern A on the entire surface, form an insulating film thereon in a desired metal wiring pattern, and then irradiate it with a laser beam from above. To provide a method for manufacturing a semiconductor device, which selectively heats only a wiring pattern portion formed of an insulating film by annealing, and improves the coverage range at a stepped portion without deteriorating the characteristics of a semiconductor element. It is in.

(5) 発明の構成 そして、この目的は本発明によれば段部を有する半導体
基板表面上に配線金属層を形成し、前記金属層の上に絶
縁膜パターンを形成し、その後に、レーザ照射して前記
金属層のステップカバーレンジを改善することを特徴と
する半導体装置の製造方法を提供することによって達成
される。
(5) Structure of the Invention According to the present invention, the purpose is to form a wiring metal layer on the surface of a semiconductor substrate having a step, form an insulating film pattern on the metal layer, and then perform laser irradiation. This is achieved by providing a method for manufacturing a semiconductor device, characterized in that the step coverage range of the metal layer is improved.

(6) 発明の実施例 次に、本発明の一実施例について図面を参照しながら説
明する。
(6) Embodiment of the Invention Next, an embodiment of the present invention will be described with reference to the drawings.

第1図(al乃至(C1は、本発明の製造工程を示す概
′略的断面図である。
FIG. 1 (al to (C1) are schematic sectional views showing the manufacturing process of the present invention.

シリコン基板1上に所定のパターニングにてコンタクト
ホール2を有する絶縁層例えばS i O2層3を略1
1!m厚形成し、更にA7+配線を行うためA72層4
を全面に亘り略1μm厚形成するとA1層4はコンタク
トホール2の近傍に段部5を有する。(同図(a))次
に、/1層3に絶縁膜6例えばPSG膜若しくはSiO
2等を2000人程度0厚さに被着し、形成すべき所定
のアルミニウム配線パターンと同一パターンを有するよ
うにパターニングする。(同図(b)) 更に、例えばCO2レーザにより全面に亘って走査を行
い、すなわちレーザアニールの熱処理を行う。(同図(
C))尚、第1図(a)〜(C)において、シリコン基
板1に形成される半導体素子は図示を省略しである。レ
ーザ光線照射時は、パターニングされた絶縁膜6を介し
てのみA4層4が昇温され、従って/1層4の段部5も
加熱され、若干溶解するのでそのステップカバーレッジ
は第1図(C)に示すように改善されてくる。また、例
えば段部以外の部分のように絶縁膜6のパターンが形成
されてない領域では、A1層4がむき出しの状態で残っ
ているためレーザ照射を受けても全面的に反射されて、
シリコン基板1に形成された半導体素子を加熱しない。
An insulating layer, such as a SiO2 layer 3, having a contact hole 2 is formed on a silicon substrate 1 by predetermined patterning.
1! m thickness and further A72 layer 4 to perform A7+ wiring.
When formed to a thickness of approximately 1 μm over the entire surface, the A1 layer 4 has a stepped portion 5 near the contact hole 2. ((a) in the same figure) Next, an insulating film 6 such as a PSG film or SiO
2,000 layers are deposited to a zero thickness and patterned to have the same pattern as a predetermined aluminum wiring pattern to be formed. ((b) in the same figure) Furthermore, scanning is performed over the entire surface using, for example, a CO2 laser, that is, a heat treatment of laser annealing is performed. (Same figure (
C)) Note that in FIGS. 1A to 1C, the semiconductor elements formed on the silicon substrate 1 are not shown. During laser beam irradiation, the temperature of the A4 layer 4 is increased only through the patterned insulating film 6, and the step portion 5 of the /1 layer 4 is also heated and slightly melted, so that the step coverage is as shown in Figure 1 ( This will be improved as shown in C). Furthermore, in areas where the pattern of the insulating film 6 is not formed, such as areas other than the stepped portions, the A1 layer 4 remains exposed, so even if the laser is irradiated, it will be reflected entirely.
The semiconductor element formed on the silicon substrate 1 is not heated.

次に、AN層4を三塩化硼素(BCC20等を用いて絶
縁膜6をマスクとし選択的にドライエツチングして、ア
ルミニウム配線パターンだけを残す。そして、表面全面
に保護用のカバーPSGを形成する。
Next, the AN layer 4 is selectively dry-etched using boron trichloride (BCC20, etc.) using the insulating film 6 as a mask, leaving only the aluminum wiring pattern. Then, a protective cover PSG is formed over the entire surface. .

(7) 発明の効果 以上述べて来たように、本発明を用いればAN層を全面
に亘って形成して所定の領域にのみ絶縁膜を設けてレー
ザアニール等の熱処理を行うため、熱が基板に達するこ
とが少なく従って半導体素子の拡散深さ等に与えるダメ
ージが阻止できる効果を有する。
(7) Effects of the Invention As described above, if the present invention is used, the AN layer is formed over the entire surface and the insulating film is provided only in a predetermined area and heat treatment such as laser annealing is performed, so that the heat This has the effect of preventing damage to the diffusion depth, etc. of the semiconductor element because it is less likely to reach the substrate.

また、本発明を用いると、A4層と絶縁膜とのエツチン
グ選択性が大なるため、絶縁膜及び絶縁膜をパターニン
グするレジストが薄くてすみ微細化に適した効果を有す
る。
Further, when the present invention is used, the etching selectivity between the A4 layer and the insulating film is increased, so that the insulating film and the resist for patterning the insulating film can be made thinner, which is suitable for miniaturization.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明を用いた半導体装置の製造方法を説明
する概略的工程断面図である。 1・・・シリコン基板   2・・・コンタクトホール
   3・・・絶縁膜    4・・・アルミニウム層
   5・・・段部   6・・・絶縁膜 特許出願人  富士通株式会社
FIG. 1 is a schematic process cross-sectional view illustrating a method of manufacturing a semiconductor device using the present invention. 1... Silicon substrate 2... Contact hole 3... Insulating film 4... Aluminum layer 5... Step portion 6... Insulating film patent applicant Fujitsu Limited

Claims (1)

【特許請求の範囲】[Claims] (1)段部を有する半導体基板表面上に配線金属層を形
成し、前記金属層の上に絶縁膜パターンを形成し、その
後に、レーザ照射して前記金属層のステップカバーレッ
ジを改善することを特徴とする半導体装置の製造方法。
(1) Forming a wiring metal layer on the surface of a semiconductor substrate having a step, forming an insulating film pattern on the metal layer, and then irradiating the metal layer with a laser to improve step coverage of the metal layer. A method for manufacturing a semiconductor device, characterized by:
JP22871682A 1982-12-28 1982-12-28 Manufacture of semiconductor device Granted JPS59121923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22871682A JPS59121923A (en) 1982-12-28 1982-12-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22871682A JPS59121923A (en) 1982-12-28 1982-12-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59121923A true JPS59121923A (en) 1984-07-14
JPH0410217B2 JPH0410217B2 (en) 1992-02-24

Family

ID=16880690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22871682A Granted JPS59121923A (en) 1982-12-28 1982-12-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59121923A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6236846A (en) * 1985-06-24 1987-02-17 アメリカ合衆国 Flattening of metal layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797647A (en) * 1980-12-10 1982-06-17 Toshiba Corp Forming of electrode wiring in semiconductor device
JPS57210624A (en) * 1981-02-09 1982-12-24 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797647A (en) * 1980-12-10 1982-06-17 Toshiba Corp Forming of electrode wiring in semiconductor device
JPS57210624A (en) * 1981-02-09 1982-12-24 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6236846A (en) * 1985-06-24 1987-02-17 アメリカ合衆国 Flattening of metal layer

Also Published As

Publication number Publication date
JPH0410217B2 (en) 1992-02-24

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