JPS5919364A - Manufacture of semiconductor device and lead frame using in manufacture thereof - Google Patents

Manufacture of semiconductor device and lead frame using in manufacture thereof

Info

Publication number
JPS5919364A
JPS5919364A JP57127546A JP12754682A JPS5919364A JP S5919364 A JPS5919364 A JP S5919364A JP 57127546 A JP57127546 A JP 57127546A JP 12754682 A JP12754682 A JP 12754682A JP S5919364 A JPS5919364 A JP S5919364A
Authority
JP
Japan
Prior art keywords
lead
layer
solder
lead frame
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57127546A
Other languages
Japanese (ja)
Inventor
Usuke Enomoto
榎本　宇佑
Kazuo Hatori
羽鳥　和夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57127546A priority Critical patent/JPS5919364A/en
Publication of JPS5919364A publication Critical patent/JPS5919364A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce the number of steps of and the cost of a semiconductor device by forming a solder layer which has a lower layer of lead and an upper layer of tin on the surface of the lead part which is projected from a resin package of a lead frame before mounting an element. CONSTITUTION:A silver plating film 6 is covered on an element mount 4 of a lead frame having a lead 1, a frame piece 2, a dam piece 3, and a wire connecting part 5, and a solder forming layer which has a lower layer 7 of lead and an upper layer 8 of tin is formed on the lead part from the piece 3 to the piece 2. Then, an element 10 is secured to the mount 4, and the electrode of the element 10 and the end of the lead 1 at both sides are connected by wirings 11. Subsequently, a resin package is covered on the part disposed with the mount 4, the connecting part 5, the element 10 and the wirings 11, and the pieces 3, 2 are cut and removed.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法およびその方法において
用いるリードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device and a lead frame used in the method.

レジンパッケージ型半導体装置は、素子取付部およびリ
ード等を有する金属製のリードフレームを用意した後、
素子取付部に素子を固定するとともに、素子の電極とリ
ードの内端とをワイヤで接続し、かつリードの内端と素
子部分等をレジンパッケージで被い、さらに不要リード
フレーム部分を切断除去した後レジンパッケージから突
出するリード表面を半田ディツプあるいは半田めっき処
理して半田で被うことによって製造している。Resin-packaged semiconductor devices are manufactured by preparing a metal lead frame with an element mounting portion and leads, etc.
In addition to fixing the device to the device mounting part, we connected the electrodes of the device and the inner ends of the leads with wires, covered the inner ends of the leads and the element, etc. with a resin package, and then cut and removed the unnecessary lead frame parts. It is manufactured by subjecting the lead surface protruding from the resin package to solder dipping or solder plating and covering it with solder.

しかし、この方法ではリードの半田被着は完成品状態で
行うことから、取り扱い難いことと、レジンパッケージ
部が大きいことから処理量も少なく、工数が多く掛り、
生産コストが高くなる欠点がある。However, with this method, the soldering of the leads is done in the finished product, which makes it difficult to handle, and because the resin package is large, the amount of processing is small and the number of man-hours is large.
The disadvantage is that production costs are high.

したがって、本発明の目的は工数の低い半導体装置の製
造方法を提供することにある。Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device with a low number of man-hours.

このような目的を達成するために本発明は、素子取付面
を銀めっき処理したリードフレームを用意した後、素子
取付、ワイヤ接続、レジンパッケージング、不要リード
切断除去を順次行なって半導体装置を製造するに際して
、素子取付前のリードフレームのレジンパッケージから
突出するリード部分の表面に、下層が鉛層、上層が錫層
からなる半田構成層または半田層をめっき処理にて形成
しておくものである。In order to achieve such an object, the present invention prepares a lead frame whose element mounting surface is silver-plated, and then sequentially performs element mounting, wire connection, resin packaging, and cutting and removal of unnecessary leads to manufacture a semiconductor device. In this process, a solder component layer or a solder layer consisting of a lead layer as a lower layer and a tin layer as an upper layer is formed by plating on the surface of the lead portion of the lead frame that protrudes from the resin package before the element is mounted. .

以下、実施例によυ本発明を説明する。The present invention will be explained below with reference to Examples.

第１図は本発明の一実施例によるリードフレームの平面
図、第２図は第１図の１−１線に沿う断面図である。FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line 1--1 in FIG.

この実施例のリードフレームは、銅系の金属板を打ち抜
いてパターン化し、３本のリード１と。The lead frame of this example is made by punching out a copper-based metal plate and patterning it into three leads 1.

リード１の一端をそれぞれ連結する枠片２と、リード１
の途中をそれぞれ連結するダム片３と、がらなっている
。リードｌの他端は幅広となシ、中央のリード１は素子
取付部４を、両側のリード１はワイヤ接続部５をそれぞ
れ形作っている。また、素子取付部４およびワイヤ接続
部５は第１図のクロスハツチングで示すように、１０μ
ｍ前後の厚さの銀めっき膜６で被われている。また、ダ
ム片３から枠片２に亘るリード部分には第１図のハツチ
ング領域で示すように２層の半田構成層が形成されてい
る。下層の半田構成層は鉛層７となシ、上層の半田構成
層は錫層８となっていて、その厚さは０．２μｍ〜１０
μｍ前後となシ、融点が２００Ｃ以上となるような組成
比となっている。融点を２００Ｃ以上にすることは、半
導体装置（この場合はトランジスタ）の製造におけるレ
ジンモールド時の１０００程度の処理温度にあっても溶
融しないようにするためである。また鉛と錫の２層構造
は電解メッキ時の層形成時半田の組成比精度の維持が容
易となる。また、酸化され易い鉛は下層とし、酸化され
難い錫層で鉛層を被っている。なお、図中９はガイド孔
である。A frame piece 2 that connects one end of the lead 1 to each other, and a lead 1
A dam piece 3 connects each midway between the parts. The other end of the lead 1 is wide, and the center lead 1 forms an element mounting part 4, and the leads 1 on both sides form a wire connection part 5. In addition, the element mounting part 4 and the wire connection part 5 are 10 μm thick, as shown by cross hatching in FIG.
It is covered with a silver plating film 6 having a thickness of about m. Further, in the lead portion extending from the dam piece 3 to the frame piece 2, two solder constituent layers are formed as shown by the hatched area in FIG. The lower solder component layer is a lead layer 7, and the upper solder component layer is a tin layer 8, the thickness of which is 0.2 μm to 10 μm.
The composition ratio is such that the melting point is about 200C or higher. The purpose of setting the melting point to 200C or higher is to prevent melting even at processing temperatures of about 1000C during resin molding in the manufacture of semiconductor devices (transistors in this case). Furthermore, the two-layer structure of lead and tin makes it easy to maintain the accuracy of the composition ratio of the layer-forming solder during electrolytic plating. Further, lead, which is easily oxidized, is placed in the lower layer, and the lead layer is covered with a tin layer, which is not easily oxidized. Note that 9 in the figure is a guide hole.

そこで、このようなリードフレームを用いてトランジス
タを製造するには、第３図で示すように、中央のリード
１の先端の素子取付部４上に半田箔あるいは半田ペース
トを用いて加熱溶融によって素子（半導体ペレット）１
０を固定する。つぎに、この素子１０の電極（エミッタ
電極、ペース電極；図示せず。）と両側のリード１の先
端とをワイヤ１１で接続する。つぎに、ダム片３よりも
外側の領域、すなわち素子取付部４．ワイヤ接続部５゜
素子１０．ワイヤ１１が位置する領域をレジンモールド
によって形成するレジンパッケージ１２で被うとともに
、不要なダム片３および枠片２を切断除去して第４図で
示すような３本リードのトランジスタ１３を製造する。Therefore, in order to manufacture a transistor using such a lead frame, as shown in FIG. (semiconductor pellet) 1
Fix 0. Next, the electrodes (emitter electrode, pace electrode; not shown) of this element 10 and the tips of the leads 1 on both sides are connected with wires 11. Next, the area outside the dam piece 3, that is, the element mounting portion 4. Wire connection 5° element 10. A three-lead transistor 13 as shown in FIG. 4 is manufactured by covering the region where the wire 11 is located with a resin package 12 formed by resin molding, and cutting and removing unnecessary dam pieces 3 and frame pieces 2. .

このような実施例では、板状のリードフレームの状態で
リード部分への半田構成層の形成を行なうため、レジン
モールドが完了した状態での大きなレジンパッケージを
有する状態でのリード部分への半田めっきに比較して、
作業性がよいとともに、処理効率も高くなる。特に、リ
ードフレームが７−プ状であれば、リード部分への半田
構成層の形成は連続的に行なえ、よシ生産コストの低減
化が図れる。また、リード部分への半田構成層の形成は
、従来性なっている銀めっき装置と同様の装置で行なえ
る。In such an embodiment, since the solder component layer is formed on the lead portion in the state of a plate-shaped lead frame, the solder plating on the lead portion is performed while the resin mold is completed and the large resin package is present. compared to
Not only is the workability good, but the processing efficiency is also high. Particularly, if the lead frame has a 7-ply shape, the solder constituent layer can be continuously formed on the lead portions, and production costs can be reduced. Further, the formation of the solder constituent layer on the lead portion can be performed using an apparatus similar to a conventional silver plating apparatus.

なお１本発明は前記実施例に限定されない。たとえば、
リード部分へは直接半田層を電解めっきで被着させても
よい。この場合も、レジンモールド時に支障を来たさな
いような融点となるように。Note that the present invention is not limited to the above embodiments. for example,
A solder layer may be applied directly to the lead portion by electrolytic plating. In this case as well, the melting point should be such that it does not cause problems during resin molding.

半田の鉛と錫の組成を選択する必要がある。It is necessary to select the lead and tin composition of the solder.

以上のように、本発明によれば工数の低い半導体装置の
製造方法を提供することができるため、半導体装置の製
造コストの低減が図れる。As described above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device with a low number of man-hours, so that the manufacturing cost of the semiconductor device can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

Claims (1)

【特許請求の範囲】 １、素子取付面を銀めっき処理したリードフレームを用
意する工程と、前記素子取付面に素子を半田で固定する
工程と、前記素子の電極とリードフレームのリードの内
端とをワイヤで接続する工程と、前記リード内端を含む
素子部分をレジンでパッケージする工程と、不要リード
フレーム部分を切断除去する工程と、を有する半導体装
置の製造方法において、前記素子取付工程前にリードフ
レームのパッケージの外に突出するリード領域の表面に
下層が鉛層、上層が錫層からなる半田構成層または半田
層をめっき処理にて形成しておくことを特命とする半導
体装置の製造方法。 ２、前記リードの半田構成層または半田層は融点が２０
０Ｃ以上となるような組成となっていることを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。 ３、素子取付部およびリードを有するリードフレームニ
オイて、前記リードのレジンパッケージカら外れる部分
の表面を下層が鉛層、上層が錫層からなる半田構成層あ
るいは半田層で被っておくことを特徴とするリードフレ
ーム。 ４、前記リードの半田構成層または半田層は融点が２０
０Ｃ以上となるような組成となっていることを特徴とす
る特許請求の範囲第３項記載のリードフレーム。[Claims] 1. A step of preparing a lead frame whose element mounting surface is silver-plated, a step of fixing the element to the element mounting surface with solder, and an electrode of the element and the inner end of the lead of the lead frame. In the method for manufacturing a semiconductor device, the method includes the steps of: connecting the leads with a wire; packaging the element portion including the inner end of the lead with resin; and cutting and removing the unnecessary lead frame portion, before the element mounting step. Manufacture of semiconductor devices in which a solder component layer or a solder layer consisting of a lead layer as a lower layer and a tin layer as an upper layer is formed by plating on the surface of the lead area that protrudes outside the package of the lead frame. Method. 2. The solder component layer or solder layer of the lead has a melting point of 20
2. The method of manufacturing a semiconductor device according to claim 1, wherein the composition is such that the temperature is 0C or higher. 3. A lead frame having an element mounting part and a lead, characterized in that the surface of the part of the lead that comes off from the resin package is covered with a solder composition layer or a solder layer consisting of a lead layer as a lower layer and a tin layer as an upper layer. lead frame. 4. The solder component layer or solder layer of the lead has a melting point of 20
The lead frame according to claim 3, characterized in that the lead frame has a composition such that the lead frame has a temperature of 0C or more.
JP57127546A 1982-07-23 1982-07-23 Manufacture of semiconductor device and lead frame using in manufacture thereof Pending JPS5919364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57127546A JPS5919364A (en) 1982-07-23 1982-07-23 Manufacture of semiconductor device and lead frame using in manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57127546A JPS5919364A (en) 1982-07-23 1982-07-23 Manufacture of semiconductor device and lead frame using in manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5919364A true JPS5919364A (en) 1984-01-31

Family

ID=14962677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57127546A Pending JPS5919364A (en) 1982-07-23 1982-07-23 Manufacture of semiconductor device and lead frame using in manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5919364A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5288667A (en) * 1990-08-23 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a molded semiconductor package having a lead frame and an connecting coupler

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5288667A (en) * 1990-08-23 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a molded semiconductor package having a lead frame and an connecting coupler

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