JPS5919335A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5919335A JPS5919335A JP12978182A JP12978182A JPS5919335A JP S5919335 A JPS5919335 A JP S5919335A JP 12978182 A JP12978182 A JP 12978182A JP 12978182 A JP12978182 A JP 12978182A JP S5919335 A JPS5919335 A JP S5919335A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thickness
- deposited
- semiconductor device
- semiconductor chip
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に係り、特に半導体チップを配設台
に取着するのに好適な構造の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure suitable for mounting a semiconductor chip on a mounting table.
電気的機能を有する半導体チップをリードフレームやス
テムなとの配設台に取着する方法は、従来たとえば特開
昭５５−１９８０５号に記載されたものがある。すなわ
ち、第１図に示すように、ｐ−１接合などを形成した半
導体チップ１の配設台取着面にパナノウム（至）層２を
形成し、この７層２上にニッケル（Ｎｌ ）層３を形成
し、このＮ１層３上に金、ダルマニウムを主成分とする
ＡｕＧｅＳｂ層４を形成し、このＡｕＧｅ８ｂ １ｍ
４上にＡｌ１層５をそれぞれ蒸着にょ多形成する。この
ような積層構造のＡｕＧｅＳｂ ／ｉ＠ ４をろう材と
して配役台６にマウントしていた。なお、上記積層構造
としてチタニウム（ＴＩ）−銅（Ｃｕ）−ＡｕＧｅＳｂ
−Ａｕのものもある。A conventional method for attaching a semiconductor chip having electrical functions to a mounting base such as a lead frame or a stem is described in, for example, Japanese Unexamined Patent Publication No. 19805/1983. That is, as shown in FIG. 1, a pananoum layer 2 is formed on the mounting surface of a semiconductor chip 1 on which a p-1 junction or the like is formed, and a nickel (Nl) layer is formed on this seven layer 2. 3, and on this N1 layer 3, an AuGeSb layer 4 containing gold and dalmanium as main components is formed.
A layer of Al1 5 is formed on each layer 4 by vapor deposition. AuGeSb/i@4 having such a laminated structure was mounted on the casting table 6 as a brazing material. Note that the above laminated structure is titanium (TI)-copper (Cu)-AuGeSb.
-There are also Au ones.
上記のようにマウントした半導体素子を樹脂封止したＮ
ＰＮ ）ランソスタには次のような欠点がある。前者っ
まｐ Ｖ−Ｎｌ−ＡｕＧｅＳｂ−Ａｕの積層構造では、
ＶＣＫ （ｓａｔ）などの電気特性は満足するが、プレ
ッシャークツカーテスト（ＰＣＴ ）を３００時間時間
性うとＮ１層が腐食される場合がある。また、後者つま
Ｊ） Ｔｉ−Ｃｕ−ＡｕＧｅ５ｂ−Ａｕの積層構造では
、ＡｕＧｅをろう材としてマウントした場合、ＰＣＴで
の電極腐食は問題ないが、Ｔ Ｉ −Ｃｕ層が厚いとＶ
。Ｅ（＋＋ａｔ）などの電気的特性が満足せず悪く、さ
らにＴｉ−Ｃｕ層が薄いとＣｕ層がＡｕＧｅと合金化し
、更に著しい場合にはＡｕＧｅ８１ＣｕあるいはＡｕＧ
ｅ５ｉＣｕＴｉの合金層が形成され、熱衝激試験でチッ
プクラックを生じることがあるなどの問題があった。N with resin-sealed semiconductor element mounted as above
PN) Runsosta has the following drawbacks. In the former pV-Nl-AuGeSb-Au stacked structure,
Although the electrical characteristics such as VCK (sat) are satisfied, the N1 layer may be corroded if subjected to pressure tester test (PCT) for 300 hours. In addition, in the latter case J) In the Ti-Cu-AuGe5b-Au stacked structure, when AuGe is mounted as a brazing material, electrode corrosion in PCT is not a problem, but if the Ti-Cu layer is thick, V
. If the electrical properties such as E(++at) are unsatisfactory and poor, and if the Ti-Cu layer is thin, the Cu layer will alloy with AuGe, and in even more severe cases, AuGe81Cu or AuGe.
There was a problem that an alloy layer of e5iCuTi was formed, which could cause chip cracks in a thermal shock test.
本発明は上記事情に鑑みてなされたもので、その目的と
するところは、電気的特性を低下させることなく、ＰＣ
Ｔでの電極腐食および熱衝激試験でのチップクラックを
防止する半導体装置を提供することにある。The present invention has been made in view of the above circumstances, and its purpose is to
An object of the present invention is to provide a semiconductor device that prevents electrode corrosion at T and chip cracking during a thermal shock test.
〔発明の概要〕
本発明は、配設台にマウントされる半導体チップ間にチ
タニウム（Ｔｉ）層および金、ダルマニウム（Ａｕ Ｇ
ｅ）を主成分とする合金層の積層構造を設けた半導体装
置を構成することにより、ＰＣＴ試験に対して耐え、チ
ップクラックの発生を減少させたものである。[Summary of the Invention] The present invention provides a titanium (Ti) layer and a gold, dalmanium (AuG) layer between semiconductor chips mounted on a mounting table.
By configuring a semiconductor device with a laminated structure of alloy layers mainly composed of e), it can withstand PCT tests and reduce the occurrence of chip cracks.
以下、本発明の一実施例について図面を参照して説明す
る。なお、この実施例は、第２図（Ａ）に示すように配
役台、たとえばＶ−ドフレーム２１の半導体チップ取着
リード２２に半導体チップ２３をマウントし、この半導
体チップ２３の電極からワイヤ２４により、ｒｌンディ
／グする場合について説明する。第２図（Ｂ） （Ｃ）
において、−導電形半導体基板、まとえばｎ形シリコン
ウェハ３１の内表面にそれぞれ離散してｐ形不純物を注
入することにより、ｐ影領域３２を複数個島状に形成し
、この各島状のｐ・影領域３２内の一部にｎ形不純物を
注入することにより、ｎ影領域３３を形成し、多数のＮ
ＰＮ ）ランジスタ３４を構成する。このトランジスタ
３４のリードフレーム２１へのマウント側面上にＴｉ層
３５を厚さ約１ｏｏｏ１蒸着する。このＴｉ層３５上に
ＡｕＧｅを主成分とする層、たとえばＡｕＧａ （１２
ｗｔ％） 、ｓｂ （０，１ｗｔｌ ）の合金層３６を
厚さ約１．５μｍ蒸着し、この合金層３６上にＡｕ層３
７を厚さ約１０００１蒸着する（第２図Ｂ）。このよう
に処理したウニノ・を上面からダイヤモンドスクライブ
法によシ個々のチップに分割する。この分割により得ら
れた半導体チップ２３を第２図（４）に図示したように
リードフレームの取着リード２２にマウントする（第２
図Ｃ）。すなわち、ＡｕＧｅＳｂの合金層３６をろう材
として取着リード２２にマウントする。このようにして
得られたＮＰＮ ）ランジスタのＶｃＩｌ、（ｓａｔ）
特性は、従来のＶ−ＡｕＧａＳｂ−Ａｕの積層構造のＮ
ＰＮ ）ランジスタと何ら差がなく、ＰＣＴ試験５００
時間でも蒸着膜の腐食は一切起らなかった。このような
積層構造がＶｃ Ｉ、（ｓ ａ ｔ ）、腐食などの耐
湿性、チップクラックの減少などの作用効果を有する理
由は明らかではないが、次の様な理由によるものと思わ
れる。An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIG. 2(A), a semiconductor chip 23 is mounted on a semiconductor chip mounting lead 22 of a mounting stand, for example, a V-shaped frame 21, and a wire 24 is connected from an electrode of this semiconductor chip 23. The following describes the case where the rl index is executed. Figure 2 (B) (C)
In this step, p-type impurities are discretely implanted into the inner surface of a -conductivity type semiconductor substrate, for example, an n-type silicon wafer 31, to form a plurality of p-shadow regions 32 in the form of islands, and each island-like By implanting an n-type impurity into a part of the p-shade region 32, an n-shade region 33 is formed, and a large number of N
PN) constitutes the transistor 34. A Ti layer 35 is deposited to a thickness of approximately 1001 mm on the side surface of the transistor 34 mounted on the lead frame 21 . On this Ti layer 35, a layer containing AuGe as a main component, for example, AuGa (12
wt%), sb (0,1 wtl) is deposited to a thickness of approximately 1.5 μm, and an Au layer 3 is deposited on this alloy layer 36.
7 is deposited to a thickness of about 10,001 mm (FIG. 2B). The thus treated Unino® is divided into individual chips by the diamond scribing method from the upper surface. The semiconductor chip 23 obtained by this division is mounted on the mounting leads 22 of the lead frame as shown in FIG. 2 (4).
Figure C). That is, the AuGeSb alloy layer 36 is mounted on the attachment lead 22 as a brazing material. The thus obtained NPN ) transistor VcIl, (sat)
The characteristics are that of the conventional V-AuGaSb-Au stacked structure.
PN) No difference from transistor, PCT test 500
No corrosion of the deposited film occurred over time. The reason why such a laminated structure has such effects as Vc I, (s a t ), moisture resistance against corrosion, reduction of chip cracks, etc. is not clear, but it is believed to be due to the following reasons.
５−
（１）耐湿性について
従来のＶ−Ｎｉ−ＡｕＧｅＳｂ−Ａｕの積層構造のよう
にＮ１とＡｕＧｅＳｂとの中のＡｕが湿度の高い葬囲気
中で接すると局部電池が形成され、 Ｎｉ層が流電腐食
を起こしたものと推定される。これに対し、前述した従
来のＴｌ−Ｃｕ−ＡｕＧｅ５ｂ−Ａｕ積層構造とすると
、ＣｕあるいはＴ１とＡｕとの接触による電池作用は殆
ど起らず、ＣｕまたはＴＩが腐食されることはない。5- (1) Moisture resistance As in the conventional V-Ni-AuGeSb-Au stacked structure, when N1 and Au in AuGeSb come into contact with each other in a humid atmosphere, a local battery is formed, and the Ni layer It is presumed that galvanic corrosion occurred. On the other hand, in the conventional Tl-Cu-AuGe5b-Au laminated structure described above, almost no battery action occurs due to contact between Cu or T1 and Au, and Cu or TI is not corroded.
（２） ｖｃｇ（ｓａｔ）不良についてＴＩ−Ｃｕ−
ＡｕＧｅ８ｂ−Ａｕ積層構造の場合、ＮＰＮ ）ランジ
スタはＡｕＧｅＳｂ中のｓｂが８１ペレツト中に拡散し
、Ｖｃｌ（ｍａｔ）％性を満しているため、Ｔｌ−Ｃｕ
蒸着膜の厚さを同一にし、厚さも５０００Ｘ以下、厚く
ても１μｍ以下に押える必要がある。このようなＴｌ−
Ｃｕの膜厚にすれば、Ｖｏｗ（ｓａｔ）不良の発生は殆
ど押えることが可能となる。(2) About vcg (sat) failure TI-Cu-
In the case of the AuGe8b-Au stacked structure, the Tl-Cu
It is necessary to keep the thickness of the deposited film the same, and to keep the thickness to 5000X or less, and at most 1 μm or less. Such Tl-
If the film thickness is set to Cu, the occurrence of Vow (sat) defects can be almost suppressed.
（３） チップクラックについて
Ｔｉ−Ｃｕ層を１μｍ以下に押えた場合、ＡｕＧｅもＴ
１−Ｃｕ層を拡散し、ＡｕＧｅ５１合金ができる場合
６一
がある。ところが、とのＡｕＧｅＳｉ合金が形成される
と、熱衝激試験で非常にチップクラックを発生しやすく
なる。(3) Regarding chip cracks, when the Ti-Cu layer is suppressed to 1 μm or less, AuGe also
There is a case in which an AuGe51 alloy is produced by diffusing a 1-Cu layer. However, when an AuGeSi alloy is formed, chip cracks are very likely to occur in a thermal shock test.
これら３点の欠点を解決するために特にＮｉの使用をさ
け、さらにＡｕＧｅの特に拡散しゃすいＣｕの使用もさ
けた電極構造としたもので、この発明のＴＩ−ＡｕＧｅ
（Ｓｂ）−Ａｕの積層構造は、Ｔｉの膜厚をＡｕＧｅが
半導体チップたとえばシリコンへ拡散するのを防止する
厚さにし、ｓｂだけが半導体チップへ拡散可能なＴｉの
膜厚に設定することが望ましく、Ｔ１の膜厚は１０００
Ｘ乃至１μｍが最適である。また、ＡｕＧｅ（Ｓｂ）の
膜厚は、半導体チップをリードフレームにマウントする
ろう材として必要な厚さでよく、その厚さは１μｍもあ
れば充分である。とのＡｕＧｅ（Ｓｂ）はろう材として
用いるので、半導体チップ側にあらかじめ設けた上記実
施例と異なり、リードフレームに設けてもよい。なお、
前記実施例において、Ａｕ層３７はＡｕＧｅ（Ｓｂ）中
のＧｅやｓｂの酸化防止のための被膜であり、蒸着後１
週間以内にリードフレームにマウントする場合には全く
なくてもよい。In order to solve these three drawbacks, the electrode structure was designed to avoid the use of Ni, and also to avoid the use of Cu, which is particularly difficult to diffuse in AuGe.
In the (Sb)-Au stacked structure, the Ti film thickness can be set to a thickness that prevents AuGe from diffusing into the semiconductor chip, such as silicon, and the Ti film thickness can be set so that only sb can be diffused into the semiconductor chip. Desirably, the film thickness of T1 is 1000
X to 1 μm is optimal. Further, the thickness of the AuGe (Sb) film may be the thickness required as a brazing material for mounting a semiconductor chip on a lead frame, and a thickness of 1 μm is sufficient. Since AuGe (Sb) is used as a brazing material, it may be provided on the lead frame, unlike the above embodiment in which it is provided in advance on the semiconductor chip side. In addition,
In the above embodiment, the Au layer 37 is a coating for preventing oxidation of Ge and sb in AuGe(Sb), and after vapor deposition,
It may not be necessary at all if mounted on a lead frame within a week.
以上説明したように本発明によれば、電気的特性を劣下
させることなく、ＰＣＴでの電極腐食および熱衝激試験
でのチップクラックを防止できる半導体装置を提供でき
る。As described above, according to the present invention, it is possible to provide a semiconductor device that can prevent electrode corrosion in PCT and chip cracking in thermal shock testing without deteriorating electrical characteristics.
第１図（Ａ） （Ｂ）は従来の半導体装置の半導体チ。
７°全ろう材によりマウントする構造説明図、第２図は
本発明の一実施例を説明するための図で、仏）図は一部
切欠斜視図、■）図および（Ｃ）図は断面構造図である
。
２１・・・リードフレーム、２２・・・半導体テッゾ取
着リード、２３・・・半導体チップ、２４・・・ワイヤ
、３１・・・ｎ形シリコンウェハ、３２・・・ｐ影領域
、３３・・・ｎ影領域、３４・・・ＮＰＮ ）ランジス
タ、３５・・・Ｔ１層、３６− Ａｕ Ｇｅ（Ｓｂ）層
、３７・・）Ａｕ層。FIGS. 1A and 1B are semiconductor chips of a conventional semiconductor device. An explanatory diagram of a structure in which the entire 7° mounting is performed using a brazing material. Figure 2 is a diagram for explaining an embodiment of the present invention. Figure (F) is a partially cutaway perspective view, Figure (■) and Figure (C) are cross-sectional views. It is a structural diagram. 21... Lead frame, 22... Semiconductor Tezzo attachment lead, 23... Semiconductor chip, 24... Wire, 31... N-type silicon wafer, 32... P shadow region, 33...・n shadow area, 34...NPN) transistor, 35...T1 layer, 36-Au Ge (Sb) layer, 37...) Au layer.
Claims (4)
ウム層および金、ダルマニウムを主成分とする合金層の
積層構造を具備してなることを特徴とする半導体装置。(1) A semiconductor device comprising a laminated structure of a titanium layer and an alloy layer containing gold and dalmanium as main components between semiconductor chips mounted on a mounting table.
許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the alloy layer is an AuGeSb alloy layer.
μｍである特許請求の範囲第１項記載の半導体装置。(3) The thickness of the titanium layer is 100OX to 1
The semiconductor device according to claim 1, which has a diameter of μm.
上に酸化防止のための金属層を設けたものである特許請
求の範囲第１項記載の半導体装置。(4) The semiconductor device according to claim 1, wherein the alloy layer is a metal layer for preventing oxidation provided on an alloy layer containing AuGe as a main component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12978182A JPS5919335A (en) | 1982-07-26 | 1982-07-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12978182A JPS5919335A (en) | 1982-07-26 | 1982-07-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5919335A true JPS5919335A (en) | 1984-01-31 |
| JPH0328822B2 JPH0328822B2 (en) | 1991-04-22 |
Family
ID=15018059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12978182A Granted JPS5919335A (en) | 1982-07-26 | 1982-07-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5919335A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02138753A (en) * | 1988-11-18 | 1990-05-28 | Sanyo Electric Co Ltd | Semiconductor pellet and its assembly structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5519806A (en) * | 1978-07-28 | 1980-02-12 | Toshiba Corp | Semiconductor device |
-
1982
- 1982-07-26 JP JP12978182A patent/JPS5919335A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5519806A (en) * | 1978-07-28 | 1980-02-12 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02138753A (en) * | 1988-11-18 | 1990-05-28 | Sanyo Electric Co Ltd | Semiconductor pellet and its assembly structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0328822B2 (en) | 1991-04-22 |
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