JPS63234562A - Electrode of semiconductor device - Google Patents
Electrode of semiconductor deviceInfo
- Publication number
- JPS63234562A JPS63234562A JP6942387A JP6942387A JPS63234562A JP S63234562 A JPS63234562 A JP S63234562A JP 6942387 A JP6942387 A JP 6942387A JP 6942387 A JP6942387 A JP 6942387A JP S63234562 A JPS63234562 A JP S63234562A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- ohmic
- barrier layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000010931 gold Substances 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052737 gold Inorganic materials 0.000 claims abstract description 7
- 150000001875 compounds Chemical class 0.000 claims abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 2
- 229910052719 titanium Inorganic materials 0.000 claims 2
- 239000010936 titanium Substances 0.000 claims 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000011109 contamination Methods 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000001771 vacuum deposition Methods 0.000 description 3
- 229910017401 Au—Ge Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、III −V族化合物半導体で形成された
半導体装置の電極に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrode for a semiconductor device formed of a III-V group compound semiconductor.
(従来の技術〕
第2図は従来のIII −V族化合物半導体で形成され
た半導体装置、例えばGaAs、AJZGaAs等で形
成された半導体レーザ装置の電極の構成を示す断面図で
あり、図において、1はN型またはP型のGaAs基板
、2はこのGaAs基板1にオーミック接触するオーミ
ック層で、例えば金ゲルマニウム(Au−Ge)合金層
2 a %ニッケル(Ni)層2b、金(Au)層2c
などを積層して形成されている。(Prior Art) FIG. 2 is a cross-sectional view showing the structure of an electrode of a conventional semiconductor device made of a III-V compound semiconductor, for example, a semiconductor laser device made of GaAs, AJZGaAs, etc. In the figure, 1 is an N-type or P-type GaAs substrate, 2 is an ohmic layer in ohmic contact with this GaAs substrate 1, for example, a gold germanium (Au-Ge) alloy layer 2 a % nickel (Ni) layer 2 b, a gold (Au) layer 2c
It is formed by laminating layers.
なお、このオーミック層2の各金属層は、いずれも真空
蒸着法等により形成され、その後GaAs基板1とオー
ミック層2との接触界面における良好なオーミック特性
を得るために熱処理される。Note that each metal layer of this ohmic layer 2 is formed by a vacuum evaporation method or the like, and then heat-treated to obtain good ohmic characteristics at the contact interface between the GaAs substrate 1 and the ohmic layer 2.
また、オーミック層2の最上層であるAu層2Cの表面
には、アセンブリ時にAu線等がワイヤボンディングさ
れる。Furthermore, an Au wire or the like is wire-bonded to the surface of the Au layer 2C, which is the uppermost layer of the ohmic layer 2, during assembly.
(発明が解決しようとする問題点〕
従来の電極は以上のように構成されているが、前述のオ
ーミック特性を得るための熱処理の際に、GaAs基板
1中のGaが熱拡散によりオーミック層2中を浸透して
、Au層2Cの表面に集積・酸化して、ワイヤボンディ
ング時の接着強度を低下させるなどの問題点があった。(Problems to be Solved by the Invention) The conventional electrode is constructed as described above, but during the heat treatment to obtain the above-mentioned ohmic characteristics, Ga in the GaAs substrate 1 is thermally diffused into the ohmic layer 2. There were problems such as penetrating into the Au layer 2C, accumulating and oxidizing on the surface of the Au layer 2C, and reducing adhesive strength during wire bonding.
この発明は、上記のような問題点を解決するためになさ
れたもので、熱処理により電極表面を汚染するのを防止
して、ワイヤボンディング時の接着強度の高い半導体装
置の電極を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and the purpose is to prevent the electrode surface from being contaminated by heat treatment and to obtain an electrode for a semiconductor device that has high adhesive strength during wire bonding. shall be.
この発明に係る半導体装置の電極は、IH−V族化合物
半導体基板上にオーミック層を形成し、とのオーミック
層の上に、バリヤ層と金層を順次形成したものである。The electrode of the semiconductor device according to the present invention includes an ohmic layer formed on an IH-V group compound semiconductor substrate, and a barrier layer and a gold layer sequentially formed on the ohmic layer.
〔作用]
この発明においては、バリヤ層が熱処理によるGaの拡
散・浸透を阻止するので、III族原子による電極表面
の汚染を防止する。[Function] In the present invention, the barrier layer prevents diffusion and penetration of Ga due to heat treatment, thereby preventing contamination of the electrode surface by group III atoms.
第1図はこの発明の一実施例を示す断面図であり、1.
2は第2図のものと全く同一のものである。3は前記オ
ーミック層2上に真空蒸着法等によって形成されたバリ
ヤ層、4はこのバリヤ層3上に真空蒸着法等によって形
成される金層である。そして、バリヤ層3は順にTi層
3a、M。FIG. 1 is a sectional view showing an embodiment of the present invention.1.
2 is exactly the same as that shown in FIG. 3 is a barrier layer formed on the ohmic layer 2 by a vacuum evaporation method, and 4 is a gold layer formed on this barrier layer 3 by a vacuum evaporation method or the like. The barrier layer 3 includes Ti layers 3a and M in this order.
層3b、Ti層3cで構成される。It is composed of a layer 3b and a Ti layer 3c.
上記のように構成された半導体装置の電極においては、
高融点金属であり、Gaに対する拡散係数の充分小さな
MO層3bが熱処理時にGaAs基板1中から拡散して
くるGaを阻止し、Gaがさらに上の層へ拡散するのを
防ぐ。しかしMoはAuとの密着性が悪いため、MOと
Auのどちらも密着性が極めて良好なTi層3a、3c
をM。In the electrode of the semiconductor device configured as above,
The MO layer 3b, which is a high melting point metal and has a sufficiently small diffusion coefficient for Ga, blocks Ga from diffusing from within the GaAs substrate 1 during heat treatment, and prevents Ga from further diffusing into the upper layer. However, since Mo has poor adhesion to Au, the Ti layers 3a and 3c have extremely good adhesion to both MO and Au.
M.
層3bの上下に形成し、オーミック層2の最上層である
Au層2cと電極最表面のAu層4のそれぞれとMo層
3bの密着性を向上させている。They are formed above and below the layer 3b to improve the adhesion between the Mo layer 3b and each of the Au layer 2c, which is the uppermost layer of the ohmic layer 2, and the Au layer 4, which is the outermost surface of the electrode.
なお、上記実施例はGaAs基板の場合であるが、その
他のIII −V族半導体基板にもこの発明は適用でき
る。It should be noted that although the above embodiment is a case of a GaAs substrate, the present invention can also be applied to other III-V group semiconductor substrates.
この発明は以上説明したとおり、オーミック層上にバリ
ヤ層を形成することにより、熱処理時にIII族原子が
拡散して電極表面を汚染するのを防止し、ワイヤボンデ
ィング強度を高くできる効果がある。As explained above, this invention has the effect of preventing group III atoms from diffusing and contaminating the electrode surface during heat treatment by forming a barrier layer on the ohmic layer, thereby increasing wire bonding strength.
第1図はこの発明の一実施例を示す半導体装置の電極の
断面図、第2図は従来の半導体装置の電極を示す断面図
である。
図において、1はGaAs基板、2はオーミック層、2
aはAu−Ge合金層、2bはNi層、2cはAu層、
3はバリヤ層、3aはTi層、3bはMO層、3cはT
i層、4はAu層である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 (外2名)第1図
第2図FIG. 1 is a sectional view of an electrode of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a sectional view of an electrode of a conventional semiconductor device. In the figure, 1 is a GaAs substrate, 2 is an ohmic layer, and 2 is a GaAs substrate.
a is an Au-Ge alloy layer, 2b is a Ni layer, 2c is an Au layer,
3 is a barrier layer, 3a is a Ti layer, 3b is an MO layer, 3c is a T layer
The i layer and 4 are Au layers. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2
Claims (2)
、バリヤ層、および金層を順次形成したことを特徴とす
る半導体装置の電極。(1) An electrode for a semiconductor device, characterized in that an ohmic layer, a barrier layer, and a gold layer are sequentially formed on a III-V group compound semiconductor substrate.
を順次形成した積層構造からなることを特徴とする特許
請求の範囲第(1)項記載の半導体装置の電極。(2) An electrode for a semiconductor device according to claim (1), wherein the barrier layer has a laminated structure in which a titanium layer, a molybdenum layer, and a titanium layer are sequentially formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6942387A JPS63234562A (en) | 1987-03-23 | 1987-03-23 | Electrode of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6942387A JPS63234562A (en) | 1987-03-23 | 1987-03-23 | Electrode of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63234562A true JPS63234562A (en) | 1988-09-29 |
Family
ID=13402194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6942387A Pending JPS63234562A (en) | 1987-03-23 | 1987-03-23 | Electrode of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63234562A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5060050A (en) * | 1987-07-21 | 1991-10-22 | Hitachi, Ltd. | Semiconductor integrated circuit device |
US5294486A (en) * | 1990-10-22 | 1994-03-15 | International Business Machines Corporation | Barrier improvement in thin films |
US5412249A (en) * | 1993-03-31 | 1995-05-02 | Kabushiki Kaisha Toshiba | Semiconductor device having layered electrode |
-
1987
- 1987-03-23 JP JP6942387A patent/JPS63234562A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5060050A (en) * | 1987-07-21 | 1991-10-22 | Hitachi, Ltd. | Semiconductor integrated circuit device |
US5294486A (en) * | 1990-10-22 | 1994-03-15 | International Business Machines Corporation | Barrier improvement in thin films |
US5412249A (en) * | 1993-03-31 | 1995-05-02 | Kabushiki Kaisha Toshiba | Semiconductor device having layered electrode |
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