JPH0637301A - Semiconductor device and fabrication of the same - Google Patents
Semiconductor device and fabrication of the sameInfo
- Publication number
- JPH0637301A JPH0637301A JP21557992A JP21557992A JPH0637301A JP H0637301 A JPH0637301 A JP H0637301A JP 21557992 A JP21557992 A JP 21557992A JP 21557992 A JP21557992 A JP 21557992A JP H0637301 A JPH0637301 A JP H0637301A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- impurities
- gold
- substrate
- alloy layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010931 gold Substances 0.000 claims abstract description 72
- 239000012535 impurity Substances 0.000 claims abstract description 61
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 39
- 239000000956 alloy Substances 0.000 claims abstract description 39
- 229910052737 gold Inorganic materials 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910021484 silicon-nickel alloy Inorganic materials 0.000 abstract 2
- 239000010936 titanium Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 229910052715 tantalum Inorganic materials 0.000 description 9
- 229910052719 titanium Inorganic materials 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- -1 Ti and Ta Chemical class 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Die Bonding (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に関するものであり、特にオーミック特性にすぐ
れた裏面電極を有する半導体装置及びその製造方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a back electrode having excellent ohmic characteristics and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、半導体装置の裏面電極形成方法に
おいて、特公平３−２３５１号（特開昭６０−２０６１
３３号）公報、特開昭６１−３２５１５号公報及び特開
昭６１−２２０３４４号公報に開示された技術がある。
前記特公平３−２３５１号公報には、従来の技術として
シリコン（Ｓｉ）層、アンチモン（Ｓｂ）を含む金（Ａ
ｕ）層、ニッケル（Ｎｉ）層及び銀（Ａｇ）層を順次蒸
着した蒸着系が紹介されている。このような蒸着系によ
る製造方法を図７〜図１０に示す。なおこの場合前記Ａ
ｇ層の代わりにＡｕ層を使用した場合を図示している。
図７において、図示４はウェーハプロセスの終了したＮ
型Ｓｉ基板を示し、その裏面４２は研磨されている。な
お４１は表面素子領域である。図８は図７の続きを示す
断面図である。図８において前記裏面４２にＳｂを含む
Ａｕ層５１、Ｎｉ層５２及びＡｕ層５３を順次蒸着形成
している。図９は図８の続きを示す断面図である。図８
の状態で熱処理をすると、図９の状態となる。図９にお
いて、前記裏面４２からＳｉ基板４中にＳｂを含むＡｕ
及びＮｉが導入され、Ｓｂを含むＡｕとＳｉとの合金層
５４及びＳｂを含むＡｕとＳｉとＮｉとの合金層５５が
形成されている。また前記裏面４２にＳｂを含むＡｕと
Ｎｉとの合金層５６、Ｎｉ層５２、ＡｕとＮｉとの合金
層５７及びＡｕ層５３が積層形成されて裏面電極５とな
る。図１０では図９の状態にハンダ付けをして、ハンダ
とＮｉとＡｕとの合金層６が形成されている。2. Description of the Related Art Conventionally, in a method of forming a back surface electrode of a semiconductor device, Japanese Patent Publication No. 3-2351 (JP-A-60-2061).
33), JP-A-61-32515 and JP-A-61-220344.
In Japanese Patent Publication No. 3251/1993, the prior art discloses a silicon (Si) layer and gold (A) containing antimony (Sb).
An evaporation system in which a u) layer, a nickel (Ni) layer, and a silver (Ag) layer are sequentially evaporated is introduced. A manufacturing method using such a vapor deposition system is shown in FIGS. In this case, A
The case where an Au layer is used instead of the g layer is illustrated.
In FIG. 7, FIG. 4 shows N at the end of the wafer process.
A type Si substrate is shown, the back surface 42 of which is polished. Reference numeral 41 is a surface element region. FIG. 8 is a sectional view showing a continuation of FIG. In FIG. 8, an Au layer 51 containing Sb, a Ni layer 52, and an Au layer 53 are sequentially formed on the back surface 42 by vapor deposition. FIG. 9 is a sectional view showing a continuation of FIG. Figure 8
When the heat treatment is performed in this state, the state shown in FIG. 9 is obtained. In FIG. 9, Au containing Sb in the Si substrate 4 from the back surface 42
And Ni are introduced to form an alloy layer 54 of Au and Si containing Sb and an alloy layer 55 of Au, Si and Ni containing Sb. Further, an Au / Ni alloy layer 56 containing Sb, a Ni layer 52, an Au / Ni alloy layer 57, and an Au layer 53 are laminated on the back surface 42 to form the back electrode 5. In FIG. 10, the state of FIG. 9 is soldered to form an alloy layer 6 of solder, Ni, and Au.
【０００３】この蒸着系では、上述のようにＳｂを含む
ＡｕとＳｉとＮｉとの合金層５５が形成される。したが
ってＮｉとＳｉの合金は高抵抗であるため、裏面電極の
オーミック特性が悪化する。この欠点を解決するために
特公平３−２３５１号公報では、半導体基板と、この半
導体基板裏面に設けられたＡｕを主成分としＳｂを不純
物として含む第一の電極層と、この第一の電極層上に設
けられたタンタル（Ｔａ）を含む第二の電極層と、この
第二の電極層上に設けられたＮｉを含む第三の電極層と
を有する半導体装置が開示されている。この構造による
と後述するようにＮｉとＳｉがＴａで分離され、Ｎｉと
Ｓｉの合金化が防止される。またＳｉ基板の不純物濃度
が１０18／cm3 以下の場合、Ｓｉ基板の裏面に接触させ
るＡｕ層によって不純物を導入しなければ、良好なオー
ム接触は得られないことが知られている。この特公平３
−２３５１号公報においては、Ｎ型Ｓｉ基板の裏面にＳ
ｂを含むＡｕ層、Ｔａ層、Ｎｉ層、Ａｇ層を順次蒸着形
成した後、熱処理を行うことによりＳｉ基板中にＳｂを
導入する。ここではＡｕがＳｉと低い温度で共晶するこ
とを利用して、前記Ｓｂを含むＡｕ層によりＳｂを前記
Ｓｉ基板に導入している。前記Ｔａ層は、オーム性接触
を得るためにＳｉ層及びＡｕ（Ｓｂを含む）層を積層し
た系とハンダ層との接続に使用するＮｉ層及びＡｇ層を
積層した系を分離するバリア金属層である。また前記Ｔ
ａ層の上に形成されたＮｉ層はハンダとのなじみを向上
させる。さらにＮｉ層が酸化しやすく、酸化したＮｉ層
はハンダとのなじみが悪化するために、前記Ａｇ層は、
Ｎｉ層の酸化を防止している。また前記特開昭６１−３
２５１５号公報には、チタン（Ｔｉ）層を前記バリア金
属層として使用する半導体装置の製造方法が開示されて
いる。更に前記特開昭６１−２２０３４４号公報には、
Ｔｉ、モリブデン（Ｍｏ）、タングステン（Ｗ）もしく
はＴａの内の１つ又は２つ以上の組み合わされた金属層
を前記バリア金属層として使用することが開示されてい
る。In this vapor deposition system, the alloy layer 55 of Au, Si and Ni containing Sb is formed as described above. Therefore, since the alloy of Ni and Si has a high resistance, the ohmic characteristics of the back surface electrode are deteriorated. In order to solve this drawback, Japanese Patent Publication No. 3-2351 discloses that a semiconductor substrate, a first electrode layer provided on the back surface of the semiconductor substrate and containing Sb as an impurity as a main component, and the first electrode. A semiconductor device having a second electrode layer containing tantalum (Ta) provided on a layer and a third electrode layer containing Ni provided on the second electrode layer is disclosed. According to this structure, Ni and Si are separated by Ta as described later, and the alloying of Ni and Si is prevented. Further, it is known that when the impurity concentration of the Si substrate is 10 18 / cm 3 or less, good ohmic contact cannot be obtained unless impurities are introduced by the Au layer that contacts the back surface of the Si substrate. This special fair 3
In Japanese Patent No. 2351, S is formed on the back surface of an N-type Si substrate.
After the Au layer, the Ta layer, the Ni layer, and the Ag layer containing b are sequentially formed by vapor deposition, heat treatment is performed to introduce Sb into the Si substrate. Here, utilizing the fact that Au is eutectic with Si at a low temperature, Sb is introduced into the Si substrate by the Au layer containing Sb. The Ta layer is a barrier metal layer that separates a system in which a Si layer and an Au (including Sb) layer are laminated to obtain an ohmic contact from a system in which a Ni layer and an Ag layer used to connect the solder layer are separated. Is. Also, the T
The Ni layer formed on the a layer improves the compatibility with the solder. Further, since the Ni layer is easily oxidized, and the oxidized Ni layer is less compatible with solder, the Ag layer is
The Ni layer is prevented from being oxidized. Further, the above-mentioned JP-A-61-3
Japanese Patent No. 2515 discloses a method for manufacturing a semiconductor device using a titanium (Ti) layer as the barrier metal layer. Further, in the above-mentioned JP-A-61-220344,
The use of one or more combined metal layers of Ti, molybdenum (Mo), tungsten (W) or Ta as the barrier metal layer is disclosed.
【０００４】[0004]
【発明が解決しようとする課題】上述の従来技術では、
Ｓｂを含むＡｕ層、Ｔｉ、Ｔａ等のバリア金属層、Ｎｉ
層、Ａｇ（又はＡｕ）層を順次積層しているので、Ｔ
ｉ、Ｔａ等のバリア金属層が必要不可欠となる。しかし
Ｔｉ、Ｔａ等は高価であり、またＴｉ、Ｔａ等を使用す
ると、裏面電極の製造工程が煩雑になる。したがって本
発明の課題は、上述の欠点をなくし、Ｔｉ、Ｔａ等の高
価なバリア金属を使用しないで裏面電極の良好なオーム
接触が得られ、かつ裏面電極の接触抵抗を小さくするこ
とができ、更に製造工程が煩雑にならない半導体装置及
びその製造方法を提供することである。In the above-mentioned prior art,
Au layer containing Sb, barrier metal layer such as Ti and Ta, Ni
Since the layers and the Ag (or Au) layer are sequentially laminated, T
A barrier metal layer such as i or Ta is indispensable. However, Ti, Ta, etc. are expensive, and the use of Ti, Ta, etc. complicates the manufacturing process of the back electrode. Therefore, the object of the present invention is to eliminate the above-mentioned drawbacks, obtain good ohmic contact of the back electrode without using expensive barrier metals such as Ti and Ta, and reduce the contact resistance of the back electrode, It is another object of the present invention to provide a semiconductor device and a method of manufacturing the semiconductor device, the manufacturing process of which is not complicated.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するた
め、本発明の構成の第一のものは、不純物を含むシリコ
ン基板の裏面に金、前記不純物と同型の不純物及びシリ
コンを含む合金層、金のみもしくは金及び前記不純物と
同型の不純物を含む層、ニッケル層を順次積層形成した
半導体装置である。さらに本発明の構成の第二のもの
は、不純物を含むシリコン基板の裏面に、前記不純物と
同型の不純物を含む金層を形成した後に、熱処理して前
記不純物と同型の不純物を前記シリコン基板に導入する
とともに、前記シリコン基板の裏面に金、前記不純物と
同型の不純物及びシリコンを含む合金層を形成する第一
の工程と、この合金層の前記シリコン基板と反対側の面
に金のみもしくは金及び前記不純物と同型の不純物を含
む層を形成する第二の工程と、前記金のみもしくは金及
び前記不純物と同型の不純物を含む層の前記合金層と反
対側の面にニッケル層を形成する第三の工程とを含む半
導体装置の製造方法である。In order to solve the above-mentioned problems, a first aspect of the present invention is to provide an alloy layer containing gold, an impurity of the same type as said impurities and silicon on the back surface of a silicon substrate containing impurities. This is a semiconductor device in which only gold or a layer containing gold and an impurity of the same type as the above impurities, and a nickel layer are sequentially stacked. A second aspect of the present invention is that a gold layer containing impurities of the same type as the impurities is formed on the back surface of the silicon substrate containing impurities, and then heat-treated to form impurities of the same type on the silicon substrate. Along with the introduction, a first step of forming an alloy layer containing gold, impurities of the same type as the impurities and silicon on the back surface of the silicon substrate, and gold alone or gold on the surface of the alloy layer opposite to the silicon substrate. And a second step of forming a layer containing impurities of the same type as the impurities, and a step of forming a nickel layer on the surface of the layer containing only the gold or the layer containing impurities of the same type as the gold and the impurities opposite to the alloy layer. A method of manufacturing a semiconductor device, including the third step.
【０００６】[0006]
【作用】上記構成の半導体装置によると、不純物を含む
Ｓｉ基板の裏面にＡｕ、前記Ｓｉ基板に含まれる不純物
と同型の不純物及びＳｉを含む合金層が存在するので、
裏面電極とＳｉ基板とのオーミック特性が良好となる。
また金のみもしくは金及び前記不純物と同型の不純物を
含む層は前記合金層中のＳｉとＮｉ層中のＮｉとの合金
層の発生を防止する。さらにＮｉ層は、裏面電極とハン
ダとのなじみを良くする。また上記構成の半導体装置の
製造方法によると、Ｓｉ基板の裏面に前記合金層を形成
する第一の工程においてＳｉ基板に含まれる不純物と同
型の不純物が前記Ｓｉ基板中に導入されるので、前記Ｓ
ｉ基板中の不純物濃度を高くすることができるため、前
記Ｓｉ基板と裏面電極とのオーミック特性を良好にする
ことができる。また前記第一の工程の熱処理の後に金の
みもしくは金及び前記不純物と同型の不純物を含む層を
形成し、その後Ｎｉ層を形成しているので、熱処理後に
形成した金層がＳｉとＮｉの接触を防止し、ＳｉとＮｉ
の合金層の発生を防ぐことができる。According to the semiconductor device having the above structure, since the back surface of the Si substrate containing impurities is Au, and the alloy layer containing Si and the impurities of the same type as the impurities contained in the Si substrate are present.
The ohmic characteristics of the back surface electrode and the Si substrate are improved.
Further, the layer containing only gold or gold and impurities of the same type as the impurities prevents generation of an alloy layer of Si in the alloy layer and Ni in the Ni layer. Further, the Ni layer improves the compatibility between the back surface electrode and the solder. Further, according to the method for manufacturing a semiconductor device having the above structure, since impurities of the same type as those contained in the Si substrate are introduced into the Si substrate in the first step of forming the alloy layer on the back surface of the Si substrate, S
Since the impurity concentration in the i substrate can be increased, the ohmic characteristics of the Si substrate and the back electrode can be improved. In addition, after the heat treatment in the first step, a layer containing only gold or gold and an impurity of the same type as the above impurities is formed, and then a Ni layer is formed. Therefore, the gold layer formed after the heat treatment makes contact between Si and Ni. Prevent Si and Ni
It is possible to prevent the formation of the alloy layer.
【０００７】[0007]
【実施例】本発明の一実施例を図面を参照しながら説明
する。図１〜図５は本発明の一実施例の断面図である。
まず図１に示すように、ウェーハプロセスにおいて、不
純物Ｘを含むＳｉ基板１の表面素子領域１１を形成し
て、次にＳｉ基板１の研磨した裏面１２を形成する。そ
の後図２に示すように、この研磨した裏面１２に対しＳ
ｉ基板の不純物と同型の不純物Ｘを０．１〜５％含有し
たＡｕ層２１ａを１００〜２００ｎｍ蒸着する。次に図
３に示すように、真空中もしくは不活性ガス（例えばア
ルゴン、チッソ）中にて３００〜４００℃の熱処理を行
い、Ｓｉ基板１の前記裏面１２に、Ａｕと前記同型の不
純物ＸとＳｉを含む合金層２１を形成する。このとき前
記同型の不純物ＸがＳｉ基板１中に導入されるので、Ｓ
ｉ基板１中の不純物濃度を高めることができる。更に図
４に示すように、Ｓｉ基板１の温度を１００〜２００℃
まで冷却し、前記合金層２１上にＡｕ（Ｘを含むもの又
はＸを含まないもの）層２２を１００〜２００ｎｍ蒸着
し、その上にＮｉ層２３を２００〜８００ｎｍ蒸着し、
更にその上にＡｕ（Ｘを含むもの又はＸを含まないも
の）層２４を５０〜２００ｎｍ蒸着し、裏面電極２を形
成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. 1 to 5 are sectional views of an embodiment of the present invention.
First, as shown in FIG. 1, in a wafer process, a surface element region 11 of an Si substrate 1 containing an impurity X is formed, and then a polished back surface 12 of the Si substrate 1 is formed. Then, as shown in FIG. 2, S
An Au layer 21a containing 0.1 to 5% of an impurity X of the same type as that of the i substrate is vapor-deposited to a thickness of 100 to 200 nm. Next, as shown in FIG. 3, heat treatment is performed at 300 to 400 ° C. in a vacuum or in an inert gas (for example, argon, nitrogen), and the back surface 12 of the Si substrate 1 is subjected to Au and the impurity X of the same type. An alloy layer 21 containing Si is formed. At this time, since the impurity X of the same type is introduced into the Si substrate 1, S
The impurity concentration in the i substrate 1 can be increased. Further, as shown in FIG. 4, the temperature of the Si substrate 1 is 100 to 200 ° C.
Cooled to 100 nm to 200 nm of Au (containing X or not containing X) layer 22 on the alloy layer 21, and Ni layer 23 of 200 to 800 nm thereon.
Further, an Au (X-containing or X-free) layer 24 is vapor-deposited thereon with a thickness of 50 to 200 nm to form the back electrode 2.
【０００８】このようにして形成した裏面電極２の構造
は、第一層目にＡｕとＳｉ基板１の不純物と同型の不純
物ＸとＳｉを含む合金層２１、第二層目にＡｕ（Ｘを含
むもの又はＸを含まないもの）層２２、第三層目にＮｉ
層２３及び第四層目にＡｕ（Ｘを含むもの又はＸを含ま
ないもの）層２４で構成されている。なおＸは、Ａｕに
含まれるＰ型もしくはＮ型不純物であり、Ｓｉ基板１が
Ｎ型のときはＮ型の不純物例えばリン（Ｐ）、砒素（Ａ
ｓ）、Ｓｂ等であり、Ｐ型のときはＰ型の不純物例えば
ホウ素（Ｂ）、ガリウム（Ｇａ）、インジウム（Ｉｎ）
等となる。この場合、上述の従来例で存在していたＳｂ
を含むＡｕとＳｉとＮｉとの合金層５５及びＳｂを含む
ＡｕとＮｉとの合金層５６と同様のものは存在しない。
また前記Ａｕ（Ｘを含むもの又はＸを含まないもの）層
２２は、ＳｉとＮｉの合金層が生ずることを防ぐため
に、前記合金層２１とＮｉ層２３との間に形成されてい
る。更に前記Ａｕ（Ｘを含むもの又はＸを含まないも
の）層２４はＡｇ（Ｘを含むもの又はＸを含まないも
の）層で置き換えてもよい。図５は裏面電極２をハンダ
付けした後の状態の断面図である。図５において、３は
ハンダとＮｉとＡｕとの合金層である。ハンダ付け後も
図４と同様に上述の従来例で存在していたＳｂを含むＡ
ｕとＳｉとＮｉとの合金層５５及びＳｂを含むＡｕとＮ
ｉとの合金層５６と同様のものは存在しない。The structure of the back electrode 2 thus formed is such that the first layer is an alloy layer 21 containing Au and the impurities X and Si of the same type as the impurities of the Si substrate 1, and the second layer is Au (X. (Containing or not containing X) layer 22, Ni as the third layer
The layer 23 and the fourth layer are Au (those containing X or not X) layers 24. X is a P-type or N-type impurity contained in Au, and when the Si substrate 1 is N-type, N-type impurities such as phosphorus (P) and arsenic (A
s), Sb, etc., and when P type, P type impurities such as boron (B), gallium (Ga), indium (In)
And so on. In this case, Sb that was present in the above-mentioned conventional example
There is no similar one to the alloy layer 55 of Au, Si and Ni containing Si and the alloy layer 56 of Au and Ni containing Sb.
The Au (X-containing or X-free) layer 22 is formed between the alloy layer 21 and the Ni layer 23 in order to prevent the formation of an alloy layer of Si and Ni. Further, the Au (X-containing or X-free) layer 24 may be replaced with an Ag (X-containing or X-free) layer. FIG. 5 is a sectional view showing a state after the back surface electrode 2 is soldered. In FIG. 5, 3 is an alloy layer of solder, Ni, and Au. Even after soldering, as in FIG. 4, A including Sb, which was present in the above-described conventional example, is included.
An alloy layer 55 of u, Si and Ni and Au and N containing Sb
There is no similar alloy layer 56 with i.
【０００９】以上の構成により、裏面電極２の特長は次
のようになる。上記構成の半導体装置において、合金層
２１及びＡｕ層２２は、裏面電極２とＳｉ基板１とのオ
ーミック特性を良好にする。またＮｉ層２３は、裏面電
極２とハンダとのなじみを良くする。更にＡｕ層２４
は、Ｎｉ層２３の酸化を防いでいる。また前記合金層２
１形成の過程において、上述のようにＳｉ基板１中にＳ
ｉ基板１の不純物と同型の不純物Ｘが導入されるので、
Ｓｉ基板１の不純物濃度を高めてＳｉ基板１と裏面電極
２とのオーミック特性を良好にすることができる。さら
にＳｉ基板１の裏面１２に、このＳｉ基板１の不純物と
同型の不純物Ｘを含むＡｕ層２１ａ蒸着後上述のように
熱処理を行うことにより、前記合金層２１を形成し、そ
の後Ａｕ（Ｘを含むもの又はＸを含まないもの）層２
２、Ｎｉ層２３及びＡｕ（Ｘを含むもの又はＸを含まな
いもの）層２４を順次蒸着積層しているので、Ｎｉ層２
３のＮｉとＳｉ基板１のＳｉとの合金層が形成されるこ
とが防止される。したがって良好なオーミック特性を妨
げるＳｉとＮｉとの合金層の形成を防止できる。この場
合使用されるＳｉ基板１は、Ｎ型でもＰ型でもよい。ま
た上述のようにＡｕに含まれる不純物Ｘの選択範囲が広
い。図６は、上述の一実施例の裏面電極２の電圧Ｖ−電
流Ｉ特性を示す。図６において、前記各Ａｕ層のよう
に、Ｓｂを含むＡｕのときは良好なオーミック特性を示
している。一方Ｓｂを含まないＡｕのときは電圧Ｖ−電
流Ｉ特性が非線形である。また上述の一実施例の裏面電
極２は前記従来例の各公報に開示されたＳｂを含むＡｕ
層、Ｔｉ、Ｔａ、Ｗ、Ｍｏ等のバリア金属層、Ｎｉ層、
Ａｕ（又はＡｇ）層の金属系のうち前記Ｔｉ、Ｔａ、
Ｗ、Ｍｏ等のバリア金属層を省いても同様な効果及び信
頼性が得られるため、材料費と工程数の削減となる。な
お、上述の本発明の一実施例は、パワートランジスタ等
の半導体装置の裏面を電極とするものに応用できる。With the above structure, the features of the back electrode 2 are as follows. In the semiconductor device having the above structure, the alloy layer 21 and the Au layer 22 improve the ohmic characteristics of the back electrode 2 and the Si substrate 1. Further, the Ni layer 23 improves the compatibility between the back surface electrode 2 and the solder. Further, the Au layer 24
Protects the Ni layer 23 from oxidation. Also, the alloy layer 2
In the process of forming 1, the S in the Si substrate 1 is formed as described above.
Since the impurity X of the same type as that of the i-substrate 1 is introduced,
By increasing the impurity concentration of the Si substrate 1, the ohmic characteristics of the Si substrate 1 and the back surface electrode 2 can be improved. Further, the alloy layer 21 is formed on the back surface 12 of the Si substrate 1 by depositing the Au layer 21a containing the impurity X of the same type as that of the Si substrate 1 and then performing the heat treatment as described above. Containing or not containing X) Layer 2
2. Since the Ni layer 23 and the Au (containing X or not containing X) layer 24 are sequentially deposited by vapor deposition, the Ni layer 2
The formation of an alloy layer of Ni of No. 3 and Si of the Si substrate 1 is prevented. Therefore, it is possible to prevent the formation of an alloy layer of Si and Ni that hinders good ohmic characteristics. The Si substrate 1 used in this case may be N type or P type. Further, as described above, the selection range of the impurity X contained in Au is wide. FIG. 6 shows the voltage V-current I characteristic of the back surface electrode 2 of the above-described embodiment. In FIG. 6, as in the Au layers, Au containing Sb exhibits good ohmic characteristics. On the other hand, when Au does not contain Sb, the voltage V-current I characteristic is non-linear. Further, the back surface electrode 2 of the above-described embodiment includes Au containing Sb disclosed in each of the prior art publications.
Layer, barrier metal layer such as Ti, Ta, W, Mo, Ni layer,
Of the metal systems of the Au (or Ag) layer, Ti, Ta,
Even if the barrier metal layer such as W or Mo is omitted, the same effect and reliability can be obtained, so that the material cost and the number of steps can be reduced. The above-described embodiment of the present invention can be applied to a semiconductor device such as a power transistor having a back surface as an electrode.
【００１０】[0010]
【発明の効果】以上詳細に説明したように、本発明の半
導体装置及びその製造方法によれば、Ｔｉ、Ｔａ、Ｗ、
Ｍｏ等を使用しないで、半導体装置の裏面電極のオーミ
ック特性を著しく改良することができ、またこの裏面電
極の接触抵抗を小さくできる。そのため半導体装置の製
造工程において、材料費及び工程数を削減することがで
きる。更に上述のように裏面電極の接触抵抗を小さくで
きるので、Ｔｉ、Ｔａ、Ｗ、Ｍｏ等を使用しないで電力
用半導体装置の特性の低下を防ぐことができる。As described in detail above, according to the semiconductor device and the method of manufacturing the same of the present invention, Ti, Ta, W,
By not using Mo or the like, the ohmic characteristics of the back surface electrode of the semiconductor device can be remarkably improved, and the contact resistance of the back surface electrode can be reduced. Therefore, the material cost and the number of steps can be reduced in the manufacturing process of the semiconductor device. Further, since the contact resistance of the back electrode can be reduced as described above, it is possible to prevent deterioration of the characteristics of the power semiconductor device without using Ti, Ta, W, Mo or the like.
【図１】前記本発明の一実施例の製造方法を示す断面図
である。FIG. 1 is a cross-sectional view showing the manufacturing method of the embodiment of the present invention.
【図２】前記本発明の一実施例の製造方法を示す断面図
であり、図１の続きを示すものである。FIG. 2 is a cross-sectional view showing the manufacturing method of the embodiment of the present invention, which is a continuation of FIG.
【図３】前記本発明の一実施例の製造方法を示す断面図
であり、図２の続きを示すものである。3 is a cross-sectional view showing the manufacturing method of the embodiment of the present invention, which is a continuation of FIG.
【図４】前記本発明の一実施例の製造方法を示す断面図
であり、図３の続きを示すものである。FIG. 4 is a cross-sectional view showing the manufacturing method of the embodiment of the present invention, which is a continuation of FIG.
【図５】前記本発明の一実施例の裏面電極をハンダ付け
した状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state where the back surface electrode of the embodiment of the present invention is soldered.
【図６】前記本発明の一実施例の特性を示す図である。FIG. 6 is a diagram showing characteristics of the embodiment of the present invention.
【図７】従来例の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing a manufacturing method of a conventional example.
【図８】前記従来例の製造方法を示す断面図であり、図
７の続きを示すものである。FIG. 8 is a cross-sectional view showing the manufacturing method of the conventional example, which is a continuation of FIG.
【図９】前記従来例の製造方法を示す断面図であり、図
８の続きを示すものである。9 is a cross-sectional view showing the manufacturing method of the conventional example, which is a continuation of FIG.
【図１０】前記従来例の裏面電極をハンダ付けした状態
を示す断面図である。FIG. 10 is a cross-sectional view showing a state in which the back surface electrode of the conventional example is soldered.
１ シリコン基板 １２ シリコン基板の裏面 ２ 裏面電極 ２１ 合金層 ２１ａ 不純物を含む金層 ２２ 金層 ２３ ニッケル層 1 Silicon Substrate 12 Back Side of Silicon Substrate 2 Back Side Electrode 21 Alloy Layer 21a Gold Layer Containing Impurities 22 Gold Layer 23 Nickel Layer
Claims (2)
前記不純物と同型の不純物及びシリコンを含む合金層、
金のみもしくは金及び前記不純物と同型の不純物を含む
層、ニッケル層を順次積層形成したことを特徴とする半
導体装置。1. Gold on the back surface of a silicon substrate containing impurities,
An alloy layer containing impurities of the same type as the impurities and silicon,
A semiconductor device characterized in that only gold or a layer containing gold and an impurity of the same type as the above impurities, and a nickel layer are sequentially formed.
記不純物と同型の不純物を含む金層を形成した後に、熱
処理して前記不純物と同型の不純物を前記シリコン基板
中に導入するとともに、前記シリコン基板の裏面に金、
前記不純物と同型の不純物及びシリコンを含む合金層を
形成する第一の工程と、 この合金層の前記シリコン基板と反対側の面に金のみも
しくは金及び前記不純物と同型の不純物を含む層を形成
する第二の工程と、 前記金のみもしくは金及び前記不純物と同型の不純物を
含む層の前記合金層と反対側の面にニッケル層を形成す
る第三の工程とを含むことを特徴とする半導体装置の製
造方法。2. A gold layer containing impurities of the same type as the impurities is formed on the back surface of the silicon substrate containing impurities, and then heat treated to introduce impurities of the same type as the impurities into the silicon substrate. Gold on the back of the board,
First step of forming an alloy layer containing impurities and silicon of the same type as the impurities, and forming a layer containing only gold or gold and impurities of the same type as the impurities on the surface of the alloy layer opposite to the silicon substrate. And a third step of forming a nickel layer on the surface opposite to the alloy layer of the layer containing only gold or the same type of impurities as gold and the impurities. Device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21557992A JPH0637301A (en) | 1992-07-20 | 1992-07-20 | Semiconductor device and fabrication of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21557992A JPH0637301A (en) | 1992-07-20 | 1992-07-20 | Semiconductor device and fabrication of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0637301A true JPH0637301A (en) | 1994-02-10 |
Family
ID=16674779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21557992A Pending JPH0637301A (en) | 1992-07-20 | 1992-07-20 | Semiconductor device and fabrication of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0637301A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5120384A (en) * | 1989-05-25 | 1992-06-09 | Matsushita Electric Works, Ltd. | Method of manufacturing multilayer laminate |
| JP2007194514A (en) * | 2006-01-23 | 2007-08-02 | Mitsubishi Electric Corp | Method for manufacturing semiconductor device |
| JP2010021171A (en) * | 2008-07-08 | 2010-01-28 | Renesas Technology Corp | Method for manufacturing semiconductor device, and semiconductor manufacturing apparatus used for the same |
-
1992
- 1992-07-20 JP JP21557992A patent/JPH0637301A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5120384A (en) * | 1989-05-25 | 1992-06-09 | Matsushita Electric Works, Ltd. | Method of manufacturing multilayer laminate |
| JP2007194514A (en) * | 2006-01-23 | 2007-08-02 | Mitsubishi Electric Corp | Method for manufacturing semiconductor device |
| US8183144B2 (en) | 2006-01-23 | 2012-05-22 | Mitsubishi Electric Corporation | Method of manufacturing semiconductor device |
| JP2010021171A (en) * | 2008-07-08 | 2010-01-28 | Renesas Technology Corp | Method for manufacturing semiconductor device, and semiconductor manufacturing apparatus used for the same |
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