JPH0328822B2 - - Google Patents

Info

Publication number
JPH0328822B2
JPH0328822B2 JP57129781A JP12978182A JPH0328822B2 JP H0328822 B2 JPH0328822 B2 JP H0328822B2 JP 57129781 A JP57129781 A JP 57129781A JP 12978182 A JP12978182 A JP 12978182A JP H0328822 B2 JPH0328822 B2 JP H0328822B2
Authority
JP
Japan
Prior art keywords
layer
augesb
semiconductor chip
auge
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57129781A
Other languages
Japanese (ja)
Other versions
JPS5919335A (en
Inventor
Mitsuo Kobayashi
Toshio Tetsuya
Tsukasa Hatsutori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP12978182A priority Critical patent/JPS5919335A/en
Publication of JPS5919335A publication Critical patent/JPS5919335A/en
Publication of JPH0328822B2 publication Critical patent/JPH0328822B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に係り、特に半導体チツプ
を配設台に取着するのに好適な構造の半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure suitable for mounting a semiconductor chip on a mounting table.

〔発明の技術的背景〕[Technical background of the invention]

電気的機能を有する半導体チツプをリードフレ
ームやステムなどの配設台に取着する方法は、従
来たとえば特開昭55−19805号に記載されたもの
がある。すなわち、第１図に示すように、ｐ−ｎ
接合などを形成した半導体チツプ１の配設台取着
面にバナジウム（Ｖ）層２を形成し、このＶ層２
上にニツケル（Ni）層３を形成し、このNi層３
上に金、ゲルマニウムを主成分とするAuGeSb層
４を形成し、このAuGeSb層４上にAu層５をそ
れぞれ蒸着により形成する。このような積層構造
のAuGeSb層４をろう材として配設台６にマウン
トしていた。なお、上記積層構造としてチタニウ
ム（Ti）−銅（Cu）−AuGeSb−Auのものもあ
る。 A conventional method for attaching a semiconductor chip having electrical functions to a mounting base such as a lead frame or a stem is described in, for example, Japanese Patent Application Laid-Open No. 19805-1983. That is, as shown in FIG.
A vanadium (V) layer 2 is formed on the mounting surface of the semiconductor chip 1 on which the bonding etc. have been formed, and this V layer 2 is
A nickel (Ni) layer 3 is formed on top, and this Ni layer 3
An AuGeSb layer 4 containing gold and germanium as main components is formed thereon, and an Au layer 5 is formed on this AuGeSb layer 4 by vapor deposition. The AuGeSb layer 4 having such a laminated structure was mounted on a mounting table 6 as a brazing material. Note that there is also a titanium (Ti)-copper (Cu)-AuGeSb-Au layered structure.

〔背景技術の問題点〕[Problems with background technology]

上記のようにマウントした半導体素子を樹脂封
止したNPNトランジスタには次のような欠点が
ある。前者つまりＶ−Ni−AuGeSb−Auの積層
構造では、VCE（sat）などの電気特性は満足する
が、プレツシヤークツカーテスト（PCT）を300
時間程度行うとNi層が腐食される場合がある。
また、後者つまりTi−Cu−AuGeSb−Auの積層
構造では、AuGeをろう材としてマウントした場
合、PCTでの電極腐食は問題ないが、Ti−Cu層
が厚いとVCE（sat）などの電気的特性が満足せず
悪く、さらにTi−Cu層が薄いとCu層がAuGeと
合金化し、更に著しい場合にはAuGeSiCuあるい
はAuGeSiCuTiの合金層が形成され、熱衝激試験
でチツプクラツクを生じることがあるなどの問題
があつた。 The NPN transistor in which the mounted semiconductor element is sealed with resin as described above has the following drawbacks. The former, that is, the V-Ni-AuGeSb-Au stacked structure, satisfies the electrical characteristics such as V CE (sat), but the pressure test (PCT) is 300
The Ni layer may be corroded if the process is continued for a period of time.
In addition, in the latter layered structure of Ti-Cu-AuGeSb-Au, if AuGe is mounted as a brazing material, there is no problem with electrode corrosion in PCT, but if the Ti-Cu layer is thick, electrical problems such as V CE (sat) In addition, if the Ti-Cu layer is thin, the Cu layer will alloy with AuGe, and in severe cases, an alloy layer of AuGeSiCu or AuGeSiCuTi may be formed, which may cause chip cracks in thermal shock tests. There were problems such as.

〔発明の目的〕 本発明は上記事情に鑑みてなされたもので、そ
の目的とするところは、電気的特性を低下させる
ことなく、PCTでの電極腐食および熱衝激試験
でのチツプクラツクを防止する半導体装置を提供
することにある。[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to prevent electrode corrosion in PCT and chip cracks in thermal shock tests without deteriorating electrical characteristics. The purpose of the present invention is to provide semiconductor devices.

〔発明の概要〕[Summary of the invention]

本発明は、配設台にマウントされる半導体チツ
プ間にチタニウム（Ti）層および金、ゲルマニ
ウム（Au Ge）を主成分とする合金層の積層構
造を設けた半導体装置を構成することにより、
PCT試験に対して耐え、チツプクラツクの発生
を減少させたものである。 The present invention provides a semiconductor device in which a laminated structure of a titanium (Ti) layer and an alloy layer mainly composed of gold and germanium (Au Ge) is provided between semiconductor chips mounted on a mounting table.
It withstood the PCT test and reduced the occurrence of chip cracks.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例について図面を参照し
て説明する。なお、この実施例は、第２図Ａに示
すように配設台、たとえばリードフレーム２１の
半導体チツプ取着リード２２に半導体チツプ２３
をマウントし、この半導体チツプ２３の電極から
ワイヤ２４によりボンデイングする場合について
説明する。第２図Ｂ，Ｃにおいて、一導電形半導
体基板、たとえばｎ形シリコンウエハ３１の内表
面にそれぞれ離散してｐ形不純物を注入すること
により、ｐ形領域３２を複数個島状に形成し、こ
の各島状のｐ形領域３２内の一部にｎ形不純物を
注入することにより、ｎ形領域３３を形成し、多
数のNPNトランジスタ３４を構成する。このト
ランジスタ３４のリードフレーム２１へのマウン
ト側面上にTi層３５を厚さ約1000Å蒸着する。
このTi層３５上にAuGeを主成分とする層、たと
えばAuGe（12wt％）、Sb（0.1wt％）の合金層３６
を厚さ約1.5μｍ蒸着し、この合金層３６上にAu
層３７を厚さ約1000Å蒸着する（第２図Ｂ）。こ
のように処理したウエハを上面からダイヤモンド
スクライプ法により個々のチツプに分割する。こ
の分割により得られた半導体チツプ２３を第２図
Ａに図示したようにリードフレームの取着リード
２２にマウントする（第２図Ｃ）。すなわち、
AuGeSbの合金層３６をろう材として取着リード
２２にマウントする。このようにして得られた
NPNトランジスタのVCE（sat）特性は、従来のＶ
−AuGeSb−Auの積層構造のNPNトランジスタ
と何ら差がなく、PCT試験500時間でも蒸着膜の
腐食は一切起らなかつた。このような積層構造が
VCE（sat）、腐食などの耐湿性、チツプクラツクの
減少などの作用効果を有する理由は明らかではな
いが、次の様な理由によるものと思われる。 An embodiment of the present invention will be described below with reference to the drawings. In addition, in this embodiment, as shown in FIG.
A case will be described in which the semiconductor chip 23 is mounted and bonded from the electrodes of the semiconductor chip 23 with the wires 24. In FIGS. 2B and 2C, a plurality of p-type regions 32 are formed in the form of islands by discretely implanting p-type impurities into the inner surface of a semiconductor substrate of one conductivity type, for example, an n-type silicon wafer 31, and By implanting an n-type impurity into a part of each island-shaped p-type region 32, an n-type region 33 is formed, and a large number of NPN transistors 34 are formed. A Ti layer 35 having a thickness of about 1000 Å is deposited on the side surface of the transistor 34 mounted on the lead frame 21.
On this Ti layer 35, a layer containing AuGe as a main component, for example, an alloy layer 36 of AuGe (12wt%) and Sb (0.1wt%)
Au is deposited to a thickness of approximately 1.5 μm on this alloy layer 36.
Layer 37 is deposited to a thickness of about 1000 Å (FIG. 2B). The wafer thus processed is divided into individual chips from the top surface by a diamond scribing method. The semiconductor chip 23 obtained by this division is mounted on the mounting leads 22 of a lead frame as shown in FIG. 2A (FIG. 2C). That is,
The AuGeSb alloy layer 36 is mounted on the attachment lead 22 as a brazing material. obtained in this way
The V CE (sat) characteristics of an NPN transistor are
There is no difference from the NPN transistor with the -AuGeSb-Au stacked structure, and no corrosion of the deposited film occurred even after 500 hours of PCT testing. This kind of laminated structure
The reason why it has such effects as V CE (sat), moisture resistance against corrosion, and chip crack reduction is not clear, but it is thought to be due to the following reasons.

(1) 耐湿性について 従来のＶ−Ni−AuGeSb−Auの積層構造の
ようにNiとAuGeSbとの中のAuが湿度の高い
雰囲気中で接すると局部電池が形成され、Ni
層が流電腐食を起こしたものと推定される。こ
れに対し、前述した従来のTi−Cu−AuGeSb
−Au積層構造とすると、CuあるいはTiとAu
との接触による電池作用は殆ど起らず、Cuま
たはTiが腐食されることはない。(1) Moisture resistance When Ni and Au in AuGeSb come into contact with each other in a humid atmosphere, as in the conventional V-Ni-AuGeSb-Au stacked structure, a local battery is formed, and the Ni
It is presumed that the layer has undergone galvanic corrosion. In contrast, the conventional Ti−Cu−AuGeSb
−If the Au layered structure is used, Cu or Ti and Au
Almost no battery action occurs due to contact with Cu or Ti, and Cu or Ti is not corroded.

(2) VCE（sat）不良について Ti−Cu−AuGeSb−Au積層構造の場合、
NPNトランジスタはAuGeSb中のSbがSiペレ
ツト中に拡散し、VCE（sat）特性を満している
ため、Ti−Cu蒸着膜の厚さを同一にし、厚さ
も5000Å以下、厚くしても1μｍ以下に押える
必要がある。このようなTi−Cuの膜厚にすれ
ば、VCE（sat）不良の発生は殆ど押えることが
可能となる。(2) Regarding V CE (sat) failure In case of Ti-Cu-AuGeSb-Au stacked structure,
In NPN transistors, the Sb in AuGeSb diffuses into the Si pellet and satisfies the V CE (sat) characteristics, so the thickness of the Ti-Cu deposited film is the same, and the thickness is less than 5000 Å, and even if it is thicker, it is 1 μm. It is necessary to keep it below. With such a Ti-Cu film thickness, it is possible to almost suppress the occurrence of V CE (sat) defects.

(3) チツプクラツクについて Ti−Cu層を1μｍ以下に押えた場合、AuGe
もTi−Cu層を拡散し、AuGeSi合金ができる場
合がある。ところが、このAuGeSi合金が形成
されると、熱衝激試験で非常にチツプクラツク
を発生しやすくなる。(3) Regarding chip cracks When the Ti-Cu layer is suppressed to 1 μm or less, AuGe
may also diffuse through the Ti-Cu layer to form an AuGeSi alloy. However, once this AuGeSi alloy is formed, it becomes extremely susceptible to chip cracks in thermal shock tests.

これら３点の欠点を解決するために特にNiの
使用をさけ、さらにAuGeの特に拡散しやすいCu
の使用もさけた電極構造としたもので、この発明
のTi−AuGe（Sb）−Auの積層構造は、Tiの膜厚
をAuGeが半導体チツプたとえばシリコンへ拡散
するのを防止する厚さにし、Sbだけが半導体チ
ツプへ拡散可能なTiの膜厚に設定することが望
ましく、Tiの膜厚は1000Å乃至1μｍが最適であ
る。また、AuGe（Sb）の膜厚は、半導体チツプ
をリードフレームにマウントするろう材として必
要な厚さでよく、その厚さは1μｍもあれば充分
である。このAuGe（Sb）はろう材として用いる
ので、半導体チツプ側にあらかじめ設けた上記実
施例と異なり、リードフレームに設けてもよい。
なお、前記実施例において、Au層３７はAuGe
（Sb）中のGeやSbの酸化防止のための被膜であ
り、蒸着後１週間以内にリードフレームにマウン
トする場合には全くなくてもよい。 In order to solve these three drawbacks, we especially avoided the use of Ni, and furthermore, we
The Ti-AuGe(Sb)-Au laminated structure of the present invention has a Ti film thickness that prevents AuGe from diffusing into a semiconductor chip, such as silicon, and It is desirable to set the Ti film thickness to such a value that only Sb can diffuse into the semiconductor chip, and the optimal Ti film thickness is 1000 Å to 1 μm. Further, the thickness of the AuGe (Sb) film may be the thickness required as a brazing material for mounting a semiconductor chip on a lead frame, and a thickness of 1 μm is sufficient. Since this AuGe (Sb) is used as a brazing material, it may be provided on the lead frame, unlike the above embodiment in which it is provided in advance on the semiconductor chip side.
Note that in the above embodiment, the Au layer 37 is made of AuGe.
This is a coating to prevent oxidation of Ge and Sb in (Sb), and may not be present at all if it is mounted on a lead frame within one week after deposition.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、電気的特
性を劣化させることなく、PCTでの電極腐食お
よび熱衝激試験でのチツプクラツクを防止できる
半導体装置を提供できる。 As explained above, according to the present invention, it is possible to provide a semiconductor device that can prevent electrode corrosion in PCT and chip cracks in thermal shock testing without deteriorating electrical characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第１図Ａ，Ｂは従来の半導体装置の半導体チツ
プをろう材によりマウントする構造説明図、第２
図は本発明の一実施例を説明するための図で、Ａ
図は一部切欠斜視図、Ｂ図およびＣ図は断面構造
図である。 ２１……リードフレーム、２２……半導体チツ
プ取着リード、２３……半導体チツプ、２４……
ワイヤ、３１……ｎ形シリコンウエハ、３２……
ｐ形領域、３３……ｎ形領域、３４……NPNト
ランジスタ、３５……Ti層、３６……AuGe（Sb）
層、３７……Au層。 Figures 1A and 1B are structural explanatory diagrams for mounting the semiconductor chip of a conventional semiconductor device using a brazing material.
The figure is a diagram for explaining one embodiment of the present invention, and A
The figure is a partially cutaway perspective view, and figures B and C are cross-sectional structural views. 21...Lead frame, 22...Semiconductor chip attachment lead, 23...Semiconductor chip, 24...
Wire, 31... N-type silicon wafer, 32...
p-type region, 33...n-type region, 34...NPN transistor, 35...Ti layer, 36...AuGe (Sb)
Layer, 37...Au layer.

Claims (1)

【特許請求の範囲】 １ Ti層及びAuGeSb層の積層構造を配設台と半
導体チツプとの間に設けてなり、前記Ti層の厚
さは1000Å乃至1μｍであることを特徴とする半
導体装置。 ２ 前記積層構造に酸化防止層を設けた特許請求
の範囲第１項に記載の半導体装置。[Scope of Claims] 1. A semiconductor device characterized in that a laminated structure of a Ti layer and an AuGeSb layer is provided between a mounting table and a semiconductor chip, and the thickness of the Ti layer is 1000 Å to 1 μm. 2. The semiconductor device according to claim 1, wherein the stacked structure is provided with an oxidation prevention layer.
JP12978182A 1982-07-26 1982-07-26 Semiconductor device Granted JPS5919335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12978182A JPS5919335A (en) 1982-07-26 1982-07-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12978182A JPS5919335A (en) 1982-07-26 1982-07-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5919335A JPS5919335A (en) 1984-01-31
JPH0328822B2 true JPH0328822B2 (en) 1991-04-22

Family

ID=15018059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12978182A Granted JPS5919335A (en) 1982-07-26 1982-07-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5919335A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766927B2 (en) * 1988-11-18 1995-07-19 三洋電機株式会社 Method for manufacturing semiconductor pellet and semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519806A (en) * 1978-07-28 1980-02-12 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519806A (en) * 1978-07-28 1980-02-12 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
JPS5919335A (en) 1984-01-31

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